EN EL SIGUIENTE CÓDIGO SE PRESENTA UN CONTADOR CON DOS PROCESOS SEPARADOS, UNO PARA LA PARTE COMBINACIONAL Y EL OTRO PARA LA PARTE SECUENCIAL. library ieee; use ieee.std_logic_1164.all; entity CONT4 is port ( clk: in std_logic; rst: in std_logic; f: out std_logic_vector(1 downto 0)); end CONT4; architecture ejem of CONT4 is signal Qp, Qs: std_logic_vector (1 downto 0); begin comb: process(Qp) begin case Qp is when "00" => Qs <= "01"; when "01" => Qs <= "10"; when "10" => Qs <= "11"; when others => Qs <= "00"; end case; f <= Qp; end process comb; sec: process(rst, clk) begin if (rst = '1') then Qp <= "00"; elsif (clk'event and clk='1') then Qp <= Qs; end if; end process sec; end ejem;