use IEEE.STD_LOGIC_1164.ALL

Decodificador a 7 segmentos.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity deco7seg is
Port ( entrada : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (6 downto 0));
end deco7seg;
architecture Behavioral of deco7seg is
begin
salida<=
"0000001" when entrada="000" else
"1001111" when entrada="001" else
"0010010" when entrada="010" else
"0000110" when entrada="011" else
"1001100" when entrada="100" else
"0100100" when entrada="101" else
"0100000" when entrada="110" else
"0001101" when entrada="111" else
"1111111";
end Behavioral;
Simulación:
.
Codificador
Multiplexor 4 a 1
Demultiplexor
entity demulti is port(
entra:
in bit_vector(7 downto 0);
control: in bit_vector(1 downto 0);
enable: in bit;
a,b,c,d: out bit_vector(7 downto 0)
);
end demulti;
architecture archdemul of demulti is
begin
process (entra, control, enable)
begin
if enable='1' then a<="11111111";
b<="11111111";
c<=(others=>'1');
d<=(others=>'1');
elsif enable='0' then
case control is
when "00" => a <= entra;
when "01" => b <= entra;
when "10" => c <= entra;
when others => d <= entra;
end case;
end if;
end process;
end archdemul;