1) PUERTA TRIESTADO (combinacional): 2) MULTIPLEXOR

1) PUERTA TRIESTADO (combinacional):
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY triestado IS
PORT (op, entrada: IN std_logic;
salida: OUT std_logic);
END triestado;
ARCHITECTURE synth OF triestado IS
BEGIN
PROCESS(entrada,op)
BEGIN
IF op='1' THEN
salida <= entrada;
ELSE
salida <= 'Z';
END IF;
END PROCESS;
END ARCHITECTURE synth;
2) MULTIPLEXOR (combinacional):
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux IS
PORT (a,b,c : IN std_logic_vector(3 DOWNTO 0);
sel
: IN std_logic_vector(1 DOWNTO 0);
salida : OUT std_logic_vector(3 DOWNTO 0));
END mux;
ARCHITECTURE synth OF mux IS
BEGIN
PROCESS (sel, a, b, c) IS
BEGIN
CASE sel IS
WHEN "00" => salida <= (others => '0');
WHEN "01" => salida <= a;
WHEN "10" => salida <= b;
WHEN "11" => salida <= c;
WHEN OTHERS => salida <= (others => '0');
END CASE;
END PROCESS;
END synth;
3) SUMADOR (combinacional):
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY sum IS
PORT (a : IN std_logic_vector(3 DOWNTO 0);
b : IN std_logic_vector(3 DOWNTO 0);
salida : OUT std_logic_vector(4 DOWNTO 0));
END sum;
ARCHITECTURE synth OF sum IS
BEGIN
PROCESS (a, b) IS
BEGIN
salida <= (‘0’ & a) + (‘0’ & b);
END PROCESS;
END synth;
4) CONTADORES DE 8 Y 32 BITS (secuenciales):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY count IS
PORT (clk : IN std_logic;
rst : IN std_logic;
enable1 : IN std_logic;
enable2 : IN std_logic;
reset1 : IN std_logic;
reset2 : IN std_logic;
count1 : OUT std_logic_vector(7 DOWNTO 0);
count2 : OUT std_logic_vector(31 DOWNTO 0));
END count;
ARCHITECTURE synth OF sum IS
SIGNAL cnt1 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL cnt2 : std_logic_vector(31 DOWNTO 0) := (others => '0');
SIGNAL en1 : boolean := false;
SIGNAL en2 : boolean := false;
BEGIN
pSeq : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
cnt1 <= (others => '0');
cnt2 <= (others => '0');
ELSIF clk='1' AND clk'event THEN
IF en1 THEN
cnt1 <= cnt1 + 1;
END IF;
IF en2 THEN
cnt2 <= cnt2 + 1;
END IF;
END IF;
END PROCESS;
pCom : PROCESS (enable1, enable2) IS
BEGIN
IF enable1 = '1' THEN
en1 <= NOT en1;
END IF;
IF enable2 = '1' THEN
en2 <= NOT en2;
END IF;
END PROCESS;
count1 <= cnt1;
count2 <= cnt2;
END synth;
5) BIESTABLE (secuencial):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY biestable IS
PORT (clk : IN std_logic;
rst : IN std_logic;
a : IN std_logic_vector(31 DOWNTO 0);
b: OUT std_logic_vector(31 DOWNTO 0));
END biestable;
ARCHITECTURE synth OF biestable IS
BEGIN
pSeq : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
b <= (others => '0');
ELSIF clk='1' AND clk'event THEN
b <= a;
END IF;
END PROCESS;
END synth;
6) ALU (combinacional):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY alu IS
PORT( a : IN std_logic_vector(7 DOWNTO 0); --entrada 2
b : IN std_logic_vector(7 DOWNTO 0); --entrada 1
proceso : IN std_logic_vector(3 DOWNTO 0); -- tipo de operacion
c : OUT std_logic_vector(15 DOWNTO 0));
END alu;
ARCHITECTURE synth OF alu IS
BEGIN
PROCESS (a, b, proceso)
BEGIN
CASE proceso IS
WHEN "0000" => c <= "0000000" & (a + b);
WHEN "0001" =>
IF a < b THEN
c <= "1000000" & (b - a);
ELSE
c <= "00000000" & (a - b);
END IF;
WHEN "0010" =>
........
WHEN OTHERS => null;
END CASE;
END PROCESS;
END synth;
7) Máquina de estados (secuencial):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY maquina_estados IS
PORT (clk : IN std_logic;
rst : IN std_logic;
a : OUT std_logic;
b : OUT std_logic;
estado : OUT std_logic_vector(3 downto 0));
END maquina_estados;
ARCHITECTURE synth OF maquina_estados IS
SIGNAL pstate, n_state : std_logic_vector(3 downto 0);
BEGIN
-- maquina de estados
PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
pstate <= "0000";
ELSIF clk = '1' AND clk'event THEN
pstate <= n_state;
END IF;
END PROCESS;
estado <= pstate;
n_state <= "0001" WHEN
"0010" WHEN
"0011" WHEN
"0100" WHEN
"0101" WHEN
"0011" WHEN
"0111" WHEN
"1000" WHEN
"1001" WHEN
"0000";
(pstate
(pstate
(pstate
(pstate
(pstate
(pstate
(pstate
(pstate
(pstate
a <= '1' WHEN
'0' WHEN
'0' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'0';
pstate
pstate
pstate
pstate
pstate
pstate
pstate
pstate
pstate
pstate
=
=
=
=
=
=
=
=
=
=
"0000"
"0001"
"0010"
"0011"
"0100"
"0101"
"0110"
"0111"
"1000"
"1001"
ELSE --0
ELSE --1
ELSE --2
ELSE --3
ELSE --4
ELSE --5
ELSE --6
ELSE --7
ELSE --8
ELSE --9
b <= '1' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'0' WHEN
'0' WHEN
'1' WHEN
'1' WHEN
'1' WHEN
'0';
END synth;
pstate
pstate
pstate
pstate
pstate
pstate
pstate
pstate
pstate
pstate
=
=
=
=
=
=
=
=
=
=
"0000"
"0001"
"0010"
"0011"
"0100"
"0101"
"0110"
"0111"
"1000"
"1001"
ELSE --0
ELSE --1
ELSE --2
ELSE --3
ELSE --4
ELSE --5
ELSE --6
ELSE --7
ELSE --8
ELSE --9
=
=
=
=
=
=
=
=
=
"0000")
"0001")
"0010")
"0011")
"0100")
"0101")
"0011")
"0111")
"1000")
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE