Etapas de ejecución de las instrucciones (I)

Etapas de ejecución de las instrucciones (I)
Etapa 1: Búsqueda del código de operación (fetch)
IR = Memory[PC]
PC = PC + 4
Etapa 2: Decodificación y acceso a operandos
A = Reg[rs]
B = Reg[rt]
ALUout = PC + extensión-signo(IR[15-0]) << 2
Etapa 3: Ejecución, cálculo de dirección o terminación del salto
• Instrucción tipo R (and, or, add, sub,slt)
ALUOut = A op B
• Referencia a memoria (lw/sw)
ALUOut = A + extensión-signo(IR[15-0])
• Salto (beq)
if (A == B) PC = ALUOut
• Bifurcación (j)
PC = PC[31-28] || IR[25-0] << 2
Diseño de la ruta de datos multiciclo
8
Etapas de ejecución de las instrucciones (II)
Etapa 4: Acceso a memoria/fin de ejecución
instrucción tipo R
• Referencia a memoria
MDR = Memory[ALUOut]
o
Memory[ALUOut] = B
• Fin ejecución instrucción tipo R
Reg[rd] = ALUOut
Etapa 5: Fin de lectura en memoria
Reg[rt] = MDR
Diseño de la ruta de datos multiciclo
9
FIGURA 5.36 Una visión de alto nivel del control mediante una
máquina de estados finitos
1
FIGURA 5.37 La búsqueda de la instrucción y la fase de
decodificación/búsqueda de registros son idénticas para todas las
instrucciones
2
FIGURA 5.38 La máquina de estados finitos para controlar las
instrucciones de acceso a memoria tiene cuatro estados
3
FIGURA 5.39 Las instrucciones de tipo R pueden realizarse mediante
una máquina de estados finitos sencilla de sólo dos estados
4
FIGURA 5.40 La instrucción de salto condicional requiere un único
estado
5
FIGURA 5.41 La instrucción jump requiere un único estado
FIGURA 5.42 El control completo de la máquina de estados finitos
para el camino de datos multiciclo
[página siguiente]
6
7
FIGURA 5.43 Los controladores de máquinas de estados finitos
suelen estar realizados mediante un bloque de lógica combinatoria y
un registro para guardar el estado actual
8
Instruction decode/
Register fetch
Instruction fetch
T1
=
(Op
=
(Op
') or
'LW
Memory reference FSM
(Figure 5.38)
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
=
(Op
')
'SW
R-type FSM
(Figure 5.39)
)
ype
R-t
Branch FSM
(Figure 5.40)
(Op = 'JMP')
Start
1
'BE
Q'
)
Instrucción de CARGA (LW): Etapa 1
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
(O
p=
0
Jump FSM
(Figure 5.41)
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5–0]
0
M
26
Instruction[25–0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25–21]
Read
register 1
Instruction
[20–16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15–0]
Instruction
register
Instruction
[15–0]
Memory
data
register
0
M
Instruction u
x
[15–11]
1
B
4
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
Jump
address [31-0]
1u
x
2
PC [31-28]
0
M
u
x
1
A
28
Zero
ALU ALU
result
ALUOut
0
1M
u
2 x
3
ALU
control
Instruction [5–0]
Diseño de la ruta de datos multiciclo
10
Instruction decode/
Register fetch
Instruction fetch
T2
=
(Op
=
(Op
') or
'LW
Memory reference FSM
(Figure 5.38)
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
=
(Op
')
'SW
R-type FSM
(Figure 5.39)
)
ype
R-t
Branch FSM
(Figure 5.40)
(Op = 'JMP')
Start
1
'BE
Q'
)
Instrucción de CARGA (LW): Etapa 2
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
(O
p=
0
Jump FSM
(Figure 5.41)
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5–0]
0
M
26
Instruction[25–0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25–21]
Read
register 1
Instruction
[20–16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15–0]
Instruction
register
Instruction
[15–0]
Memory
data
register
0
M
Instruction u
x
[15–11]
1
B
4
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
Jump
address [31-0]
1u
x
2
PC [31-28]
0
M
u
x
1
A
28
Zero
ALU ALU
result
ALUOut
0
1M
u
2 x
3
ALU
control
Instruction [5–0]
Diseño de la ruta de datos multiciclo
11
Instrucción de CARGA (LW): Etapa 3
T3
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5–0]
0
M
26
Instruction[25–0]
0
M
u
x
1
Instruction
[31-26]
Address
Memory
MemData
Instruction
[20–16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15–0]
Memory
data
register
0
M
Instruction u
x
[15–11]
1
0
M
u
x
1
A
B
4
0
M
u
x
1
(Op = 'LW') or (Op = 'SW')
Memory address computation
2
Zero
ALU ALU
result
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUOut
0
1M
u
2 x
3
')
'SW
Read
register 1
PC [31-28]
p=
(O
Write
data
x
2
From state 1
Instruction
[25–21]
Instruction
[15–0]
Instruction
register
1u
Jump
address [31-0]
(Op = 'LW')
PC
Shift
left 2
28
3
16
Sign
extend
32
Memory
access
Memory
access
5
MemRead
IorD = 1
Shift
left 2
ALU
control
MemWrite
IorD = 1
Write-back step
Instruction [5–0]
4
RegWrite
MemtoReg = 1
RegDst = 0
Diseño de la ruta de datos multiciclo
To state 0
(Figure 5.37)
12
Instrucción de CARGA (LW): Etapa 4
T4
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5–0]
0
M
26
Instruction[25–0]
0
M
u
x
1
Instruction
[31-26]
Address
Memory
MemData
Instruction
[20–16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15–0]
Memory
data
register
0
M
Instruction u
x
[15–11]
1
0
M
u
x
1
A
B
4
0
M
u
x
1
(Op = 'LW') or (Op = 'SW')
Memory address computation
2
Zero
ALU ALU
result
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALUOut
0
1M
u
2 x
3
')
'SW
Read
register 1
PC [31-28]
p=
(O
Write
data
x
2
From state 1
Instruction
[25–21]
Instruction
[15–0]
Instruction
register
1u
Jump
address [31-0]
(Op = 'LW')
PC
Shift
left 2
28
3
16
Sign
extend
32
Memory
access
Memory
access
5
MemRead
IorD = 1
Shift
left 2
ALU
control
MemWrite
IorD = 1
Write-back step
Instruction [5–0]
4
RegWrite
MemtoReg = 1
RegDst = 0
Diseño de la ruta de datos multiciclo
To state 0
(Figure 5.37)
13
Instrucción de CARGA (LW): Etapa 5
T5
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5–0]
0
M
26
Instruction[25–0]
0
M
u
x
1
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25–21]
Read
register 1
Instruction
[20–16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15–0]
Instruction
register
4
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
Zero
ALU ALU
result
(Op = 'LW') or (Op = 'SW')
ALUOut
Memory address computation
2
0
1M
u
2 x
3
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
ALU
control
')
'SW
Memory
data
register
B
From state 1
p=
(O
Instruction
[15–0]
0
M
Instruction u
x
[15–11]
1
x
2
PC [31-28]
0
M
u
x
1
A
1u
Jump
address [31-0]
(Op = 'LW')
PC
Shift
left 2
28
Memory
access
Memory
access
3
5
MemRead
IorD = 1
MemWrite
IorD = 1
Instruction [5–0]
Write-back step
4
RegWrite
MemtoReg = 1
RegDst = 0
Diseño de la ruta de datos multiciclo
To state 0
(Figure 5.37)
14