Dell-Loki-G-15-17-la-f611p-r10-032-pdf

A
B
C
D
E
PCB R1
ZZZ
DAA000FC010
COMPAL CONFIDENTIAL
1
PCB@
MODEL NAME : Loki-G 15/17
MB PCB PN : DAA000FC010
PWR/B PCB PN : DA4002L3010
IO/B PCB PN : DA6001XF010
w
e
i
v
UC1
UC1
CPU R1
UC1
1
CPU R3
SA0000BPJ1L
SA0000BPJ2L
i5@
i5@
UC1
SA0000BPZ1L
SA0000BPZ2L
i7@
i7@
e
r
Dell/Compal Confidential
2
L
L
2
Schematic Document
COFFEE LAKE H
N17P-G0/G1
E
D
3
3
Loki-G 15/17
Layout Dell logo
4
COPYRIGHT 2014
ALL RIGHT RESERVED
REV: X00
PWB: 9HTP8
A
r
o
F
2018-03-22
REV : 1.0 (A00)
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Cover Page
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
1
of
78
A
B
GB4-128
GPU
N17P-G0/G1
VRAM * 4
GDDR5
HDMI2.0
HDMI 2.0
Conn.
1
C
1.2V DDR4 2400 MHz
Intel
CFL-Lake-H
Processor
45W
32GB Max
BGA
DDI1 x4
E
DDRIV-DIMM X2
DDR4 ChannelA
DDR4 ChannelB
PEG 3.0 x8
IFPx
Re-Timer
PS8409A
D
w
e
i
v
15.6'' and 17.3"
HD / FHD
eDP1.2 x4
USB3.1 Gen1
USB3.1
TypeC
P41
USB2.0/CC
TPS65982DC
Thunderbolt
Alpine Ridge-SP
I2C/USB2.0
DMI x4
100MHz
5GB/s
PCI-E x4
Port 7-Port 10
M.2 Slot A Key-E
(WLAN+BT4.0)
RJ45
P33
P28
LOM
RTL8111H P33
PCI-E x1
(SATA/PCIe SSD)
P29
Port 1
Port 1
USB2.0
USB3.0
Port 3
Port 3
USB2.0
Port 2
Port 15
CNVi
PCI-E x1
Port 14
Intel
CNL-H-PCH
BGA 874 Balls
2
M.2 Slot C Key-M
USB2.0
USB3.0
PCI-E x4
Port 9-Port 12
SATA1A
USB2.0
Port 4
HM370
HDD
Conn.
L
L
SATA0B
P29
Main SPKR *2
P24
Universal
Audio Jack
HDA Codec
ALC3204
HD Audio
P23
P24
SPI Flash
(BIOS 32MB)
P17
3
E
D
SPI
SMBus
TPM
NPCT650
Reserved
P27
FFS
LNG2DMTR
P29
Reserved
4
128M*32 x4 =2G
256M*32 x4 =4G
A
r
o
F
I2C
Touch Pad
PS2
P26
LED
Port 5
USB2.0
Port 8
USB2.0
Port 6
e
r
Card Reader
RTS5170
P34
USB 3.0
Type-A
USB 2.0
Type-A
TPS65982DC
P32
P32
P32
Left
Left
Right
I/O Board
2
P28
Digital Camera
Conn.
P38
SD3.0
USB2.0
Port 9
Touch Panel
Conn.
P38
2 in 1
SD / MS
P34
I/O Board
Finger Print
3
M.2 Slot A Key-E
(WLAN+BT4.0)
P28
P16-22
eSPI
PWM
MEC 1416
KBC
USB2.0
USB 3.0
Type-A
1
P36
I2C
P37
FAN
P26
Thermal Sensor
NCT7718W P27
KB Conn.
P25
SMBus
4
Power Button
P37
Charger &
Battery P59/P60
AC Adaptor
P59
Power Button Board
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
D
Document Number
Rev
0.3
LA-F611P
Date:
B
Block Diagram
Thursday, March 22, 2018
E
Sheet
2
of
78
5
Refer Page 26
Board ID
4
2
1
HSIO port Alloction
USB3
Resistor
X00
10K
X01
17.8K
X02
27K
X03
37.4K
A00
49.9K
PCI EXPRESS
USB JUSB1 (Left Side)
Lane 1
DESTINATION
None
2
None
Lane 2
3
Lane 3
4
USB JUSB3 (Left Side)
None
5
6
1
D
3
DESTINATION
USB3
7
DESTINATION
None
None
8
None
None
9
None
Lane 4
None
10
None
None
Lane 5
None
None
Lane 6
None
Lane 7
None
Lane 8
None
w
e
i
v
Lane 9
USB2
C
DDI
1
DESTINATION
Lane 10
1
USB JUSB1 (Left Side)
Lane 11
2
USB JUSB2 (I/O)
Lane 12
3
USB JUSB3 (Left Side)
Lane 13
None (HDD)
4
Lane 14
LAN
5
TYPEC PD
CAMERA
Lane 15
6
Card Reader (I/O)
Lane 16
NGFF - WLAN
None
7
BT & CNVi BRI
Lane 17
None
4
None
8
Lane 18
None
5
None
9
Touch Screen
Finger Print
Lane 19
None
6
None
None
7
None
10
None
Lane 20
11
None
Lane 21
12
None
Lane 22
13
None
Lane 23
14
None
Lane 24
DESTINATION
Alpine Ridge
2
Alpine Ridge
3
HDMI2.0 LSPCON PS175
CLK_PCIE
5
r
o
F
DESTINATION
1a
0b
NGFF - SSD
HDD
1b
None (LAM)
2
None (WLAN)
None
3
CLK_REQ
0
1
TBT-AR
None
2
None
2
3
None
3
4
None
4
1
e
r
C
DESTINATION
TBT-AR
None
None
None
B
None
5
None
5
6
None
6
7
GPU
None
7
GPU
8
None
8
None (NVMe)
L
L
Alpine Ridge - SP
DESTINATION
SATA
0a
E
D
0
B
A
NGFF - NVMe SSD
D
None
None
9
NGFF - SSD
9
NVMe
10
None
10
None
11
None
11
None
12
None
12
None
13
None
13
None
14
LAN
14
LAN
15
WLAN
15
WLAN
Symbol Note :
: means Digital Ground
A
: means Analog Ground
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2017/01/06
Deciphered Date
2018/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Notes List
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
Thursday, March 22, 2018
1
Sheet
3
of
78
5
4
PJP901
VCCIO_EN
SY8286RAC
(PU901)
3
2
1
PJP902
+VCCIO
+VCCIOP
EN_VCCSTG_VCCPLL_OC
RZ67
APE8937GN2
(UZ16)
+1.2V_VCCPLL_OC
PJPM04
PJPM02
PJPM01
D
1.2V_VDDQ_EN
RT8207PGQW
(PUM01)
+1.2VP
SM_PG_CTRL
+1.2V_DDR
JDIMM1/JDIMM2
+0.6V_DDR_VTT
JDIMM1/JDIMM2
w
e
i
v
PJPM03
+0.6VSP
EN_VCCSTG_VCCPLL_OC
RZ48
TPS22961
(UZ9)
TPS22961
(UZ15)
PJPH01
+1.05VP
FUSE 1.5A_24V
(F1)
PJPW01
C
SY8180CRAC
(PU501)
+1.05VALW
RC251
1.35VGPUP
2.8A
+1.05V_XDP
0.24A
+VCCST
+1.35VS_VGA
PJP502
PJP503
EN_5V
+5VALW P
+5VALW
PJP301
SY8288BRAC
(PU301)
ADAPTER
+VCCST_OUT
PJPW03
PJPW02
DGPU_PW ROK
RT8816AGQW
(PUW01)
3.4A
RZ66
+DCBAT_LCD
PJP501
CPU PWR
GPU PWR
Peripheral Device PWR
+VCCSTG
3.44A
PJPH03
PJPH02
FBVDD_EN
TPS51212DSCR
(PUH01)
+VCCSTG_OUT
SIO_SLP_S4 #
SIO_SLP_S3 #
BAS40C
(D1)
+3VLP
+RTC_CELL
SY6288D20AAC
(UU1)
USB_EN#
SY6288D20AAC
(UU3)
USB_EN#
EM5209VF
(UZ1)
SIO_SLP_S3 #
+TPAN_VDD
0ohm 0805
(RA1)
+5V_PVDD
0ohm 0603
(RA4)
+5V_AVDD
JP5
+5V_HDD
AP2330W-7
(UV17)
+VDISPLAY_VCC
FUSE 0.5A_13.2V
(F3)
+5V_KB_BL
+TBTA_VBUS_1 PLS11, PLS12
AON7409
(PQS17,PAS18)
+VBUS_DC_TRIP
RB551V-30
(DT17)
+3VALW_PD
USB30_VCCA
USB20_VCCB
+5VS
SN1610042ZQZR
(UT4)
EN_3V
0ohm 0603
(R13)
PLS11, PLS12
+TBTA_VBUS
+RTC_VCC
RT9058-33GX
(PUS04)
CHARGER
ISL9538HRTZ-T
(PUB01)
SIO_SLP_S3 #
+3VALW P
PJP303
PJP302
EM5209VF
(UZ1)
+3VALW
JPZ2
SY6288C20AAC
(UL2)
E
D
RB551V-30
(DT18)
EM5209VF
(UZ7)
+VCC_CORE
PJP1801
NCP302045MN
(PUG01)
DRVON
PWM1_2PH/ICCMAX2
+VCC_GT
PJP2501
NCP302035MNTXG
(PUA01)
A
5
DRVON
PWM1_1PH/ICCMAX1
r
o
F
+VCC_SA
NCP302045MNTXG
(PUV01)
+GPU_CORE
NCP302045MNTXG
(PUV02)
+GPU_CORE
NCP302045MNTXG
(PUV03)
+GPU_CORE
PJP1001
RT8061AZQW
(PU1801)
+LCDVDD
e
r
+VBUS_DC_SS
AON7409
(PQS2,PAS16)
CHARGER
ISL9538HRTZ-T
(PUB01)
+SDC_IN
+1.2V_RTM_IN
POK
RT9059GSP
(PU2501)
SIO_SLP_S4 #
RT8061AZQW
(PU1001)
PEX_VDD_EN
B
+3VS_TBT
+3VALW_PD
+3V_PCH_PRIM
RH162
+3VALW_DSW
PJP1802
+1.8V_PRIM
+1.8VALWP
AOZ1331
(UG12)
1V8_AON_ON
+1V8_AON
1V8_MAIN_EN
+1V8_MAIN
PJP2502
+2.5VP
+2.5V_MEM
LN2306LT1G
(QA1)
+1.8V_AVDD
0ohm 0603
(RE66)
+1.8VALW_EC
PJP1002
+1.0VS_VGAP
+1VS_GFX
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Power Rail
Size
Document Number
3
2
Rev
0.3
LA-F611P
Date:
4
C
+3.3V_TBT_SX
0ohm 0805
(RT95)
DRVON
PWM2_4PH/ADDR
PWM1_4PH/ICCMAX4
RT9041E-15GQW
(UP1)
+LAN_VDD33
0ohm 0402
(RT97)
NCP302045MNTXG
(PUI02)
LCD_VCC_TEST_EN_R
or
EDP_VDD_EN
+3VALW_EC
AUX_ON
B
NCP302045MNTXG
(PUI01)
SY6288C20AAC
(U1)
+3VS
0ohm 0603
(RE2)
BATTERY
PLS11, PLS12
+3.3V_VBUS_IN
L
L
+PW R_SRC
(+19VB)
AON7409
(PQS1,PAS15)
D
Thursday, March 22, 2018
1
Sheet
4
of
78
5
4
3
1K
PCH
D
1K
Host
BE26
BF26
2
1K
+3VALW
254
+3VS
SMBCLK
SMBDATA
DMN65D8L
499
+3VALW
@
499
@
499
254
Address: 0xA0/0xA1
DIMM2
Address: 0xA4/0xA5
FFS
Address: 0x52/0x53
Slave
1
4
+3VS
w
e
i
v
DIMM1
Slave
253
PCH_SMBCLK
PCH_SMBDATA
DMN65D8L
499
Slave
253
+3VS
1K
1
Slave
BF25
BE24
SML0_SMBCLK
SML0_SMBDATA
4.7K
4.7K
Host
BE21
C
BF21
I2C1_SCL_TCH_PAD
I2C1_SDA_TCH_PAD
2.2K
+3VS
+3VS
DMN66D0L
BE27
E
D
B
Host
11
A
5
89
DMN66D0L
DMN66D0L
12
9
8
Slave
8
7
1.8K
Address: 0x98/0x99
VGA_SMB_CK2
VGA_SMB_DA2
DMN53D0L
Thermal
Sensor
+1V8_AON
1.8K
DMN53D0L
C
+3VS
THM_SML1_CLK
THM_SML1_DATA
ALL_GPWRGD
GPU_THM_SMBCLK
GPU_THM_SMBDAT
MEC1416
r
o
F
+3VS
GPU_THM_SMBCLK
GPU_THM_SMBDAT
Address: 0x88/0x89
Address: 0x2C/0x2D
2.2K
L
L
GPU_THM_SMBCLK
GPU_THM_SMBDAT
Touch
Pad
2.2K
+3VALW_EC
2.2K
Host
BF27
7
2.2K
@
e
r
Slave
8
I2C_SCL_TP
I2C_SDA_TP
DMN66D0L
@
Slave
+TP_VDD
2.2K
D
Slave
T4
T3
GPU
Address: 0x9E/0x9F
4.7K
B
4.7K
+3VALW_EC
Slave
7
PBAT_CHG_SMBCLK
PBAT_CHG_SMBDAT
BATT
Address: 0x16/0x17
CHAGER
Address: 0x12/0x13
6
Slave
22
91
21
Host
@
10K
@
10K
+3VS
0 Ohm
TYPEC_SMBCLK
TYPEC_SMBDA
PD_I2C_SCL_R
PD_I2C_SDA_R
0 Ohm
Slave
B5
A5
TPS65982D
Address: 0x70/0x71
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2017/01/06
Deciphered Date
2018/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
SMBus Block Diagram
Size Document Number
Custom
Date:
4
3
2
R ev
0.3
LA-F611P
Thursday, March 22, 2018
Sheet
1
5
of
78
A
B
C
D
E
Main Func = CPU
UC1
CFL_H@
w
e
i
v
1
CFL-H_BGA1440
SA011703151
CFL_H_SOC
UC1D
TBT-AR
41
41
41
41
41
41
41
41
CPU_DP1_P0
CPU_DP1_N0
CPU_DP1_P1
CPU_DP1_N1
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N3
41
41
CPU_DP1_AUXP
CPU_DP1_AUXN
CPU_DP1_P0
CPU_DP1_N0
CPU_DP1_P1
CPU_DP1_N1
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N3
K36
K37
J35
J34
H37
H36
J37
J38
CPU_DP1_AUXP
CPU_DP1_AUXN
D27
E27
H34
H33
F37
G38
F34
F35
E37
2
E36
F26
E26
C34
D34
B36
B34
F33
E33
C33
B33
A27
B27
DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3
EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3
DDI1_AUXP
DDI1_AUXN
EDP_AUXP
EDP_AUXN
DDI2_TXP_0
DDI2_TXN_0
DDI2_TXP_1
DDI2_TXN_1
DDI2_TXP_2
DDI2_TXN_2
DDI2_TXP_3
EDP_DISP_UTIL
DISP_RCOMP
D29
E29
F28
E28
A29
B29
C28
B28
EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
C26
B26
EDP_AUXP
EDP_AUXN
A33
D37
RC1
L
L
DDI2_TXN_3
DDI2_AUXP
DDI2_AUXN
DDI3_TXP_0
DDI3_TXN_0
DDI3_TXP_1
DDI3_TXN_1
DDI3_TXP_2
DDI3_TXN_2
DDI3_TXP_3
DDI3_TXN_3
29
29
29
29
EDP_AUXP
EDP_AUXN
29
29
e
r
EDP_DISP_UTIL
DP_RCOMP
EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
TC1 TP@
1
2 24.9_0402_1%
1
eDP
+VCCIO
Check OK
2
DP_RCOMP
Trace width=5 mils
Spacing=20 mils
Max length= 600 mils
PROC_AUDIO_CLK
DDI3_AUXP
PROC_AUDIO_SDI
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13
E
D
G27
G25
G29
CPU_DISPA_SDI_C RC2
2
1 20_0402_5%
CPU_DISPA_BCLK
CPU_DISPA_SDO
CPU_DISPA_SDI
CPU_DISPA_BCLK
18
CPU_DISPA_SDO
18
CPU_DISPA_SDI
18
CFL-H_BGA1440
@
3
4
A
r
o
F
3
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(1/8)DDI/eDP
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
6
of
78
A
B
C
D
E
Main Func = CPU
CFL_H_SOC
UC1A
14
DDRCHANNELA
DDR_A_D[0..63]
1
2
3
For ECC DIMM
4
A
r
o
F
LP3/DDR4
DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
BR6
BT6
BP3
BR3
BN5
BP6
BP2
BN3
BL4
BL5
BL2
BM1
BK4
BK5
BK1
BK2
BG4
BG5
BF4
BF5
BG2
BG1
BF1
BF2
BD2
BD1
BC4
BC5
BD5
BD4
BC1
BC2
AB1
AB2
AA4
AA5
AB5
AB4
AA2
AA1
V5
V2
U1
U2
V1
V4
U5
U4
R2
P5
R4
P4
R5
P2
R1
P1
M4
M1
L4
L2
M5
M2
L5
L1
DDR0_DQ_0/DDR0_DQ_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_DQ_1/DDR0_DQ_1
DDR0_CKN_0/DDR0_CKN_0
DDR0_DQ_2/DDR0_DQ_2
DDR0_CKP_1/DDR0_CKP_1
DDR0_DQ_3/DDR0_DQ_3
DDR0_CKN_1/DDR0_CKN_1
DDR0_DQ_4/DDR0_DQ_4
NC/DDR0_CKP_2
DDR0_DQ_5/DDR0_DQ_5
NC/DDR0_CKN_2
DDR0_DQ_6/DDR0_DQ_6
NC/DDR0_CKP_3
DDR0_DQ_7/DDR0_DQ_7
NC/DDR0_CKN_3
DDR0_DQ_8/DDR0_DQ_8
DDR0_DQ_9/DDR0_DQ_9
DDR0_CKE_0/DDR0_CKE_0
DDR0_DQ_10/DDR0_DQ_10
DDR0_CKE_1/DDR0_CKE_1
DDR0_DQ_11/DDR0_DQ_11
DDR0_CKE_2/DDR0_CKE_2
DDR0_DQ_12/DDR0_DQ_12
DDR0_CKE_3/DDR0_CKE_3
DDR0_DQ_13/DDR0_DQ_13
DDR0_DQ_14/DDR0_DQ_14
DDR0_CS#_0/DDR0_CS#_0
DDR0_DQ_15/DDR0_DQ_15
DDR0_CS#_1/DDR0_CS#_1
DDR0_DQ_16/DDR0_DQ_32
NC/DDR0_CS#_2
DDR0_DQ_17/DDR0_DQ_33
NC/DDR0_CS#_3
DDR0_DQ_18/DDR0_DQ_34
DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0
DDR0_DQ_20/DDR0_DQ_36
NC/DDR0_ODT_1
DDR0_DQ_21/DDR0_DQ_37
NC/DDR0_ODT_2
DDR0_DQ_22/DDR0_DQ_38
NC/DDR0_ODT_3
DDR0_DQ_23/DDR0_DQ_39
DDR0_DQ_24/DDR0_DQ_40
DDR0_CAB_4/DDR0_BA_0
DDR0_DQ_25/DDR0_DQ_41
DDR0_CAB_6/DDR0_BA_1
DDR0_DQ_26/DDR0_DQ_42
DDR0_CAA_5/DDR0_BG_0
DDR0_DQ_27/DDR0_DQ_43
DDR0_DQ_28/DDR0_DQ_44
DDR0_CAB_3/DDR0_MA_16
DDR0_DQ_29/DDR0_DQ_45
DDR0_CAB_2/DDR0_MA_14
DDR0_DQ_30/DDR0_DQ_46
DDR0_CAB_1/DDR0_MA_15
DDR0_DQ_31/DDR0_DQ_47
DDR0_DQ_32/DDR1_DQ_0
DDR0_CAB_9/DDR0_MA_0
DDR0_DQ_33/DDR1_DQ_1
DDR0_CAB_8/DDR0_MA_1
DDR0_DQ_34/DDR1_DQ_2
DDR0_CAB_5/DDR0_MA_2
DDR0_DQ_35/DDR1_DQ_3
NC/DDR0_MA_3
DDR0_DQ_36/DDR1_DQ_4
NC/DDR0_MA_4
DDR0_DQ_37/DDR1_DQ_5
DDR0_CAA_0/DDR0_MA_5
DDR0_DQ_38/DDR1_DQ_6
DDR0_CAA_2/DDR0_MA_6
DDR0_DQ_39/DDR1_DQ_7
DDR0_CAA_4/DDR0_MA_7
DDR0_DQ_40/DDR1_DQ_8
DDR0_CAA_3/DDR0_MA_8
DDR0_DQ_41/DDR1_DQ_9
DDR0_CAA_1/DDR0_MA_9
DDR0_DQ_42/DDR1_DQ_10
DDR0_CAB_7/DDR0_MA_10
DDR0_DQ_43/DDR1_DQ_11
DDR0_CAA_7/DDR0_MA_11
DDR0_DQ_44/DDR1_DQ_12
DDR0_CAA_6/DDR0_MA_12
DDR0_DQ_45/DDR1_DQ_13
DDR0_CAB_0/DDR0_MA_13
DDR0_DQ_46/DDR1_DQ_14
DDR0_CAA_9/DDR0_BG_1
DDR0_DQ_47/DDR1_DQ_15
DDR0_CAA_8/DDR0_ACT#
DDR0_DQ_48/DDR1_DQ_32
DDR0_DQ_49/DDR1_DQ_33
NC/DDR0_PAR
DDR0_DQ_50/DDR1_DQ_34
NC/DDR0_ALERT#
DDR0_DQ_51/DDR1_DQ_35
DDR4(IL)/LP3-DDR4(NIL)
DDR0_DQ_52/DDR1_DQ_36
DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQ_61/DDR1_DQ_45
DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
LP3/DDR4
NC/DDR0_ECC_0
DDR0_DQSP_3/DDR0_DQSP_5
NC/DDR0_ECC_1
DDR0_DQSP_4/DDR1_DQSP_0
NC/DDR0_ECC_2
DDR0_DQSP_5/DDR1_DQSP_1
NC/DDR0_ECC_3
DDR0_DQSP_6/DDR1_DQSP_4
NC/DDR0_ECC_4
DDR0_DQSP_7/DDR1_DQSP_5
NC/DDR0_ECC_5
NC/DDR0_ECC_6
DDR0_DQSP_8/DDR0_DQSP_8
1OF13
NC/DDR0_ECC_7
DDR0_DQSN_8/DDR0_DQSN_8
TC4
TC5
TC6
TC7
TC8
TC9
TC10
TC12
BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
AT1
AT2
AT3
AT5
DDR_A_CKE0
DDR_A_CKE1
AD5
AE2
AD2
AE5
DDR_A_CS#0
DDR_A_CS#1
AD3
AE4
AE1
AD4
DDR_A_ODT0
DDR_A_ODT1
AH5
AH1
AU1
DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
AH4
AG4
AD1
DDR_A_MA16_RAS#
DDR_A_MA14_W E#
DDR_A_MA15_CAS#
AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BG1
DDR_A_ACT#
AG3
AU5
DDR_A_PAR
DDR_A_ALERT#
BR5
BL3
BG3
BD3
AA3
U3
P3
L3
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
BP5
BK3
BF3
BC3
AB3
V3
R3
M3
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
L
L
E
D
TP@
TP@
TP@
TP@
TP@
TP@
TP@
TP@
AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1
w
e
i
v
DDR_A_CLK0 14
DDR_A_CLK#0 14
DDR_A_CLK1 14
DDR_A_CLK#1 14
DDR_A_CKE0
DDR_A_CKE1
14
14
DDR_A_CS#0
DDR_A_CS#1
14
14
DDR_A_ODT0
DDR_A_ODT1
14
14
e
r
AY3
BA3
DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
1
14
14
14
DDR_A_MA16_RAS# 14
DDR_A_MA14_W E# 14
DDR_A_MA15_CAS# 14
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BG1
DDR_A_ACT#
2
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
DDR_A_PAR 14
DDR_A_ALERT# 14
TC11 TP@
TC13 TP@
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
14
14
14
14
14
14
14
14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
14
14
14
14
14
14
14
14
3
For ECC DIMM
CFL-H_BGA1440
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(2/8)DIMMA
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
7
of
78
A
B
C
D
E
Main Func = CPU
15
CFL_H_SOC
DDR_B_D[0..63]
UC1B
DDRCHANNELB
1
2
3
For ECC DIMM
r
o
F
RC3
RC4
RC5
1
1
1
TP@
TP@
TP@
TP@
TP@
TP@
TP@
TP@
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
BT11
BR11
BT9
BR8
BP11
BN11
BP8
BN8
BL12
BL11
BL8
BJ8
BJ11
BJ10
BL7
BJ7
BG11
BG10
BG8
BF8
BF11
BF10
BG7
BF7
BB11
BC11
BB8
BC8
BC10
BB10
BC7
BB7
AA11
AA10
AC11
AC10
AA7
AA8
AC8
AC7
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
W8
W7
V10
V11
W11
W10
V7
V8
R11
P11
P7
R8
R10
P10
R7
P8
L11
M11
L7
M8
L10
M10
M7
L8
2 121_0402_1% SM_RCOMP0
2 75_0402_1% SM_RCOMP1
2 100_0402_1% SM_RCOMP2
A
AW11
AY11
AY8
AW8
AY10
AW10
AY7
AW7
G1
H1
J2
LP3/DDR4
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKN_1/DDR1_CKN_1
NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3
DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3
DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1
NC/DDR1_CS#_2
NC/DDR1_CS#_3
DDR1_ODT_0/DDR1_ODT_0
NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3
DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15
DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
DDR_RCOMP_0
DDR_RCOMP_1
DDR_RCOMP_2
AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
AT8
AT10
AT7
AT11
DDR_B_CKE0
DDR_B_CKE1
AF11
AE7
AF10
AE10
DDR_B_CS#0
DDR_B_CS#1
AF7
AE8
AE9
AE11
DDR_B_ODT0
DDR_B_ODT1
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
2OF13
DDR_B_CLK0 15
DDR_B_CLK#0 15
DDR_B_CLK1 15
DDR_B_CLK#1 15
AH10
AH11
AF8
DDR_B_MA16_RAS#
DDR_B_MA14_W E#
DDR_B_MA15_CAS#
AH8
AH9
AR9
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
L
L
DDR4(IL)/LP3-DDR4(NIL)
DDR1_DQ_40/DDR1_DQ_24
DDR1_CAA_3/DDR1_MA_8
DDR1_DQ_41/DDR1_DQ_25
DDR1_CAA_1/DDR1_MA_9
DDR1_DQ_42/DDR1_DQ_26
DDR1_CAB_7/DDR1_MA_10
DDR1_DQ_43/DDR1_DQ_27
DDR1_CAA_7/DDR1_MA_11
DDR1_DQ_44/DDR1_DQ_28
DDR1_CAA_6/DDR1_MA_12
DDR1_DQ_45/DDR1_DQ_29
DDR1_CAB_0/DDR1_MA_13
DDR1_DQ_46/DDR1_DQ_30
DDR1_CAA_9/DDR1_BG_1
DDR1_DQ_47/DDR1_DQ_31
DDR1_CAA_8/DDR1_ACT#
DDR1_DQ_48/DDR1_DQ_48
DDR1_DQ_49/DDR1_DQ_49
NC/DDR1_PAR
DDR1_DQ_50/DDR1_DQ_50
NC/DDR1_ALERT#
DDR1_DQ_51/DDR1_DQ_51
DDR1_DQ_52/DDR1_DQ_52
DDR4(IL)/LP3-DDR4(NIL)
DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQ_61/DDR1_DQ_61
DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
LP3/DDR4
NC/DDR1_ECC_0
DDR1_DQSP_3/DDR0_DQSP_7
NC/DDR1_ECC_1
DDR1_DQSP_4/DDR1_DQSP_2
NC/DDR1_ECC_2
DDR1_DQSP_5/DDR1_DQSP_3
NC/DDR1_ECC_3
DDR1_DQSP_6/DDR1_DQSP_6
NC/DDR1_ECC_4
DDR1_DQSP_7/DDR1_DQSP_7
NC/DDR1_ECC_5
NC/DDR1_ECC_6
DDR1_DQSP_8/DDR1_DQSP_8
NC/DDR1_ECC_7
DDR1_DQSN_8/DDR1_DQSN_8
E
D
TC14
TC15
TC16
TC17
TC18
TC19
TC20
TC22
Trace Width/Space: 15 mil/ 25 mil
Max Trace Length: 500 mil
4
DDR4(IL)/LP3-DDR4(NIL)
DDR1_DQ_0/DDR0_DQ_16
DDR1_DQ_1/DDR0_DQ_17
DDR1_DQ_2/DDR0_DQ_18
DDR1_DQ_3/DDR0_DQ_19
DDR1_DQ_4/DDR0_DQ_20
DDR1_DQ_5/DDR0_DQ_21
DDR1_DQ_6/DDR0_DQ_22
DDR1_DQ_7/DDR0_DQ_23
DDR1_DQ_8/DDR0_DQ_24
DDR1_DQ_9/DDR0_DQ_25
DDR1_DQ_10/DDR0_DQ_26
DDR1_DQ_11/DDR0_DQ_27
DDR1_DQ_12/DDR0_DQ_28
DDR1_DQ_13/DDR0_DQ_29
DDR1_DQ_14/DDR0_DQ_30
DDR1_DQ_15/DDR0_DQ_31
DDR1_DQ_16/DDR0_DQ_48
DDR1_DQ_17/DDR0_DQ_49
DDR1_DQ_18/DDR0_DQ_50
DDR1_DQ_19/DDR0_DQ_51
DDR1_DQ_20/DDR0_DQ_52
DDR1_DQ_21/DDR0_DQ_53
DDR1_DQ_22/DDR0_DQ_54
DDR1_DQ_23/DDR0_DQ_55
DDR1_DQ_24/DDR0_DQ_56
DDR1_DQ_25/DDR0_DQ_57
DDR1_DQ_26/DDR0_DQ_58
DDR1_DQ_27/DDR0_DQ_59
DDR1_DQ_28/DDR0_DQ_60
DDR1_DQ_29/DDR0_DQ_61
DDR1_DQ_30/DDR0_DQ_62
DDR1_DQ_31/DDR0_DQ_63
DDR1_DQ_32/DDR1_DQ_16
DDR1_DQ_33/DDR1_DQ_17
DDR1_DQ_34/DDR1_DQ_18
DDR1_DQ_35/DDR1_DQ_19
DDR1_DQ_36/DDR1_DQ_20
DDR1_DQ_37/DDR1_DQ_21
DDR1_DQ_38/DDR1_DQ_22
DDR1_DQ_39/DDR1_DQ_23
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#
AJ7
AR8
DDR_B_PAR
DDR_B_ALERT#
BN9
BL9
BG9
BC9
AC9
W9
R9
M9
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
BP9
BJ9
BF9
BB9
AA9
V9
P9
L9
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
AW9
AY9
BN13
BP13
BR13
DDR_B_CKE0
DDR_B_CKE1
15
15
DDR_B_CS#0
DDR_B_CS#1
15
15
DDR_B_ODT0
DDR_B_ODT1
15
15
w
e
i
v
1
DDR_B_MA16_RAS# 15
DDR_B_MA14_W E# 15
DDR_B_MA15_CAS# 15
e
r
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
15
15
15
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
15
15
15
15
15
15
15
15
2
DDR_B_MA8 15
DDR_B_MA9 15
DDR_B_MA10 15
DDR_B_MA11 15
DDR_B_MA12 15
DDR_B_MA13 15
DDR_B_BG1 15
DDR_B_ACT# 15
DDR_B_PAR 15
DDR_B_ALERT# 15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
15
15
15
15
15
15
15
15
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
15
15
15
15
15
15
15
15
3
TC21 TP@
TC23 TP@ For ECC DIMM
+V_DDR_REFA_R
+V_DDR_REFA_R
TC111TP@
+V_DDR_REFB_R
+V_DDR_REFB_R
CFL-H_BGA1440
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(3/8)DIMMB
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
8
of
78
A
B
C
D
E
Main Func = CPU
w
e
i
v
1
CFL_H_SOC
UC1C
PEG_CTX_C_GRX_P[0..7]
48
E25
D25
PEG_CTX_C_GRX_P[0..7]
PEG_CTX_C_GRX_N[0..7]
48
PEG_CTX_C_GRX_N[0..7]
E24
F24
PEG_CRX_GTX_P[0..7]
48
PEG_CRX_GTX_P[0..7]
48
PEG_CRX_GTX_N[0..7]
PEG_CRX_GTX_N[0..7]
E23
D23
E22
F22
E21
D21
E20
F20
E19
D19
E18
F18
2
+VCCIO
RC9
1
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
D17
E17
PEG_CRX_GTX_P6
PEG_CRX_GTX_N6
F16
E16
PEG_CRX_GTX_P5
PEG_CRX_GTX_N5
D15
E15
PEG_CRX_GTX_P4
PEG_CRX_GTX_N4
F14
E14
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
D13
E13
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
F12
E12
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
D11
E11
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
F10
E10
PEG_RXP_0
PEG_RXN_0
PEG_TXP_0
PEG_TXN_0
PEG_RXP_1
PEG_RXN_1
PEG_TXP_1
PEG_TXN_1
PEG_RXP_2
PEG_RXN_2
PEG_TXP_2
PEG_TXN_2
PEG_RXP_3
PEG_RXN_3
PEG_TXP_3
PEG_TXN_3
PEG_RXP_4
PEG_RXN_4
PEG_TXP_4
PEG_TXN_4
PEG_RXP_5
PEG_RXN_5
PEG_TXP_5
PEG_TXN_5
PEG_RXP_6
PEG_RXN_6
PEG_TXP_6
PEG_TXN_6
PEG_RXP_7
PEG_RXN_7
PEG_TXP_7
PEG_TXN_7
PEG_RXP_8
PEG_RXN_8
PEG_TXP_8
PEG_TXN_8
PEG_RXP_9
PEG_RXN_9
PEG_TXP_9
PEG_TXN_9
PEG_RXP_10
PEG_RXN_10
PEG_TXP_10
PEG_TXN_10
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
E
D
PEG_RCOMP
2 24.9_0402_1%
G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
3
From PCH
19
19
DMI_CRX_PTX_P0
DMI_CRX_PTX_N0
19
19
DMI_CRX_PTX_P1
DMI_CRX_PTX_N1
19
19
DMI_CRX_PTX_P2
DMI_CRX_PTX_N2
19
19
DMI_CRX_PTX_P3
DMI_CRX_PTX_N3
r
o
F
A
D8
E8
DMI_CRX_PTX_P1
DMI_CRX_PTX_N1
E6
F6
DMI_CRX_PTX_P2
DMI_CRX_PTX_N2
D5
E5
DMI_CRX_PTX_P3
DMI_CRX_PTX_N3
J8
J9
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
B23
A23
B22
C22
B21
A21
B20
C20
B19
A19
B18
C18
A17
B17
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
CC15
CC16
1
1
C16
B16
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
CC13
CC14
1
1
A15
B15
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
CC11
CC12
1
1
PEG_TXP_11
PEG_TXN_11
C14
B14
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
CC9
CC10
1
1
PEG_TXP_12
PEG_TXN_12
A13
B13
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
CC7
CC8
1
1
C12
B12
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_TXP_13
PEG_TXN_13
CC5
CC6
1
1
PEG_TXP_14
PEG_TXN_14
A11
B11
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
CC3
CC4
PEG_TXP_15
PEG_TXN_15
C10
B10
PEG_CTX_GRX_P0
PEG_CTX_GRX_N0
CC1
CC2
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_RXP_3 3OF13 DMI_TXP_3
DMI_RXN_3
DMI_TXN_3
B8
A8
DMI_CTX_PRX_P0
DMI_CTX_PRX_N0
C6
B6
DMI_CTX_PRX_P1
DMI_CTX_PRX_N1
B5
A5
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
D4
B4
DMI_CTX_PRX_P3
DMI_CTX_PRX_N3
e
r
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_N7
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_N6
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P5
PEG_CTX_C_GRX_N5
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P4
PEG_CTX_C_GRX_N4
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_N2
1
1
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_N1
1
1
2 0.22U_0201_6.3V6M
2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
DMI_CTX_PRX_P0
DMI_CTX_PRX_N0
19
19
DMI_CTX_PRX_P1
DMI_CTX_PRX_N1
19
19
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
19
19
DMI_CTX_PRX_P3
DMI_CTX_PRX_N3
19
19
2
3
To PCH
CFL-H_BGA1440
@
PEG_RCOMP
Trace width=15 mils
Spacing=15 mils
Max length= 600 mils
4
DMI_CRX_PTX_P0
DMI_CRX_PTX_N0
B24
C24
L
L
PEG_RXP_11
PEG_RXN_11
PEG_RXP_15
PEG_RXN_15
B25
A25
1
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(4/8)PEG
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
9
of
78
A
B
C
Main Func = CPU
D
UC1E
17
17
PCH_CPU_PCIBCLK_P
PCH_CPU_PCIBCLK_N
17
17
CPU_24MHZ_P
CPU_24MHZ_N
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
B31
A32
PCH_CPU_PCIBCLK_P
PCH_CPU_PCIBCLK_N
D35
C36
CPU_24MHZ_P
CPU_24MHZ_N
E31
D31
BCLKP
BCLKN
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
PCI_BCLKP
PCI_BCLKN
CLK24P
CLK24N
1
VR_SVID_ALERT#
VR_SVID_CLK
VR_SVID_DATA
H_PROCHOT#
VR_SVID_ALERT#
RC267
1
2
220_0402_5%
VR_SVID_DATA
H_PROCHOT#
RC268
1
2
499_0402_1%
VR_SVID_ALERT#_R
BH31
BH32
BH29
H_PROCHOT#_R BR30
DDR_VTT_PG_CTRL
BT13
VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#
< OUT >
18
H_VCCST_PW RGD
H_VCCST_PW RGD
18 H_CPUPW RGD
16 H_PLTRST_CPU#
16 H_PM_SYNC_R
16 H_PM_DOW N
16,26 PECI_EC
16 H_THERMTRIP#
16
H_PM_DOW N
PECI_EC
H_THERMTRIP#
PROC_DETECT#
PROC_DETECT#
1
RC269
2 60.4_0402_1%
RC22 1
RC44 1
RC45 1
1
RC277
2 20_0402_5%
2 0_0201_5%
2 0_0201_5%
@
2 0_0402_5%
TP@ TC97
2
TP@ TC96
VCCST_PW RGD_CPU
H_CPUPW RGD
H_PLTRST_CPU#
H_PM_SYNC_R
H_PM_DOW N_R
PECI_EC_R
H_THERMTRIP#_C
H13
BT31
BP35
BM34
BP31
BT34
J31
PROC_SELECT#
BR33
BN1
CATERR#
BM30
VCCST_PWRGD
BPM#_0
BPM#_1
BPM#_2
BPM#_3
PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
SKTOCC#
PROC_SELECT#
CATERR#
CFG_RCOMP
AT13
AW13
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
BN23
BP23
BP22
BN22
CFG17
CFG16
CFG19
CFG18
CFG17
CFG16
CFG19
CFG18
38
38
38
38
BR27
BT27
BM31
BT30
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
BP30
BL30
BP27
CPU_XDP_TRST#
XDP_PREQ#
XDP_PRDY#
BT25
CFG_RCOMP
L
L
5 OF13
+1.2V_DDR
RC20
RC46
2
2
RC259
1
1 1K_0402_5%
1 1K_0402_5%
@
2
H_VCCST_PW RGD
H_THERMTRIP#
XDP_PREQ#
51_0402_5%
1
1
1
@
2
2
2
49.9_0402_1%
100_0402_1%
56.2_0402_1%
RC262
2
1K_0402_5%
1
0.1U_0402_10V7K
< VDDQ_VTT_EN >
5
4
SM_PG_CTRL
E
D
CATERR#
VR_SVID_DATA
VR_SVID_ALERT#
+3VS
2
RC19
CFG0
RC255 1
49.9_0402_1%
CFG2
CFG4
RC258 1
RC257 1
CFG5
CFG6
CFG7
RC256 1
RC253 1
RC254 1
2 1K_0402_5%
@
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
@
@
1
RC270
2
330K_0402_5%
VCC
NC
A
Y
GND
1
2
< IN >
DDR_VTT_PG_CTRL
3
74AUP1G07GW _TSSOP5
MAIN@
SA00007WE00 (S IC 74AUP1G07SE-7 SOT353 5P LOW PW BUFF) _DIODES
SA00005U600 (S IC 74AUP1G07GW TSSOP 5P BUFFER) _NXP
+VCCSTG
3
To be confirm
CPU_XDP_TRST# 22,38
XDP_PREQ# 22,38
XDP_PRDY# 22,38
UC10
2
CH197
63
RC263
RC260
RC261
1
CFG[7]: PEG Training:
*1 = (default) PEG Train immediately following RESET# de assertion.
0 = PEG Wait for BIOS for training.
CPU_XDP_TDO 18,38
CPU_XDP_TDI 18,38
CPU_XDP_TMS 18,38
CPU_XDP_TCK0 18,38
Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil
RSVD1
RSVD2
CFL-H_BGA1440
@
+VCCST
e
r
CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK0
The CFG signals have a default value of '1' if not terminated on the board.
CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
*1 = (Default) Normal Operation;
0 = Stall.
CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
1 = Normal operation
*0 = Lane numbers reversed.
CFG[4]: eDP enable:
1 = Disabled.
*0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation:
00 = 1 x8, 2 x4 PCI Express*
01 = reserved
*10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
w
e
i
v
TC98 TP@
TC99 TP@
TC101TP@
TC100TP@
BT28
BL32
BP28
BR28
ZVM#
MSM#
AU13
AY13
TP@ TC94
TP@ TC95
DDR_VTT_CNTL
CFG_17
CFG_16
CFG_19
CFG_18
BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19
1
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
2
17
17
67
67
67
26,59,61,67
E
CFL_H_SOC
1
H_PROCHOT#
Reserve for ESD
H_VCCST_PW RGD
CH210 1
@ESD@
2
100P_0402_50V8J
H_PROCHOT#_R
CH211
1
2
100P_0402_50V8J
4
A
r
o
F
3
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(5/8)CFG
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
10
of
78
A
B
Main Func = CPU
C
D
+VCC_CORE
E
+VCC_CORE
+VCC_CORE
+VCC_CORE
CFL_H_SOC
CFL_H_SOC
UC1J
UC1I
AH37
AH38
AG37
AG38
e
r
2
+VCC_CORE
RC10
100_0402_1%
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
1
2
10OF13
CFL-H_BGA1440
VCC_SENSE
VSS_SENSE
VCC_SENSE
VSS_SENSE
RC11
100_0402_1%
3
67
67
LA-F611PR01_0531C.DSN
VCCSENSE change to VCC_SENSE
VSSSENSE change to VSS_SENSE
1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC1, RC2 should be placed within 2 inches (50.8 mm) of CPU
2
+VCCGT
RC12
100_0402_1%
VCCGT_SENSE
VSSGT_SENSE
VCCGT_SENSE
VSSGT_SENSE
67
67
RC13
100_0402_1%
VSSGT_SENSE
VCCGT_SENSE
CFL-H_BGA1440
A
VCC_SENSE
VSS_SENSE
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
1
E
D
9OF13
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
w
e
i
v
L
L
CFL-H_BGA1440
r
o
F
VSSGT_SENSE
11OF13
VCCGT_SENSE
4
BD35
BD36
BE31
BE32
BE33
BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BR37
BT15
BT16
BT17
BT37
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
1
3
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT95
VCCGT96
VCCGT97
VCCGT98
VCCGT99
VCCGT100
VCCGT101
VCCGT102
VCCGT103
VCCGT104
VCCGT105
VCCGT106
VCCGT107
VCCGT108
VCCGT109
VCCGT110
VCCGT111
VCCGT112
VCCGT113
VCCGT114
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
VCCGT128
VCCGT129
VCCGT130
VCCGT131
VCCGT132
VCCGT133
VCCGT134
VCCGT135
VCCGT136
VCCGT137
VCCGT138
VCCGT139
VCCGT140
VCCGT141
VCCGT142
VCCGT143
VCCGT144
VCCGT145
VCCGT146
VCCGT147
VCCGT148
VCCGT149
VCCGT150
VCCGT151
VCCGT152
VCCGT153
VCCGT154
VCCGT155
VCCGT156
VCCGT157
VCCGT158
VCCGT164
VCCGT165
VCCGT166
VCCGT167
VCCGT168
AH13
AH14
AH29
AH30
AH31
AH32
AJ14
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP30
AP31
AP32
AP35
AP36
AP37
AP38
K13
1
2
VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163
2
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BP37
BP38
BR15
BR16
BR17
1
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124
1
+VCCGT
CFL_H_SOC
UC1K
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
2
+VCCGT
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AF38
AG14
AG31
AG32
AG33
AG34
AG35
AG36
4
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC1, RC2 should be placed within 2 inches (50.8 mm) of CPU
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(6/8)VCC_CORE/GT
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
11
of
78
A
B
C
D
E
Main Func = CPU
570805_CFL_EDS_Vol1_Rev0.5
+VCCSA
+1.2V_DDR +1.2V_VDDQ_CPU
Max: 3300mA
CFL_H_SOC
+1.2V_DDR
UC1L
H29
Max: 20mA
2
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12
22uF * 4
2
+VCCSA
M38
M37
1
1
1
1
2
e
r
1
2
2
2
1
+VCCSA
1
2
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
Max: 150mA
RC15
RC275
RC276
RC16
2
+VCCSTG
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2
+VCCST
G30
2
CC303
1U_0402_6.3V6K
H30
2
1
CC32
22U_0603_6.3V6M
2 0_0805_5%
1
CC31
22U_0603_6.3V6M
@
1
CC30
22U_0603_6.3V6M
RC14 1
1
1
w
e
i
v
+1.2V_VCCPLL_OC
1
1
CC40
1U_0201_6.3V6M
1
+1.2V_DDR
1
CC29
22U_0603_6.3V6M
2
1
CC28
10U_0402_6.3V6M
2
1
CC27
10U_0402_6.3V6M
1
CC26
10U_0402_6.3V6M
2
CC25
10U_0402_6.3V6M
VCCIO_SENSE
VSSIO_SENSE
2
1
CC37
1U_0201_6.3V6M
12OF13
1
CC24
10U_0402_6.3V6M
VCCSA_SENSE
VSSSA_SENSE
2
CC36
1U_0201_6.3V6M
570805_CFL_EDS_Vol1_Rev0.5
+1.2V_VCCPLL_OC
Max: 130mA
+VCCST
+VCCSTG
Max: 60mA
H28
J28
1
CC23
10U_0402_6.3V6M
VCCPLL1
VCCPLL2
2
CC22
10U_0402_6.3V6M
VCCSTG1
CC21
10U_0402_6.3V6M
VCCSTG2
2
1
CC35
10U_0402_6.3V6M
VCCST
2
1
+VCCIO
+1.2V_VCCPLL_OC
BH13
BJ13
G11
2
1
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12
22uF * 4
2
VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3
2
1
CC20
10U_0402_6.3V6M
2
1
CC19
10U_0402_6.3V6M
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
1
CC34
10U_0402_6.3V6M
2
+0.95VS_VCCIO AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
CC18
10U_0402_6.3V6M
+VCCIO
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
CC33
10U_0402_6.3V6M
570805_CFL_EDS_Vol1_Rev0.5
+VCC_IO
Max: 6400mA
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22
CC17
10U_0402_6.3V6M
1
11.1A J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
2
2
2
2
100_0402_1%
VCC_SA_SENSE
0_0402_5%
VSS_SA_SENSE
0_0402_5%
100_0402_1%
L
L
VCC_SA_SENSE
VSS_SA_SENSE
H14
J14
CFL-H_BGA1440
67
67
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC1, RC2 should be placed within 2 inches (50.8 mm) of CPU
4
A
r
o
F
1
1
1
1
2
2
2
2
100_0402_1%
VCCIO_SENSE
0_0402_5%
VSSIO_SENSE
0_0402_5%
100_0402_1%
VCCIO_SENSE
VSSIO_SENSE
64
64
1
2
+VCCST
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1
1
2
CC39
1U_0201_6.3V6M
RC271
RC272
RC273
RC274
3
+VCCST
CC38
1U_0201_6.3V6M
E
D
+VCCIO
3
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
Vinafix.com
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(7/8)VCCSA/VCCIO/VDDQ
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
12
of
78
A
B
C
D
E
Main Func = CPU
CFL_H_SOC
CFL_H_SOC
CFL_H_SOC
UC1F
1
2
3
A10
A12
A16
A18
A20
A22
A24
A26
A28
A30
A6
A9
AA12
AA29
AA30
AB33
AB34
AB6
AC1
AC12
AC2
AC3
AC37
AC38
AC4
AC5
AC6
AD10
AD11
AD12
AD29
AD30
AD6
AD8
AD9
AE33
AE34
AE6
AF1
AF12
AF13
AF14
AF2
AF3
AF4
AG10
AG11
AG13
AG29
AG30
AG6
AG7
AG8
AH12
AH33
AH34
AH35
AH36
AH6
AJ1
AJ13
AJ2
AJ3
AJ37
AJ38
AJ4
AJ5
AJ6
W4
W5
Y10
Y11
Y13
Y14
Y37
Y38
Y7
Y8
Y9
AK29
AK30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS 6OF13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CFL-H_BGA1440
4
A
AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34
AW5
AY12
AY33
AY34
B9
BA10
BA11
BA12
BA37
BA38
BA6
BA7
BA8
BA9
BB1
BB12
BB2
BB29
BB3
BB30
BB4
BB5
BB6
BC12
BC13
BC14
BC33
BC34
BC6
BD10
BD11
BD12
BD37
BD6
BD7
BD8
BD9
BE1
BE2
BE29
BE3
BE30
BE4
BE5
BE6
BF12
BF33
BF34
BF6
BG12
BG13
BG14
BG37
BG38
BG6
BH1
BH10
BH11
BH12
BH14
BH2
BH3
BH4
BH5
BH6
BH7
BH8
BH9
T2
T3
T33
T34
T4
T5
T7
T8
T9
U37
U38
BJ12
BJ14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
r
o
F
7OF13
CFL_H_SOC
UC1H
UC1G
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CFL-H_BGA1440
BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14
BN4
BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34
BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36
BR7
BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32
BT5
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C37
C5
C8
C9
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D3
D30
D33
D6
D9
E34
E35
E38
E4
E9
N3
N33
N34
N4
N5
N6
N7
N8
N9
P12
P37
M14
M6
N1
F11
F13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
8OF13
UC1M
22 PCH_TRIGOUT_R
22 CPU_TRIGOUT_R
RC6
1
2 0_0201_5%
RC7
1
2 0_0201_5%
TP@
TC25
TP@
TP@
TC26
TC24
E2
E3
E1
D1
TP@
TP@
TC27
TC29
BR1
BT2
TP@
TC31
BN35
TP@
TP@
TP@
TP@
TC32
TC33
TC34
TC35
J24
H24
BN33
BL34
TP@
TP@
TP@
TP@
TP@
TP@
TC36
TC37
TC38
TC39
TC40
TC41
N29
R14
AE29
AA14
AP29
AP14
A36
PCH_TRIGOUT_R
CPU_TRIGOUT
H23
J23
1
A37
2 30_0402_5%
TP@
RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3
w
e
i
v
e
r
RC8
L
L
E
D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9
TC42
TP@
TC43
TP@
TP@
TC44
TC46
TP@
TP@
TC49
TC50
TP@
TP@
TP@
TC54
TC56
TC58
F30
E30
B30
C30
G3
J3
BR35
BR31
BH30
RSVD_TP1
RSVD_TP2
RSVD11
RSVD10
BK28
BJ28
TC28 TP@
TC30 TP@
BL31
AJ8
G13
TC45 TP@
TC47 TP@
TC48 TP@
C38
C1
BR2
BP1
B38
B2
TC51 TP@
TC52 TP@
TC53 TP@
TC55 TP@
TC57 TP@
TC59 TP@
1
RSVD15
RSVD28
RSVD27
RSVD14
RSVD13
RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36
VSS_A37
PROC_TRIGIN
PROC_TRIGOUT
RSVD24
RSVD23
RSVD7
RSVD21
RSVD12
RSVD3
RSVD25
RSVD26
RSVD29
RSVD22
RSVD20
RSVD17
RSVD16
RSVD8
RSVD6
RSVD19
RSVD18
RSVD9
2
13OF13
CFL-H_BGA1440
3
A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38
CFL-H_BGA1440
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CFL-H(8/8)GND/RSVD
Size
C
D
Rev
0.3
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
13
of
78
5
4
3
2
1
Main Func = DDR
7
7
7
Layout Note:
Place near JDIMM1.257,259
7 DDR_A_D[0..63]
DDR_A_MA[0..13]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
+1.2V_DDR
Layout Note:
Place near JDIMM1.258
DDR_A_D1
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
+2.5V_MEM
+0.6V_DDR_VTT
DDR_A_D7
Layout Note:
Place near JDIMM1.255
2
2
2
1
2
1
2
DDR_A_D3
DDR_A_D9
CD61
1U_0402_6.3V6K~D
2
1
CD60
1U_0402_6.3V6K~D
1
1
CD7
10U_0603_6.3V6M~D
2
CD5
1U_0402_6.3V6K~D
1
CD4
1U_0402_6.3V6K~D
2
CD3
1U_0402_6.3V6K~D
1
CD2
10U_0603_6.3V6M~D
2
CD1
10U_0603_6.3V6M~D
1
1
CD6
10U_0603_6.3V6M~D
D
DDR_A_D8
+3VS
DDR_A_D10
DDR_A_D11
1
2
CD10
2.2U_0603_6.3V6K~D
2
CD9
0.1U_0402_16V7K~D
1
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D23
DDR_A_D18
Layout Note:
Place near JDIMM1
DDR_A_D24
DDR_A_D29
+1.2V_DDR
DDR_A_D31
DDR_A_D30
2
1
2
CD18
1U_0402_6.3V6K~D
2
1
CD17
1U_0402_6.3V6K~D
2
1
CD16
1U_0402_6.3V6K~D
2
1
CD15
1U_0402_6.3V6K~D
2
1
CD14
1U_0402_6.3V6K~D
2
1
CD13
1U_0402_6.3V6K~D
1
CD12
1U_0402_6.3V6K~D
2
CD11
1U_0402_6.3V6K~D
1
C
+1.2V_DDR
7
DDR_A_CKE0
7
7
DDR_A_BG1
DDR_A_BG0
DDR_A_CKE0
DDR_A_BG1
DDR_A_BG0
2
1
2
CD26
10U_0603_6.3V6M~D
2
1
CD25
10U_0603_6.3V6M~D
2
1
CD24
10U_0603_6.3V6M~D
2
1
CD23
10U_0603_6.3V6M~D
2
1
CD22
10U_0603_6.3V6M~D
2
1
CD21
10U_0603_6.3V6M~D
1
CD20
10U_0603_6.3V6M~D
2
CD19
10U_0603_6.3V6M~D
1
DDR_A_MA8
DDR_A_MA6
1
+
2
CD27
330U_D2_2V_Y
MAIN@
DDR_A_MA3
DDR_A_MA1
7
7
DDR_A_CLK0
DDR_A_CLK#0
7
7
DDR_A_PAR
DDR_A_BA1
7
7
7
7
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_PAR
DDR_A_BA1
DDR_A_CS#0
DDR_A_MA14_WE#
DDR_A_CS#0
DDR_A_MA14_WE#
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT1
+1.2V_DDR
+3VS
+3VS
+3VS
RD1
0_0402_5%
@
RD2
0_0402_5%
@
RD7
470_0402_1%
RD3
0_0402_5%
2
2
2
DIMM_CHA_SA0
DIMM_CHA_SA1
DIMM_CHA_SA2
DDR_DRAMRST#
2
2
RD6
0_0402_5%
2
RD5
0_0402_5%
2
RD4
0_0402_5%
1
r
o
F
1
1
RD8
+1.2V_DDR
1
+V_DDR_REFA_R
1
@
2
1
0_0402_5%
H_DRAMRST#
+V_DDR_REFA
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D39
DDR_A_D34
DDR_A_D41
DDR_A_D40
18
DDR_A_D43
DDR_A_D42
DDR_A_D48
DDR_A_D52
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D53
DDR_A_D59
DDR_A_D56
+1.2V_DDR
DDR_A_D60
DDR_A_D61
PCH_SMBCLK
+3VS
15,18,32
PCH_SMBCLK
+2.5V_MEM
1
2 2_0402_1%
DDR_A_D36
DDR_A_D37
CD29
0.1U_0402_16V7K~D
2
1
RD9
1
CD30
0.022U_0402_25V7K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
DDR_A_D0
DDR_A_D4
w
e
i
v
DDR_A_D6
DDR_A_D2
DDR_A_D12
D
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D14
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
e
r
DDR_A_D26
DDR_A_D27
DDR_DRAMRST#
DDR_A_CKE1
DDR_A_ALERT#
C
DDR_DRAMRST#
DDR_A_CKE1 7
15
DDR_A_ACT# 7
DDR_A_ALERT# 7
DDR_A_MA11
DDR_A_MA7
DDR_A_MA5
DDR_A_MA4
DDR_A_MA2
DDR_A_CLK1
DDR_A_CLK#1
2 RD23
1
240_0402_1%
All VREF traces should
have 10 mil trace width
+1.2V_DDR
DDR_A_CLK1 7
DDR_A_CLK#1 7
DDR_A_MA0
DDR_A_MA10
DDR_A_BA0
DDR_A_MA16_RAS#
DDR_A_MA15_CAS#
DDR_A_MA13
DDR_A_BA0 7
DDR_A_MA16_RAS#
7
DDR_A_MA15_CAS#
7
TP40
+V_DDR_REFA
DIMM_CHA_SA2
DDR_A_D33
1
DDR_A_D32
DDR_A_D38
+1.2V_DDR
2
DDR_A_D35
B
DDR_A_D45
DDR_A_D44
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D50
DDR_A_D49
DDR_A_D54
+1.2V_DDR
DDR_A_D51
DDR_A_D58
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PCH_SMBDATA
DIMM_CHA_SA0
PCH_SMBDATA
15,18,32
+0.6V_DDR_VTT
DIMM_CHA_SA1
A
RD12
1K_0402_1%~D
2
1
2
TP41
RD10
1K_0402_1%~D
20mil
A
DDR_A_ODT1
+1.2V_DDR
2
@
1
1
1
1
B
VSS2
DQ4
VSS4
DQ0
VSS6
DM0_n/DBI0_n
VSS7
DQ6
VSS9
DQ2
VSS11
DQ12
VSS13
DQ8
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
DM2_n/DBI2_n
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
DQS3_t
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
DM8_n/DBI_n/NC
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
CKE1
VDD2
ACT_n
ALERT_n
VDD4
A11
A7
VDD6
A5
A4
VDD8
A2
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A0
A10/AP
VDD14
BA0
RAS_n/A16
VDD16
CAS_n/A15
A13
VDD18
C0/CS2_n/NC
VREFCA
SA2
VSS54
DQ36
VSS56
DQ32
VSS58
DM4_n/DBI4_n
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
DM6_n/DBI6_n
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
SDA
SA0
VTT
SA1
GND2
CD28
0.1U_0402_16V7K~D
E
D
7
VSS1
DQ5
VSS3
DQ1
VSS5
DQS0_c
DQS0_t
VSS8
DQ7
VSS10
DQ3
VSS12
DQ13
VSS14
DQ9
VSS16
DM1_n/DBI_n
VSS17
DQ15
VSS19
DQ10
VSS21
DQ21
VSS23
DQ17
VSS25
DQS2_c
DQS2_t
VSS28
DQ23
VSS30
DQ19
VSS32
DQ29
VSS34
DQ25
VSS36
DM3_n/DBI3_n
VSS37
DQ30
VSS39
DQ26
VSS41
CB5/NC
VSS43
CB1/NC
VSS45
DQS8_c
DQS8_t
VSS48
CB2/NC
VSS50
CB3/NC
VSS52
CKE0
VDD1
BG1
BG0
VDD3
A12
A9
VDD5
A8
A6
VDD7
A3
A1
VDD9
CK0_t
CK0_c
VDD11
PARITY
BA1
VDD13
CS0_n
WE_n/A14
VDD15
ODT0
CS1_n
VDD17
ODT1
VDD19
C1, CS3_n,NC
VSS53
DQ37
VSS55
DQ33
VSS57
DQS4_c
DQS4_t
VSS60
DQ38
VSS62
DQ34
VSS64
DQ44
VSS66
DQ40
VSS68
DM5_n/DBI5_n
VSS69
DQ46
VSS71
DQ42
VSS73
DQ52
VSS75
DQ49
VSS77
DQS6_c
DQS6_t
VSS80
DQ55
VSS82
DQ51
VSS84
DQ61
VSS86
DQ56
VSS88
DM7_n/DBI7_n
VSS89
DQ62
VSS91
DQ58
VSS93
SCL
VDDSPD
VPP1
VPP2
GND1
L
L
DDR_A_MA12
DDR_A_MA9
+1.2V_DDR
SP07001CY0L
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
2
RD11
24.9_0402_1%
5
4
LOTES_ADDR0206-P001A02~D
DEREN_40-42271-26001RHF
CONN@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
DDR4 DIMMA_RVS
Size
2
Rev
0.3
LA-F611P
Date:
3
Document Number
Thursday, March 22, 2018
Sheet
1
14
of
78
5
4
3
2
1
Main Func = DDR
+1.2V_DDR
Layout Note:
Place near JDIMM2.258
8
8
8
8
Layout Note:
Place near JDIMM2.257,259
DDR_B_D[0..63]
DDR_B_MA[0..13]
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_D5
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D7
DDR_B_D3
+2.5V_MEM
+0.6V_DDR_VTT
DDR_B_D14
D
DDR_B_D10
2
1
2
CD63
1U_0402_6.3V6K~D
2
1
CD62
1U_0402_6.3V6K~D
2
1
CD37
10U_0603_6.3V6M~D
2
1
CD36
1U_0402_6.3V6K~D
2
1
CD35
1U_0402_6.3V6K~D
2
1
CD34
10U_0603_6.3V6M~D
2
1
CD33
10U_0603_6.3V6M~D
1
CD32
10U_0603_6.3V6M~D
2
CD31
1U_0402_6.3V6K~D
1
Layout Note:
Place near JDIMM2.255
DDR_B_D13
DDR_B_D11
DDR_B_D18
DDR_B_D17
+3VS
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D21
1
2
CD40
2.2U_0603_6.3V6K~D
2
Layout Note:
Place near JDIMM2
CD39
0.1U_0402_16V7K~D
1
DDR_B_D20
DDR_B_D27
DDR_B_D25
DDR_B_D29
DDR_B_D26
+1.2V_DDR
2
1
2
CD48
1U_0402_6.3V6K~D
2
1
CD47
1U_0402_6.3V6K~D
2
1
CD46
1U_0402_6.3V6K~D
2
1
CD45
1U_0402_6.3V6K~D
2
1
CD44
1U_0402_6.3V6K~D
2
1
CD43
1U_0402_6.3V6K~D
2
1
CD42
1U_0402_6.3V6K~D
1
CD41
1U_0402_6.3V6K~D
C
8
DDR_B_CKE0
8
8
DDR_B_BG1
DDR_B_BG0
DDR_B_CKE0
DDR_B_BG1
DDR_B_BG0
DDR_B_MA12
DDR_B_MA9
+1.2V_DDR
1
2
1
2
1
2
1
2
CD56
10U_0603_6.3V6M~D
2
CD55
10U_0603_6.3V6M~D
1
CD54
10U_0603_6.3V6M~D
2
CD53
10U_0603_6.3V6M~D
1
CD52
10U_0603_6.3V6M~D
2
CD51
10U_0603_6.3V6M~D
1
CD50
10U_0603_6.3V6M~D
2
CD49
10U_0603_6.3V6M~D
1
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK#0
8
8
DDR_B_PAR
DDR_B_BA1
8
8
DDR_B_CS#0
DDR_B_MA14_WE#
8
8
DDR_B_ODT0
DDR_B_CS#1
8
DDR_B_ODT1
DDR_B_PAR
DDR_B_BA1
DDR_B_CS#0
DDR_B_MA14_WE#
DDR_B_ODT0
DDR_B_CS#1
DDR_B_ODT1
+3VS
r
o
F
2
2
@
RD14
0_0402_5%
RD17
0_0402_5%
RD18
0_0402_5%
2
@
2
2
RD16
0_0402_5%
1
DIMM_CHB_SA2
1
DIMM_CHB_SA1
1
DIMM_CHB_SA0
@
RD15
0_0402_5%
2
RD13
0_0402_5%
1
RD20
1K_0402_1%~D
DDR_B_D36
DDR_B_D44
DDR_B_D45
DDR_B_D43
DDR_B_D42
DDR_B_D51
DDR_B_D52
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D53
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D60
PCH_SMBCLK
+3VS +2.5V_MEM
14,18,32
VSS2
DQ4
VSS4
DQ0
VSS6
DM0_n/DBI0_n
VSS7
DQ6
VSS9
DQ2
VSS11
DQ12
VSS13
DQ8
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
DM2_n/DBI2_n
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
DQS3_t
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
DM8_n/DBI_n/NC
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
CKE1
VDD2
ACT_n
ALERT_n
VDD4
A11
A7
VDD6
A5
A4
VDD8
A2
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A0
A10/AP
VDD14
BA0
RAS_n/A16
VDD16
CAS_n/A15
A13
VDD18
C0/CS2_n/NC
VREFCA
SA2
VSS54
DQ36
VSS56
DQ32
VSS58
DM4_n/DBI4_n
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
DM6_n/DBI6_n
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
SDA
SA0
VTT
SA1
GND2
PCH_SMBCLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
DDR_B_D4
DDR_B_D0
DDR_B_D2
w
e
i
v
DDR_B_D6
DDR_B_D8
DDR_B_D9
D
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D12
DDR_B_D15
DDR_B_D22
DDR_B_D16
DDR_B_D23
DDR_B_D19
DDR_B_D28
DDR_B_D30
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
e
r
DDR_B_D24
DDR_DRAMRST#
DDR_B_CKE1
DDR_B_ALERT#
DDR_B_MA11
DDR_B_MA7
DDR_DRAMRST#
DDR_B_CKE1 8
C
14
DDR_B_ACT# 8
DDR_B_ALERT# 8
DDR_B_MA5
DDR_B_MA4
DDR_B_MA2
DDR_B_CLK1
DDR_B_CLK#1
2 RD24
1
240_0402_1%
+1.2V_DDR
All VREF traces should
have 10 mil trace width
DDR_B_CLK1 8
DDR_B_CLK#1 8
DDR_B_MA0
DDR_B_MA10
DDR_B_BA0
DDR_B_MA16_RAS#
DDR_B_MA15_CAS#
DDR_B_MA13
DDR_B_BA0 8
DDR_B_MA16_RAS#
8
DDR_B_MA15_CAS#
8
TP43
+V_DDR_REFB
DIMM_CHB_SA2
DDR_B_D39
DDR_B_D34
1
DDR_B_D33
+1.2V_DDR
2
DDR_B_D32
DDR_B_D40
B
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D54
DDR_B_D48
DDR_B_D49
+1.2V_DDR
DDR_B_D50
DDR_B_D59
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D58
DDR_B_D56
PCH_SMBDATA
DIMM_CHB_SA0
PCH_SMBDATA
14,18,32
+0.6V_DDR_VTT
DIMM_CHB_SA1
2
20mil
DDR_B_D37
+1.2V_DDR
+1.2V_DDR
+V_DDR_REFB_R
DDR_B_DQS#4
DDR_B_DQS4
+1.2V_DDR
1
1
+3VS
1
+3VS
DDR_B_D38
DDR_B_D35
+1.2V_DDR
SP07001HW0L
CD58
0.1U_0402_16V7K~D
E
D
TP42
B
VSS1
DQ5
VSS3
DQ1
VSS5
DQS0_c
DQS0_t
VSS8
DQ7
VSS10
DQ3
VSS12
DQ13
VSS14
DQ9
VSS16
DM1_n/DBI_n
VSS17
DQ15
VSS19
DQ10
VSS21
DQ21
VSS23
DQ17
VSS25
DQS2_c
DQS2_t
VSS28
DQ23
VSS30
DQ19
VSS32
DQ29
VSS34
DQ25
VSS36
DM3_n/DBI3_n
VSS37
DQ30
VSS39
DQ26
VSS41
CB5/NC
VSS43
CB1/NC
VSS45
DQS8_c
DQS8_t
VSS48
CB2/NC
VSS50
CB3/NC
VSS52
CKE0
VDD1
BG1
BG0
VDD3
A12
A9
VDD5
A8
A6
VDD7
A3
A1
VDD9
CK0_t
CK0_c
VDD11
PARITY
BA1
VDD13
CS0_n
WE_n/A14
VDD15
ODT0
CS1_n
VDD17
ODT1
VDD19
C1, CS3_n,NC
VSS53
DQ37
VSS55
DQ33
VSS57
DQS4_c
DQS4_t
VSS60
DQ38
VSS62
DQ34
VSS64
DQ44
VSS66
DQ40
VSS68
DM5_n/DBI5_n
VSS69
DQ46
VSS71
DQ42
VSS73
DQ52
VSS75
DQ49
VSS77
DQS6_c
DQS6_t
VSS80
DQ55
VSS82
DQ51
VSS84
DQ61
VSS86
DQ56
VSS88
DM7_n/DBI7_n
VSS89
DQ62
VSS91
DQ58
VSS93
SCL
VDDSPD
VPP1
VPP2
GND1
L
L
DDR_B_MA8
DDR_B_MA6
8
8
JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
A
1
A
+V_DDR_REFB
2 2_0402_1%
1
RD19
1
RD21
1K_0402_1%~D
2
CD59
0.022U_0402_25V7K
1
2
LOTES_ADDR0205-P001A02~D
DEREN_40-42261-26001RHF
CONN@
2
RD22
24.9_0402_1%
5
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
DDR4 DIMMB_STD
Size
2
Rev
0.3
LA-F611P
Date:
3
Document Number
Thursday, March 22, 2018
Sheet
1
15
of
78
5
4
3
2
1
Main Func = PCH
CLIP1
CLIP_15X3_VIUS1
EC0XQ000G00
L47
L46
U48
U47
N48
N47
P47
R46
PCIE SSD
M.2 SSD/ NVMe/ Optane
PCIe
34
34
34
34
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
C36
B36
F39
G38
AR42
AR48
AU47
AU46
35
35
35
35
LAN
PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
C39
D39
D46
C47
SATA3_PTX_DRX_N0
SATA3_PTX_DRX_P0
SATA3_PRX_DTX_N0
SATA3_PRX_DTX_P0
32 SATA3_PTX_DRX_N0
32 SATA3_PTX_DRX_P0
32 SATA3_PRX_DTX_N0
32 SATA3_PRX_DTX_P0
SATA HDD --->
PCIE SSD
M.2 SSD/ NVMe/ Optane
PCIe
34
34
34
34
PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12
B38
C38
C45
C46
PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12
E37
D38
J41
H42
B44
A44
R37
R35
D43
C44
N42
M44
CL_CLK
CL_DATA
CL_RST#
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
GPP_K8
GPP_K9
GPP_K10
GPP_K11
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
GPP_K0
GPP_K1
GPP_K2
GPP_K3
GPP_K4
GPP_K5
GPP_K6
GPP_K7
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE_15_SATA_2_TXN
PCIE15_TXP/SATA2_TXP
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE11_TXP/SATA0A_TXP
PCIE11_TXN/SATA0A_TXN
PCIE11_RXP/SATA0A_RXP
PCIE11_RXN/SATA0A_RXN
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
GPP_F10/SATA_SCLOCK
GPP_F11/SATA_SLOAD
GPP_F13/SATA_SDATAOUT0
GPP_F12/SATA_SDATAOUT1
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP
GPP_E8/SATA_LED#
PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0
PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1
PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3
GPP_F1/SATAXPCIE4/SATAGP4
PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5
PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6
PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
PCIE12_RXN/SATA1A_RXN
GPP_F21/EDP_BKLTCTL
PCIE20_TXP/SATA7_TXP
GPP_F20/EDP_BKLTEN
PCIE20_TXN/SATA7_TXN
GPP_F19/EDP_VDDEN
PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
THRMTRIP#
PCIE19_TXP/SATA6_TXP
PECI
PCIE19_TXN/SATA6_TXN
PM_SYNC
PCIE19_RXP/SATA6_RXP 3 OF 13
PLTRST_CPU#
PCIE19_RXN/SATA6_RXN
PM_DOWN
CNP-H
41
CPU_DP1_HPD
CPU_DP1_HPD
B
29
EDP_HPD
RH656
0_0201_5%
1
2
EDP_HPD_R
E
D
AT6
AN10
AP9
AL15
AN6
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
K37
J37
C35
B35
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
F44
E45
B40
C40
PCIE_PRX_DTX_N15
PCIE_PRX_DTX_P15
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15
K43
K44
A42
B42
P41
R40
C42
D42
AH41
AJ43
AK47
AN47
AM46
AM43
AM47
AM48
5 OF 13
M2_SSD_DETECT
L_BKLT_CTRL
BKLT_IN_EC
EDP_VDD_EN
AU48
AV46
AV44
H_THERMTRIP#_R RH79 1
PECI_PCH
RH73 1
H_PM_SYNC_PCH RH13 1
H_PLTRST_CPU#
H_PM_DOWN
AD3
AF2
AF3
AG5
AE2
GPP_F14/EXT_PWR_GATE#/PS_ON#
GPP_I4/EDP_HPD/DISP_MISC4
PCH_SATA_LED#
AK48
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_F23/DDPF_CTRLDATA
GPP_F22/DDPF_CTRLCLK
GPP_I0/DDPB_HPD0/DISP_MISC0
GPP_I1/DDPC_HPD1/DISP_MISC1
GPP_I2/DPPD_HPD2/DISP_MISC2
GPP_I3/DPPE_HPD3/DISP_MISC3
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
34
34
34
34
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
34
34
34
34
PCIE_PRX_DTX_N15
PCIE_PRX_DTX_P15
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15
33
33
33
33
L41
M40
B41
C41
PCH_SATA_LED#
M2_SSD_DETECT
L
L
CNP-H_BGA874
UH1E
G36
F36
C34
D34
GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0
GPP_K21
GPP_K20
GPP_H23/TIME_SYNC0
AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49
AP41
M45
L48
T45
T46
AJ47
30,34
34
L_BKLT_CTRL
29
BKLT_IN_EC
26
EDP_VDD_EN
29
2 620_0402_5%
2 13_0402_5%
2 30_0402_5%
PCIE SSD
M.2 SSD/ NVMe/ Optane
PCIe / SATA
WLAN
e
r
H_THERMTRIP#
H_THERMTRIP#
10
PECI_EC
10,26
H_PM_SYNC_R
10
H_PLTRST_CPU#
10
H_PM_DOWN
10
H_PM_SYNC_R
D
+3VS
PCH_SATA_LED#
1
RH512
C
2
10K_0201_5%
H_PM_DOWN
@
RH14
13_0402_5%
1
P48
V47
V48
W47
C
w
e
i
v
CNP-H
UH1C
AR2
AT5
AU4
2
D
#571391_CFL_H_PDG_Rev0p5
12.2.10 PM_DOWN Topology
CPU_DP1_CTRL_DATA
T4942 TP@
T4943 TP@
T4941 TP@
PROC_DETECT#
PROC_DETECT#
B
10
PROJECT_ID2
PROJECT_ID1
2
TPM@
RH561
10K_0201_5%
1
1
2
TBT@
RH557
10K_0201_5%
A
PROJECT ID
Non-TBT
TBT
5
4
CPU_DP1_CTRL_DATA
RH33
+3VS
1
2
2.2K_0402_5%
NON_TPM@
RH562
10K_0201_5%
2
2
NON_TBT@
RH681
10K_0201_5%
PCH Strap PIN
PROJECT_ID1
PROJECT_ID2
1
r
o
F
+3VS
1
CNP-H_BGA874
eDP_HPD pull down 100K
A
PROJECT ID1
(GPP_K22)
0
1
TPM ID
SW TPM
HW TPM
DDP[B..F]CTRLDATA
This signal has a weak internal Pull-down.
0 = Port B is not detected. (Default)
1 = Port B is detected.
Notes:
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.
2. This signal is in the primary well.
PROJECT ID2
(GPP_K23)
0
1
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (1/7) SATA,DDC,PCIE
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
16
of
78
5
4
3
2
1
Update OK
PCH_RTCX1
YH1 CH45 CH46 Main X76 control
CNP-H
RH70
10M_0402_5%
1
2
UH1G
2
FFS_INT1
100K_0201_5%
FFS_INT2
FFS_INT1
20,32
RP3
4
3
2
1
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
B8
C8
pop RH71 for KBL-H
pop RH20 for CFL-H , PDG 0.5
CLKREQ_PCIE#7
CLKREQ_PCIE#14
CLKREQ_PCIE#15
CLKREQ_PCIE#9
5
6
7
8
10
10
+1.05VALW
100K_0201_5%
RH71 1
1
RH20
GPU
LAN
WLAN
NVMe
10K_0804_8P4R_5%
@
2 2.7K_0402_1%
XCLK_BIASREF
2
60.4_0402_1%
XTAL24_OUT
XTAL24_IN
U9
U10
XCLK_BIASREF
T3
PCH_RTCX1
PCH_RTCX2
BA49
BA48
CLKREQ_PCIE#0
TBT
41
XCLK_BIASREF
Trace Width/Space:
Max Trace Length:
GPU
15mil /15
1000 mil
48
NVMe
34
mil
CLKREQ_PCIE#7
CLKREQ_PCIE#7
CLKREQ_PCIE#9
CLKREQ_PCIE#9
LAN
WLAN
35 CLKREQ_PCIE#14
33 CLKREQ_PCIE#15
WLAN
33 CLK_PCIE_N15
33 CLK_PCIE_P15
CLKREQ_PCIE#14
CLKREQ_PCIE#15
35 CLK_PCIE_N14
35 CLK_PCIE_P14
LAN
BF31
BE31
AR32
BB30
BA30
AN29
AE47
AC48
AE41
AF48
AC41
AC39
AE39
AB48
AC44
AC43
CLKREQ_PCIE#0
CLK_PCIE_N15
CLK_PCIE_P15
V2
V3
CLK_PCIE_N14
CLK_PCIE_P14
T2
T1
AA1
Y2
AC7
AC6
GPP_A16/CLKOUT_48
CLKOUT_CPUNSSC_P
CLKOUT_CPUNSSC#
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK#
CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P
XTAL_OUT
XTAL_IN
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
XCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
RTCX1
RTCX2
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B5/SRCCLKREQ0#
GPP_B6/SRCCLKREQ1#
GPP_B7/SRCCLKREQ2#
GPP_B8/SRCCLKREQ3#
GPP_B9/SRCCLKREQ4#
GPP_B10/SRCCLKREQ5#
GPP_H0/SRCCLKREQ6#
GPP_H1/SRCCLKREQ7#
GPP_H2/SRCCLKREQ8#
GPP_H3/SRCCLKREQ9#
GPP_H4/SRCCLKREQ10#
GPP_H5/SRCCLKREQ11#
GPP_H6/SRCCLKREQ12#
GPP_H7/SRCCLKREQ13#
GPP_H8/SRCCLKREQ14#
GPP_H9/SRCCLKREQ15#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
CLKOUT_PCIE_N15
CLKOUT_PCIE_P15
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
CLKOUT_PCIE_N14
CLKOUT_PCIE_P14
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N13
CLKOUT_PCIE_P13
CLKOUT_PCIE_N11
CLKOUT_PCIE_N12
CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13
CLKIN_XTAL
Y3
Y4
PCH_XDP_CLK_N
PCH_XDP_CLK_P
B6
A6
PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_P
AJ6
AJ7
CLK_PCIE_N0
CLK_PCIE_P0
T4938
T4939
TP@
TP@
YH1
32.768KHZ_X1A000141000300
PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_P
CLK_PCIE_N0
CLK_PCIE_P0
TBT
AB2
AB3
W4
W3
CLK_PCIE_N7
CLK_PCIE_P7
GPU
CLK_PCIE_N9 34
CLK_PCIE_P9 34
AC9
AC11
AE9
AE11
REFCLK_CNV_H
REFCLK_CNV
2 CNV@ 1
RH698
0_0402_5%
RH75 1
2 100K_0402_5%PCH_SPI_WP#_R
RH78 1
2 100K_0402_5%PCH_SPI_HOLD#_R
PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_CS#
PCH_SPI_CLK_R
AU41
BA45
AY47
AW47
AW48
PCH_SPI_WP#_R
PCH_SPI_HOLD#_R
PCH_SPI_CS2#
AY48
BA46
AT40
2 100K_0402_5% PCH_SPI_SI_R
RH7351
RH4551
AL37
AN35
RH1 close to UH4
2 4.7K_0402_5% PCH_SPI_CS#
@
PCH_SPI_HOLD#_R
2 1K_0201_5%
@
38
PCH_SPI_WP#_R
23
PCH_SPI_CS2#
32
+3V_PCH_PRIM
+3V_SPI
2
RSPI1
VSS
TP
SPI0_IO2
SPI0_IO3
SPI0_CS2#
SPI ROM
r
o
F
PCH_SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_CLK
2
SA00009RI10
@
UH15
1
2
3
4
/CS
DO(IO1)
/WP(IO2)
GND
VCC
/HOLD(IO3)
CLK
DI(IO0)
8
7
6
5
PCH_SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
S IC FL 128M W25Q128JVSIQ SOIC8P SPI ROM
SA00005VV20
MAIN@
@EMI@
PCH_SPI_CS#
PCH_SPI_SO
PCH_SPI_WP#
Close UH4
1
+3V_SPI
@EMI@
A
RPH5
8
7
6
5
INTRUDER#
Y47
Y46
Y48
W46
AA45
TBT_FORCE_PWR
RTD3_CIO_PWR_EN
RTD3_USB_PWR_EN
AL47
AM45
BF32
BC33
AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48
BB44
TOUCH_SCREEN_PD#
TOUCHPAD_INTR#
GC6_THM_DIS#
1
X7676731L74
XTAL_M@
1
CH48
15P_0402_50V
2
Metal Shielding Type
+3VS
1
1
GC6_THM_DIS#
UH3
TC7SH08FU_SSOP5
B
A
4
Y
2
RH742
100K_0201_5%
29
CH201
0.1U_0201_6.3V6K
2
PCH_PLTRST#
TOUCH_SCREEN_PD#
C
2
41
41
41
PLTRST#
MAIN@
23,26,33,34,35,41,48
RH199
100K_0201_5%
26
GPP_H15
+3VS
GPP_H12
INTRUDER#
TOUCH_SCREEN_PD#
RH69
1
2 10K_0201_5%
TOUCHPAD_INTR#
RH179
1
2 10K_0201_5%
GC6_THM_DIS#
RH573
1
2 10K_0201_5%
TOUCHPAD_INTR#
2
+RTC_CELL_PCH
2
PCH_SPI_HOLD#_R
PCH_SPI_SO_R
PCH_SPI_SI_R
PCH_SPI_WP#_R
B
DH2
RH531
TP_WAKE_KBC#
1
TP_WAKE_KBC#
26,31
RB751S40T1G_SOD523-2
MAIN@
+3V_PCH_PRIM
PCH
2
PCH_SPI_CLK_R
15_0402_1%
PCH_SPI_CLK_R
HDD_EN_PCH
RH687
1
2 10K_0201_5%
@
+3V_PCH_PRIM
23
GPP_H15
RH726
1
GPP_H12
RH727
1
PCH_SPI_CLK_R RH738
1
2 100K_0201_5%
2 4.7K_0402_5%
@
2 100K_0201_5%
Reserve for ESD
PCH_PLTRST#
A
CH222
1
2 100P_0402_50V8J
@ESD@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Co-lay with UH4
5
TBT_FORCE_PWR
RTD3_CIO_PWR_EN
RTD3_USB_PWR_EN
1
INTRUDER#
1M_0402_5%
CH224
RH708
33P_0402_50V8J
33_0402_5%
W25Q256JVEIQ_WSON8_8X6
2
8
7
6
5
VCC
HOLD#_RESET#
CLK
DI
CH49
0.1U_0402_16V7K
1
CS#
DO
WP#
GND1
GND2
GPP_H18/SML4ALERT#
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H15/SML3ALERT#
GPP_H14/SML3DATA
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
GPP_H11/SML2DATA
GPP_H10/SML2CLK
AV29
3
4
XTAL_M@
33_0804_8P4R_5%
1
2
UH4
1
2
3
4
9
PCH_SPI_HOLD# 1
PCH_SPI_SO
2
PCH_SPI_SI
3
PCH_SPI_WP# 4
PCH_SPI_CLK
1
RH104 EMI@
+3V_SPI
PCH_SPI_CS#
PCH_SPI_SO
PCH_SPI_WP#
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
E
D
1
0_0402_5%
SPI ROM FOR ME ( 32MByte )
PN: SA00009RI10
L
L
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
T4940 HDD_DET#
PAD
GPP_B13/PLTRST#
GPP_K16/GSXCLK
GPP_K12/GSXDOUT
GPP_K13/GSXSLOAD
GPP_K14/GSXDIN
GPP_K15/GSXSRESET#
BE19
BF19 GPP_D1/SPI1_CLK/SBK1_BK1
FFS_INT2
BF18 GPP_D0/SPI1_CS#/SBK0_BK0
32 FFS_INT2
TPM_PIRQ#
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3
23 TPM_PIRQ#
BC17 GPP_D2/SPI1_MISO/SBK2_BK2
HDD_EN_PCH_H
1 OF 13
BD17 GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2
HDD_EN_PCH 1
2 HDD_EN_PCH_H
@
HDD_EN_PCH
RH699
0_0201_5%
CNP-H_BGA874
@
B
RSVD2
RSVD1
YH2 CH47 CH48 Main X76 control
2
RH74 1
GPP_A11/PME#/SD_VDD2_PWR_EN#
PCH_PLTRST#
1
2
XTAL_M@
33
XTAL24_OUT_R
YH2
24MHZ 12PF +-10PPM 7M24090001
CH47
12P_0402_50V
2
10K_0201_5%
XTAL24_OUT_R
XTAL24_IN_R
2 33_0201_5%
2 33_0201_5%
RH72
1M_0402_5%~D
1
2
e
r
NGFF - SSD
REFCLK_CNV
1RFI@
1RFI@
RH711
RH712
1
+3V_SPI
R15
R13
D
CH46
8.2P_0402_50V
XTAL_M@
2
BE36
PCH_SPI_SI_R
PCH_SPI_SO_R
2
XTAL24_IN_R
NVMe
CFL-H PDG rev0.7
pop 20K for SPI0_IO2/3
23,38 PCH_SPI_SI_R
23 PCH_SPI_SO_R
2
XTAL24_OUT
XTAL24_IN
48
48
GPU
CLK_PCIE_N9
CLK_PCIE_P9
1
RH716
UH1A
1
Reserve for RF immunity
CLK_PCIE_N7
CLK_PCIE_P7
AC14
AC15
R6
1
RTC CRYSTAL
Max Crystal ESR
= 50k Ohm.
AC2
AC3
U2
U3
2
w
e
i
v
CH45
8.2P_0402_50V
XTAL_M@
AE6
AE7
CNP-H_BGA874
CNP-H
1
TBT-AR
AE14
AE15
C
CNL- PCH EDS rev0.5
Reserved External pull-up is required. Recommend 100K if pulled
up to 3.3V
10
10
XTAL_M@
41
41
AH9
AH10
W7
W6
X7676731L91
PCH_RTCX2
1
D
2
D7
C6
5
1
RH728
1
RH680
BE33
T92
CPU_24MHZ_P
CPU_24MHZ_N
CPU_24MHZ_P
CPU_24MHZ_N
P
10
10
3
TP@
+3VS
G
Main Func = PCH
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (2/7) CLK,SPI,PLTRST
Size
4
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
1
Sheet
17
of
78
5
4
Main Func = PCH
RP50
24
24
PCH_AZ_CODEC_SDOUT
PCH_AZ_CODEC_SYNC
24
PCH_AZ_CODEC_BITCLK
1
2
3
4
8
7
6
5
3
2
1
PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK
+3VALW_DSW
33_0804_8P4R_5%
CNP-H
UH1D
PCH_AZ_BITCLK
24
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_AZ_SYNC
D
+RTC_CELL_PCH
PCH_AZ_RST#
PCH to DDR, XDP, FFS
RH83 1
1
6 CPU_DISPA_SDO
6 CPU_DISPA_SDI
6 CPU_DISPA_BCLK
RH39
1
2 30_0402_5%
CPU_DISPA_SDO_R
RH38
1
2 30_0402_5%
CPU_DISPA_BCLK_R
GPU_ID2
GPU_ID1
CLKREQ_CNV#
CNV_RF_RESET#
2
PCH_RTCRST#
1
DVT1.0
Change QH6 to SB00000PU00
G
S
3
1
33
33
CLKREQ_CNV#
CNV_RF_RESET#
48,56,76
DGPU_PWROK
PCH_RSMRST#
PCH_RSMRST#
1
2
0_0201_5%
RH503
2
26,38
PCH_RTCRST#
2
2
1
GPU_THM_SMBCLK
GPU_THM_SMBDAT
1
2 20K_0402_5%~D
CLRP1
SHORT PADS
PCH_RTCRST#
PCH_SRTCRST#
BE47
BD46
PCH_PWROK
PCH_RSMRST#_R
AY42
BA47
PCH_DPWROK
2
0_0201_5%
SMBALERT#
SMBCLK
SMBDATA
SML0ALERT#
SML0_SMBCLK
SML0_SMBDATA
1
RH672
+RTC_CELL_PCH
CH53
1U_0603_10V6K~D
DGPU_PWROK
QH7
L2N7002LT1G_SOT23-3
GEN8@
RH679 GEN8@
100K_0201_5%
C
AM2
AN3
AM3
AV18
AW18
BA17
BE16
BF15
BD16
AV16
AW15
AW41
BE25
BE26
BF26
BF24
BF25
BE24
BD33
BF27
BE27
SML1ALERT#
GPU_THM_SMBCLK
GPU_THM_SMBDAT
26,31,48 GPU_THM_SMBCLK
26,31,48 GPU_THM_SMBDAT
GPU_THM_EC
CLRP1 in DIMM Door
BF36
AV32
GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
GPP_A8/CLKRUN#
HDA_RST#/I2S1_SCLK
HDA_SDI1/I2S1_RXD
I2S1_TXD/SNDW2_DATA
I2S1_SFRM/SNDW2_CLK
BB46
BE32
BF33
BE29
R47
AP29
AU3
DRAM_RESET#
GPP_B2/VRALERT#
GPP_B1/GSPI1_CS1#/TIME_SYNC1
GPP_B0/GSPI0_CS1#
GPP_K17/ADR_COMPLETE
GPP_B11/I2S_MCLK
SYS_PWROK
GPP_D8/I2S2_SCLK
GPP_D7/I2S2_RXD
GPP_D6/I2S2_TXD/MODEM_CLKREQ
GPP_D5/I2S2_SFRM/CNV_RF_RESET#
GPP_D20/DMIC_DATA0/SNDW4_DATA
GPP_D19/DMIC_CLK0/SNDW4_CLK
GPP_D18/DMIC_DATA1/SNDW3_DATA
GPP_D17/DMIC_CLK1/SNDW3_CLK
BE45
BF44
BE35
BC37
GPD8/SUSCLK
GPD0/BATLOW#
GPP_A15/SUSACK#
GPP_A13/SUSWARN#/SUSPWRDNACK
RTCRST#
SRTCRST#
PCH_PWROK
RSMRST#
DSW_PWROK
GPP_C2/SMBALERT#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C5/SML0ALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
CNP-H_BGA874
4 OF 13
SYS_PWROK
26
PCIE_WAKE#
LAN_WAKE#
AC_PRESENT
41
1 0_0201_5%
SIO_PWRBTN#
SYS_RESET#
SIO_SLP_S0#
SIO_SLP_S3#
SIO_SLP_S4#
1 0_0201_5%
RH714 2
1 0_0201_5%
SIO_PWRBTN#
LANWAKE#
LANWAKE#
2
1
DH1 @
RB751V40_SC76-2
26
SPKR 24
H_CPUPWRGD
10
+3VS
2
5
64
+VCCIO_PG
PCH_SMBDATA
PCH_SMBCLK
2 1K_0201_5%
PCH_SMBDATA
1
2
10K_0201_5%
IMVP_VR_ON
SIO_SLP_S3#
2
IN1
IN2
MC74VHC1G08DFT2G_SC70-5
OUT
2
MAIN@
1
1
1
E
D
Buffer with Open Drain Output For VTT power control
+3VALW
0.1U_0402_16V7K
2
1
CC298
UC16
1
VR_ON
NC
2
VCC
A
Y
3
5
H_VCCST_PWRGD
4
H_VCCST_PWRGD
GPU ID
10
GND
UMA
N17P-G0
N17E-G1
N17P-G1
74AUP1G07SE-7_SOT353
SA00007WE00
MAIN@
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
A
26
ME_FWP
RH16
1
r
o
F
2 1K_0402_1%
ME_FWP PCH has internal 20K PD.
FLASH DESCRIPTOR SECURITY OVERRIDE
RH552
PCH_AZ_SDOUT
GPU ID2
(GPP_D6)
0
0
1
1
RH551
N17P_G0@
GPU ID1
(GPP_D5)
0
1
0
1
RH553
N17E_G1@
RH551
10K_0201_5%
10K_0201_5%
10K_0201_5%
SD043100280
SD043100280
SD043100280
SD043100280
RH554
RH554
RH552
RH553
UMA@
SD043100280
2
N17P_G0@
10K_0201_5%
SD043100280
N17E_G1@
10K_0201_5%
SD043100280
N17P_G1@
PCH_PWROK
1
4
RH94
10K_0201_5%
RH545
1
2 10K_0201_5%
SIO_PWRBTN#
RH717
1
2 10K_0201_5%
ME_SUS_PWR_ACK
RH506
1
@
2 1M_0402_5%
CLKRUN#
RH701
1
@
2 8.2K_0402_5%
SYS_RESET#
RH737
1
SYS_RESET#
RH571
1
@
2 8.2K_0402_5%
PCH_AZ_RST#
PCH_AZ_BITCLK
SIO_SLP_S3#
SIO_SLP_S4#
HW_ACAV_IN
RH746
RH739
RH740
RH741
RH749
1
1
1
1
1
@
2
2
2
2
2
18,26
SUSCLK_WLAN
SUSCLK_EC
33
26
26
HW_ACAV_IN
26,59,60,61
2 8.2K_0402_5%
@
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
1K_0201_5%
e
r
C
+3V_PCH_PRIM
Reserve for ESD
CH212
2
1 100P_0402_50V8J
ESD@
PCH_RSMRST#
CH209
2
1 100P_0402_50V8J
@ESD@
SYS_RESET#
B
RH66
1
@
2 2.2K_0402_5%
SMBALERT#
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
Enable
Disable
+3V_PCH_PRIM
Reserve for RF please close to UH1
CH51 1
RH64
1
2 2.2K_0402_5%
SML0ALERT#
PCH_AZ_SDOUT
2 10P_0402_25V8J
@RF@
EC interface
HIGH
LOW(DEFAULT)
ESPI*
LPC
+3VALW
@
RH551
10K_0201_5%
@
RH553
10K_0201_5%
@
RH552
10K_0201_5%
@
RH554
10K_0201_5%
1
@
2 150K_0402_5%
SPKR
RH65
1
2 150K_0402_5%
HIGH
LOW(DEFAULT)
PCHHOT#
Enable
Disable
HIGH
LOW(DEFAULT)
Enable
Disable
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SD043100280
SML1ALERT#
A
Top Swap Override (internal PD)
GPU_ID1
GPU_ID2
Issued Date
10K_0201_5%
+3V_PCH_PRIM
RH685
Title
PCH (3/7) PM,HDA,SMB,JTAG
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
D
+3VS
N17P_G1@
10K_0201_5%
10K_0201_5%
Disable ME Protect (ME can be updated)
Enable ME Protect (ME cannot be updated)(Default posit i on)
5
UMA@
UH14
OUT
SA00000OH00
MAIN@
67
PCH_RSMRST#
SYS_PWROK
PCH_DPWROK
2 100K_0201_5%
2 100K_0201_5%
2 100K_0201_5%
@
VR_ON
RZ71
100K_0201_5%
SA00000OH00
B
RH700
RH673
RH90
VR_ON
4
IN2
MC74VHC1G08DFT2G_SC70-5
2
RH676
26
DGPU_PWROK
UZ21
VCC
2 1K_0201_5%
1
GND
1
RH462
1
3
RH463
IMVP_VR_ON
IN1
2
SML0_SMBDATA
2
1
2 499_0402_1%
1
ALL_SYS_PWRGD
2
@
ALL_SYS_PWRGD
1
1
IMVP_VR_PG
IMVP_VR_PG
1
RH502
67
CC302
0.1U_0201_6.3V6K
18,26
CC301
0.1U_0201_6.3V6K
2
SML0_SMBCLK
1
2 499_0402_1%
5
@
ALL_SYS_PWRGD
L
L
1
1
1
ALL_SYS_PWRGD
+3VS
+3VS
RH501
RH105
1
2
0_0201_5%
1
2
0_0201_5%
14,15,32
2
PCH_SMBDATA
1
4
QH4B
DMN65D8LDW-7_SOT363-6
MAIN@
+3VALW
SML0_SMBCLK
SML0_SMBDATA
2 1K_0201_5%
2 1K_0201_5%
VS
3
SMBDATA
RH103
2
1
1
VALW MAIN@
SMBCLK
SMBDATA
+VCCIO_PG
5
2 1K_0201_5%
2 1K_0201_5%
14,15,32
VCC
RH62
RH63
1
1
PCH_SMBCLK
GND
RH674
RH675
RH180
100K_0201_5%
PCH to DDR / FFS
PCH_SMBCLK
1
2 100K_0201_5%
LAN_WAKE#
w
e
i
v
23,26
36,37,41
37,66
RH713 2
XDP_ITP_PMODE
38
CPU_XDP_TCK0
10,38
CPU_XDP_TMS
10,38
CPU_XDP_TDO
10,38
CPU_XDP_TDI
10,38
PCH_JTAG_TCK1
38
QH4A
DMN65D8LDW-7_SOT363-6
6
SMBCLK
2 8.2K_0402_5%
1
+3VS
RH11 2
3
2
+3V_PCH_PRIM
2 1K_0201_5%
1
RH533
+3V_PCH_PRIM
2 0_0201_5% SIO_SLP_S0#
2 0_0201_5% SIO_SLP_S3#
2 0_0201_5% SIO_SLP_S4#
PCH_BATLOW#
TP@ TH148
ME_SUS_PWR_ACK
26,33,34,35,41
1
+3VS
14
1 0_0201_5%
AL3
AH4
AJ4
AH3
AH2
AJ3
ITP_PMODE
PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TCK
H_DRAMRST#
SUSCLK
PCH_BATLOW#
BG44
BG42
BD39
BE46
AU2
AW29
AE3
GPD2/LAN_WAKE#
GPD1/ACPRESENT
SLP_SUS#
GPD3/PWRBTN#
SYS_RESET#
GPP_B14/SPKR
CPUPWRGD
1
RH515
AC_PRESENT
+3V_1.8V_PGPPA
SYS_PWROK
BB47 PCH_PCIE_WAKE#RH4 2
BE40
BF40
BC28 SIO_SLP_S0#_PCH
RH682 1
BF42 SIO_SLP_S3#_PCH
RH683 1
BE42 SIO_SLP_S4#_PCH
RH684 1
BC42
WAKE#
GPD6/SLP_A#
SLP_LAN#
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
RH453
PCH_BATLOW#
+3V_1.8V_PGPPA
BD42
GPD9/SLP_WLAN#
HDACPU_SDO
HDACPU_SDI
HDACPU_SCLK
CLKRUN#
BF41
GPD11/LANPHYPC
D
2
RTCRST_ON
RH84 1
BE10
BF10
BE12
BD12
HDA_BCLK/I2S0_SCLK
HDA_SDI0/I2S0_RXD
HDA_SDO/I2S0_TXD
HDA_SYNC/I2S0_SFRM
PCH_SRTCRST#
2 20K_0402_5%~D
CH52
1U_0603_10V6K~D
23,26
BD11
BE11
BF12
BG13
PCH_PCIE_WAKE#
Thursday, March 22, 2018
1
Sheet
18
of
78
5
4
3
2
1
Main Func = PCH
Update OK
CNP-H
G17
F16
A17
B17
R21
P21
B18
C18
K18
J18
B19
C19
N18
R18
D20
C20
F20
G20
B21
A22
K21
J21
D21
C21
B23
C23
J24
L24
F24
G24
B24
C24
C
DMI0_RXN
DMI0_RXP
DMI0_TXN
DMI0_TXP
DMI1_RXN
DMI1_RXP
DMI1_TXN
DMI1_TXP
DMI2_RXN
DMI2_RXP
DMI2_TXN
DMI2_TXP
DMI3_RXN
DMI3_RXP
DMI3_TXN
DMI3_TXP
DMI7_TXP
DMI7_TXN
DMI7_RXP
DMI7_RXN
DMI6_TXP
DMI6_TXN
DMI6_RXP
DMI6_RXN
DMI5_TXP
DMI5_TXN
DMI5_RXP
DMI5_RXN
DMI4_TXP
DMI4_TXN
DMI4_RXP
DMI4_RXN
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4#
PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5#
PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6#
PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN
PCIE2_RXP/USB31_8_RXP
USB2_COMP
PCIE2_TXN/USB31_8_TXN
USB2_VBUSSENSE
PCIE2_TXP/USB31_8_TXP
RSVD1
PCIE3_RXN/USB31_9_RXN
USB2_ID
PCIE3_RXP/USB31_9_RXP
PCIE3_TXN/USB31_9_TXN
GPD7
PCIE3_TXP/USB31_9_TXP
PCIE4_RXN/USB31_10_RXN
PCIE24_TXP
PCIE4_RXP/USB31_10_RXP
PCIE24_TXN
PCIE4_TXN/USB31_10_TXN
PCIE24_RXP
PCIE4_TXP/USB31_10_TXP
PCIE24_RXN
PCIE5_RXN
PCIE23_TXP
PCIE5_RXP
PCIE23_TXN
PCIE5_TXN
PCIE23_RXP
PCIE5_TXP
PCIE23_RXN
PCIE6_RXN
PCIE22_TXP
PCIE6_RXP
PCIE22_TXN
PCIE6_TXN
PCIE22_RXP
PCIE6_TXP
PCIE22_RXN
PCIE7_TXP
PCIE21_TXP
PCIE7_TXN
PCIE21_TXN
PCIE7_RXP
PCIE21_RXP
PCIE7_RXN
PCIE21_RXN
PCIE8_RXN
PCIE8_RXP
PCIE8_TXN
2 OF 13
PCIE8_TXP
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
J3
J2
N13
N15
K4
K3
M10
L9
M1
L2
K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6
AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N11
USB20_P11
TP@
TP@
USB20_N14
USB20_P14
TP@
TP@
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB3.0 Port1
USB3_PTX_DRX_N1
USB3_PTX_DRX_P1
USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
UH1F
F9
F7
D11
C11
C3
D4
B9
C9
B
C17
C16
G14
F14
C15
B15
J13
K13
USB3.0 Port2
27
27
27
27
USB3_PTX_DRX_P3
USB3_PTX_DRX_N3
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3
USB3_PTX_DRX_P3
USB3_PTX_DRX_N3
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3
G12
F11
C10
B10
r
o
F
C14
B14
J15
K16
A
5
4
USB31_2_TXN
USB31_2_TXP
USB31_2_RXN
USB31_2_RXP
USB31_6_TXN
USB31_6_TXP
USB31_6_RXN
USB31_6_RXP
USB31_5_TXN
USB31_5_TXP
USB31_5_RXN
USB31_5_RXP
USB31_3_TXP
USB31_3_TXN
USB31_3_RXP
USB31_3_RXN
USB31_4_TXP
USB31_4_TXN
USB31_4_RXP
USB31_4_RXN
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
RH109
RH580
1
1
2 113_0402_1%
2 1K_0201_5%
RH581
1
2 1K_0201_5%
BE41
GPD_7
PCIE_PTX_DRX_P24
PCIE_PTX_DRX_N24
PCIE_PRX_DTX_P24
PCIE_PRX_DTX_N24
PCIE_PTX_DRX_P23
PCIE_PTX_DRX_N23
PCIE_PRX_DTX_P23
PCIE_PRX_DTX_N23
PCIE_PTX_DRX_P22
PCIE_PTX_DRX_N22
PCIE_PRX_DTX_P22
PCIE_PRX_DTX_N22
PCIE_PTX_DRX_P21
PCIE_PTX_DRX_N21
PCIE_PRX_DTX_P21
PCIE_PRX_DTX_N21
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
GPP_A0/RCIN#/ESPI_ALERT1#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_K19/SMI#
GPP_K18/NMI#
GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
6 OF 13 GPP_F5/SATA_DEVSLP3
BB39
AW37
AV37
BA38
ESPI_IO0
ESPI_IO1
ESPI_IO2
ESPI_IO3
BE38
AW35
BA36
BE39
BF38
ESPI_CS#
ESPI_ALERT#
PIRQA#
BB36
BB34
ESPI_RESET#
ESPI_CLK
RPH6
USB2_COMP
50ohm single-ended and as short as possible
Spacing=15 mils
Max length= 1000 mils
27
27
USB2_ID
PCIE_PTX_DRX_P24
PCIE_PTX_DRX_N24
PCIE_PRX_DTX_P24
PCIE_PRX_DTX_N24
PCIE_PTX_DRX_P23
PCIE_PTX_DRX_N23
PCIE_PRX_DTX_P23
PCIE_PRX_DTX_N23
PCIE_PTX_DRX_P22
PCIE_PTX_DRX_N22
PCIE_PRX_DTX_P22
PCIE_PRX_DTX_N22
PCIE_PTX_DRX_P21
PCIE_PTX_DRX_N21
PCIE_PRX_DTX_P21
PCIE_PRX_DTX_N21
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
L
L
E
D
USB31_1_TXN
USB31_1_TXP
USB31_1_RXN
USB31_1_RXP
+3V_PCH_PRIM
TH142
TH141
USB2_COMP
USB2_VBUSSENSE
G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43
TBT-AR
e
r
C
+3V_PCH_PRIM
RH12
100K_0201_5%
GPD_7
@
RH705
10K_0201_5%
X'tal Input:
High: Differential
Low: Single ended
RPH7
8
7
6
5
1
2
3
4
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
26
26
26
26
+1.8V_PRIM
15_0804_8P4R_5%
ESPI_CS#
26
ESPI_ALERT#
26
ESPI_CLK_R
1 EMI@ 2
RH658
15_0402_5%
ESPI_RESET#
26
ESPI_CLK_R
26
T48
T47
AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48
w
e
i
v
D
10K_8P4R_5%
4
5
3
6
2
7
1
8
USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#
-----> BT & CNVi BRI use
-----> Touch Screen
-----> Finger Printer
F4
F3
U13
G3
CNP-H
USB3_PTX_DRX_N1
USB3_PTX_DRX_P1
USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
-----> Port 1, USB3.0 (MB)
-----> Port 3, USB2.0 (IO/B)
-----> Port 2, USB3.0 (MB)
-----> TYPEC PD
-----> CCD
-----> Card Reader (IO/B)
TH145
TH143
USB_OC0#
USB_OC1#
CNP-H_BGA874
27
27
27
27
27
27
27
27
27
27
40
40
29
29
27
27
33
33
29
29
28
28
1
UH1B
K34
J35
C33
B33
G33
F34
C32
B32
K32
J32
C31
B31
G30
F30
C29
B29
A25
B25
P24
R24
C26
B26
F26
G26
B27
C27
L26
M26
D29
E28
K29
M29
2
D
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
1
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
9 DMI_CRX_PTX_N0
9 DMI_CRX_PTX_P0
9 DMI_CTX_PRX_N1
9 DMI_CTX_PRX_P1
9 DMI_CRX_PTX_N1
9 DMI_CRX_PTX_P1
9 DMI_CTX_PRX_N2
9 DMI_CTX_PRX_P2
9 DMI_CRX_PTX_N2
9 DMI_CRX_PTX_P2
9 DMI_CTX_PRX_N3
9 DMI_CTX_PRX_P3
9 DMI_CRX_PTX_N3
9 DMI_CRX_PTX_P3
2
9
9
SSD_DEVSLP
HDD_DEVSLP
SSD_DEVSLP
HDD_DEVSLP
PIRQA#
RH546
1
2 10K_0201_5%
ESPI_ALERT#
RH578
1
2 8.2K_0402_5%
USB_OC0#
CH228
ESPI_RESET#
RH743
1
B
2 0.1U_0402_10V7K
1
2 100K_0201_5%
34
32
CNP-H_BGA874
Reserve for EMI
ESPI_CLK
CC57 2
@EMI@
1
12P_0402_50V8J
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (4/7) DMI,PCIE,USB,LPC
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
19
of
78
5
4
3
2
1
Main Func = PCH
+3V_PCH_PRIM
+3VS
GSYNC_ID
D
2 8.2K_0402_5%
WLAN_RADIO_DIS#
1
2 10K_0201_5%
SIO_EXT_SCI#
2
1 49.9K_0402_1%
UART_2_CRXD_DTXD
2
1 49.9K_0402_1%
UART_2_CTXD_DRXD
RH520
1
RH521
RH709
RH710
@
RH29
RH30
1GSYNC@ 2 10K_0201_5%
1
2 10K_0201_5%
NGSYNC@
w
e
i
v
+3V_PCH_PRIM
RTC_DET#
RH734
1
SIO_EXT_WAKE# RH721
1
CPU_ID
1
1
D
2 10K_0201_5%
@
2 10K_0201_5%
+3V_PCH_PRIM
+3VALW
1
RH707
2 8.2K_0402_5%
@
2 8.2K_0402_5%
@
BT_RADIO_DIS#
CNP-H
UH1K
WLAN_RADIO_DIS#
29
3.3V_TS_EN
17,32
FFS_INT1
29 DBC_PANEL_EN
GPU_GC6_FB_EN_H
48 GPU_EVENT#
48,56
TP@PAD
33
44
BT_RADIO_DIS#
31
31
BA26
BD30
AU26
AW26
NRB_BIT
BE30
BD29
BF29
BB26
GPU_GC6_FB_EN_H
T4937EDP_SW
BB24
BE23
AP24
BA24
CPU_ID
BT_RADIO_DIS#
BD21
AW24
AP21
AU24
HDMI_HPD_PCH
26 SIO_EXT_WAKE#
33 UART_2_CTXD_DRXD
33 UART_2_CRXD_DTXD
C
BBS_BIT0
3.3V_TS_EN
SIO_EXT_SCI#
FFS_INT1
AV21
AW21
BE20
BD20
SIO_EXT_WAKE#
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD
BE21
BF21
BC22
BF23
I2C1_SCL_TCH_PAD
I2C1_SDA_TCH_PAD
BE15
BE14
GPP_B22/GSPI1_MOSI
GPP_B21/GSPI1_MISO
GPP_B20/GSPI1_CLK
GPP_B19/GSPI1_CS0#
GPP_B18/GSPI0_MOSI
GPP_B17/GSPI0_MISO
GPP_B16/GSPI0_CLK
GPP_B15/GSPI0_CS0#
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
GPP_D14/ISH_UART0_TXD/I2C2_SCL
GPP_D13/ISH_UART0_RXD/I2C2_SDA
GPP_C9/UART0_TXD
GPP_C8/UART0_RXD
GPP_C11/UART0_CTS#
GPP_C10/UART0_RTS#
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C23/UART2_CTS#
GPP_C22/UART2_RTS#
GPP_C21/UART2_TXD
GPP_C20/UART2_RXD
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
GPP_C19/I2C1_SCL
GPP_C18/I2C1_SDA
GPP_C17/I2C0_SCL
GPP_C16/I2C0_SDA
BA20
BB20
BB16
AN18
DGPU_HOLD_RST#
WLAN_RADIO_DIS#
DGPU_PWR_EN
BF14
AR18
BF17
BE17
DGPU_HOLD_RST#
48
WLAN_RADIO_DIS#
33
DGPU_PWR_EN
56
CNVi_EN#
GSYNC_ID
CNVi_EN#
AG45
AH46
AH47
AH48
RTC_DET#
AV34
AW32
BA33
BE34
BD34
BF35
BD38
DGPU_PRSNT#
1
Follow CRB REV0.9 PU 4.7K
1
RH671
2 4.7K_0402_5%~D
CNV_BRI_PTX_DRX
E
D
CNP-H
UH1M
This signal has a weak internal pull-down.
0 = 38.4/19.2MHz XTAL frequency selected. (Default)
1 = 24MHz XTAL frequency selected.
Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
2. This signal is in the primary well.
41
TBT_CIO_PLUG_EVENT#
B
31
KB_LED_BL_DET
TBT_CIO_PLUG_EVENT#
KB_LED_BL_DET
M.2 CNV Mode Select
AP3
AP2
AN4
AM7
+1.8V_PRIM
1 CNV@
RH588
RH589 2
@
CNV_RGI_PTX_DRX
2
20K_0402_5%
1 10K_0402_5%
36
CPU_VCCIO_PWR_GATE#
CPU_VCCIO_PWR_GATE#
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
+1.8V_PRIM
RH93
r
o
F
The signal has a weak internal pull-down
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin
strap must be a ‘ 1’ for the proper functionality
of the SPI (Flash) I/Os
2
1 10K_0402_5%
@
1
RH719
2 10K_0201_5%
@
1
@
2
CNV_BRI_PRX_DTX
RH614
GPP_J9
AV6
AY3
AR13
AV7
AW3
AT10
AV4
AY2
BA4
AV3
AW2
AU9
GPP_G0/SD_CMD
GPP_G1/SD_D0
GPP_G2/SD_D1
GPP_G3/SD_D2
GPP_G4/SD_D3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
CNV_WR_CLKN
CNV_WR_CLKP
CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P
CNV_WT_CLKN
CNV_WT_CLKP
GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2
GPP_I14/M2_SKT2_CFG3
GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_VCCIO_PWR_GATE#
GPP_J11/A4WP_PRESENT
GPP_J10
GPP_J_2
GPP_J_3
GPP_J_4_CNV_BRI_DT_UART0_RTSB
GPP_J5/CNV_BRI_RSP/UART0_RXD
GPP_J6/CNV_RGI_DT/UART0_TXD
GPP_J7/CNV_RGI_RSP/UART0_CTS#
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD
13 OF 13
CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P
CNV_WT_RCOMP
PCIE_RCOMPN
PCIE_RCOMPP
SD_RCOMP_1P8
SD_RCOMP_3P3
GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83
RSVD2
RSVD3
RSVD1
TP
BD4
BE3
CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P
BB3
BB4
BA3
BA2
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CNV_PRX_DTX_N1
CNV_PRX_DTX_P1
BC5
BB6
CLK_CNV_PTX_DRX_N
CLK_CNV_PTX_DRX_P
BE6
BD7
BG6
BF6
BA1
CNV_PTX_DRX_N0
CNV_PTX_DRX_P0
CNV_PTX_DRX_N1
CNV_PTX_DRX_P1
CNV_WT_RCOMP RH667 1
2 150_0402_1%
B12
A13
BE5
BE4
BD1
BE1
BE2
PCIE_RCOMPN
PCIE_RCOMPP
SD_RCOMP_1P8
SD_RCOMP_3P3
RH669 1
2 100_0402_1%
RH668 1
RH670 1
2 200_0402_1%
2 200_0402_1%
GPPJ_RCOMP_1P8
RH666 1
2 200_0402_1%
23
31
RH23
RH24
2 10K_0201_5%
2 10K_0201_5%
@
+3VS
DGPU_PWR_EN
RH537
1
2 10K_0201_5%
1
2 10K_0201_5%
+3V_1.8V_PGPPA
KB_DET#
RH128
+3V_PCH_PRIM
RH130
1
@
BBS_BIT0
2 2.2K_0402_5%
Boot BIOS Strap Bit (internal PD)
LPC
SPI
HIGH
LOW(DEFAULT)
+3V_PCH_PRIM
RH524 1
@
2 2.2K_0402_5%
NRB_BIT
NO REBOOT mode (internal PD)
CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CNV_PRX_DTX_N1
CNV_PRX_DTX_P1
Enable
Disable
33
33
33
33
CLK_CNV_PTX_DRX_N
CLK_CNV_PTX_DRX_P
CNV_PTX_DRX_N0
CNV_PTX_DRX_P0
CNV_PTX_DRX_N1
CNV_PTX_DRX_P1
HIGH
LOW(DEFAULT)
33
33
B
33
33
33
33
33
33
Y35
Y36
BC1
AL35
TP@
TH101
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point
CNP-H_BGA874
A
20K_0402_5%
CNV_RGI_PRX_DTX
1
2
@
RH613
20K_0402_5%
CFL PDG rev0.5
To avoid floating input at the I/O pin it is recommended
to add a weak pull up resistor to the SOC pin with a recommended value of 20K ohm.
5
C
CPU_VCCIO_PWR_GATE#
+1.8V_PRIM
A
33 CNV_BRI_PTX_DRX
33 CNV_BRI_PRX_DTX
33 CNV_RGI_PTX_DRX
33 CNV_RGI_PRX_DTX
CNV_BRI_PTX_DRX
CNV_BRI_PRX_DTX
CNV_RGI_PTX_DRX
CNV_RGI_PRX_DTX
GPP_J9
+1.8V_PRIM
AW13
BE9
BF8
BF9
BG8
BE8
BD8
AV13
RH135
10K_0201_5%
L
L
@
+1.8V_PRIM
e
r
KB_DET#
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874
33
RTC_DET#
KB_DET#
2
1
RH706
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (5/7) I2C,GPIO,CNVI
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
20
of
78
A
B
C
D
E
Main Func = PCH
+RTC_CELL_PCH
+RTC_CELL
+1.05VALW
5.95A
2
1
2
CH13
1U_0402_6.3V6K
2
Close to UC1.U26
1
CH12
22U_0402_6.3V6M
1
CH62
1U_0402_6.3V6K
Close to UC1.AA22
PLACE 3-5MM FROM PACKAGE EDGE
+1.05VALW
6.6A
+1.05VALW
AD31
0.2A
AE17
0.42A
W22
W23
+1.05VALW
+1.05V_LDO
+1.05V_LDO
+1.05V_LDO
+1.05VALW
2
CH16
1U_0402_6.3V6K
1
0.109A
BG45
BG46
W31
+1.05VALW
0.015A
0.213A
+1.05VALW
1 +1.05V_VCCAMPHYPLL
0_0603_5%
+1.05V_XTAL
2
1
0_0603_5%
2
RH732
+1.05VALW
RH731
+1.05VALW
2
0.00428A
0.169A
+1.05VALW
+1.05VALW
0.0198A
+1.05VALW
P2
P3
W19
W20
C1
C2
V19
VCCRTC1
VCCRTC2
VCCPGPPG_3P3
VCCPRIM_3P33
VCCPRIM_3P34
VCCPGPPHK1
VCCPGPPHK2
VCCPGPPEF1
VCCPGPPEF2
VCCPRIM_1P0523
VCCPRIM_1P0524
VCCPRIM_1P0525
VCCPRIM_1P0526
VCCPRIM_1P0527
VCCPRIM_1P0528
VCCPRIM_1P0529
VCCPGPPD
VCCPGPPBC1
VCCPGPPBC2
VCCPRIM_1P0514
VCCPGPPA
VCCPRIM_1P0515
VCCPRIM_3P31
VCCDSW_3P31
VCCDSW_3P32
VCCDUSB_1P051
VCCDUSB_1P052
VCCHDA
VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87
VCCDSW_1P051
VCCDSW_1P052
VCCPRIM_MPHY_1P05
VCCPRIM_1P0521
VCCPRIM_1P0522
VCCAMPHYPLL_1P051
VCCAMPHYPLL_1P052
VCCAMPHYPLL_1P053
VCCPRIM_1P81
VCCPRIM_1P82
VCCPRIM_1P0520
VCCPRIM_1P0519
VCCPRIM_1P241
VCCPRIM_1P242
VCCA_XTAL_1P051
VCCA_XTAL_1P052
VCCA_SRC_1P051
VCCA_SRC_1P052
VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243
VCCAPLL_1P054
VCCAPLL_1P055
VCCA_BCLK_1P05
VCCMPHY_SENSE
VSSMPHY_SENSE
L
L
B1
B2
B3
0.021A
VCCAPLL_1P051
VCCAPLL_1P052
VCCAPLL_1P053
+VCCRTCEXT
V23
+3V_PCH_PRIM
+3V_PCH_PRIM
0.095A
2
+RTC_CELL_PCH
BC49
BD49
+3V_PCH_PRIM
+3V_PCH_PRIM
+3V_PCH_PRIM
AN21
AY8
BB7
0.195A
AC35
AC36
AE35
AE36
0.262A
AN24
AN26
AP26
0.14A
AN32
0.101A
AT44
BE48
BE49
0.106A
0.97A
@
2
Close to UC1.D1
2
Check OK 1
2
@
Close to UC1.C1
3
+1.05VALW
E
D
CH23
1U_0402_6.3V6K
2
+1.05VALW
CH22
0.1U_0402_10V6K
@
1
1
CH223
1U_0402_6.3V6K
1
CH17
1P_0402_50V8
2
CH24
1P_0402_50V8
1
+1.05VALW
1 close UC1.C1 and <120mil
2
CC42
0.5P_0402_50V8
RF@
close UC1.C1 and <120mil
+1.05VALW
+1.05V_VCCAMPHYPLL
1
0.113A
BB14
AG19
AG20
AN15
AR15
BB11
0.00767A
e
r
0.766A
AF19
AF20
CC41
0.5P_0402_50V8
RF@
+5VALW
A
1
@
RH162
2
0_0402_5%
Close
0.193A
0.0895A
+1.05VALW
+1.05VALW
AJ22
AJ23
BG5
to
2
AG20,AN15
For DDX30 R02
2
+1.24V_PRIM_MAR
+1.24V_VCCLDOSRAM_IN
+1.24V_PRIM_DPHY
+1.24V_PRIM_MAR
VCCMPHY_SENSE
VSSMPHY_SENSE
K47
K46
TP@ TH139
TP@ TH138
RH736
1.24V for CNVi logic.
Can be NC if project do not use CNVI ?
+1.24V_VCCLDOSRAM_IN
1
RH174
1
+1.24V_PRIM_DPHY
2
2 0_0402_5%
RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
+1.8V_PHVLDO
1
@
2 0_0402_5%
8/17 separate +1.8V_PRIM and +1.8V_PHVLDO
3
+3V_1.8V_PGPPA
+3V_PCH_PRIM
+1.8V_PRIM
RH143
1
@
2 0_0402_5%
RH150
2
@
1 0_0402_5%
@
CH63 1
2 1P_0402_50V8
+3VALW_DSW
+3V_PCH_PRIM
+3V_PCH_PRIM
1 0.1U_0402_10V6K
CH33
2
+3VALW_DSW +3V_PCH_PRIM
1
2
51_0402_5%
1
@
10K_0402_5%
@
Close to UC1.AE35
1 0.1U_0402_10V6K
CH32
2
Close to UC1.AC35
2
PCH_PRIM_EN
1
2
1
2
Close to UC1.AY8
QH10B
@
QH10A
@
PCH_PRIM_EN 2
2
5
6
Close to UC1.P2
26,37,65,66
@
RH747
1
Close to UC1.C49
close UC1.BB14 and <120mil
CC43
0.5P_0402_50V8
RF@
2
+1.05VALW
@
4
1
1
+1.8V_PHVLDO
2
0_1206_5%
CH30
0.1U_0402_10V6K
2
@
CH31
1U_0402_6.3V6K
2
1
2
+1.8V_PRIM
0.882A
AG31
AF31
AK22
AK23
+3V_PCH_PRIM
+3VALW_DSW
+3V_PCH_PRIM
RH748
CH20
22U_0402_6.3V6M
@
1
+1.05V_XTAL
CH19
1U_0402_6.3V6K
2
CH18
22U_0402_6.3V6M
1
Discharge
RH89 1
2
1
+1.8V_PRIM
+3V_PCH_PRIM
CH34
0.1U_0402_10V6K
r
o
F
@
2
Close to UC1.BC49
1
1
2
2
1
3
Close to UC1.W22
1
CH14
0.1U_0402_10V6K
2
CH15
0.1U_0402_10V6K
Close to UC1.W31
1
Check OK 1
4
+1.05VALW
CH21
1U_0402_6.3V6K
+1.05VALW
+VCCRTCEXT
+3V_1.8V_PGPPA
+3V_PCH_PRIM
0.334A
8 OF 13
+3VALW
2
+3V_PCH_PRIM
+1.8V_PRIM
+1.05VALW
1
+3V_PCH_PRIM
0.174A
CNP-H_BGA874
+1.05VALW
1
w
e
i
v
AN44
CH36
4.7U_0402_6.3V6M
0.0085A
D1
E1
C49
D49
E49
VCCSPI
0.182A
BF47
BG47
CH29
1U_0402_6.3V6K
0.0012A
VCCPRIM_3P35
AW9
CH35
4.7U_0402_6.3V6M
Deep Sx Well: 1.05V. This rail is generated by on die DSW low dropout (LDO)
+1.05VALW
linear regulator to supply DSW core logic. Board needs to connect a 1uF capacitor
to this rail and power should NOT be driven from the board.
U26
U29
V25
V27
V28
V30
V31
DCPRTC1
DCPRTC2
CH25
0.1U_0402_10V6K
+1.05VALW
VCCPRIM_3P32
CH226
1U_0402_6.3V6K
+1.05VALW
VCCPRIM_1P051
VCCPRIM_1P052
VCCPRIM_1P053
VCCPRIM_1P054
VCCPRIM_1P055
VCCPRIM_1P056
VCCPRIM_1P057
VCCPRIM_1P058
VCCPRIM_1P059
VCCPRIM_1P0510
VCCPRIM_1P0511
VCCPRIM_1P0512
VCCPRIM_1P0513
VCCPRIM_1P0516
VCCPRIM_1P0517
VCCPRIM_1P0518
CH225
0.1U_0402_10V6K
1
AA22
AA23
AB20
AB22
AB23
AB27
AB28
AB30
AD20
AD23
AD27
AD28
AD30
AF23
AF27
AF30
GEN8@
1
2
RH697 0_0402_5%
+3V_PCH_PRIM
CNP-H
UH1H
DMN53D0LDW-7_SOT363-6
SB000018X00
4
DMN53D0LDW-7_SOT363-6
SB000018X00
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (6/7) POWER
Size
B
C
D
Document Number
R ev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
E
21
of
78
5
4
3
2
1
Main Func = PCH
w
e
i
v
D
CNP-H
CNP-H
UH1L
UH1I
A2
A28
A3
A33
A37
A4
A45
A46
A47
A48
A5
A8
AA19
AA20
AA25
AA27
AA28
AA30
AA31
AA49
AA5
AB19
AB25
AB31
AC12
AC17
AC33
AC38
AC4
AC46
AD1
AD19
AD2
AD22
AD25
AD49
AE12
AE33
AE38
AE4
AE46
AF22
AF25
AF28
AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38
AJ19
AJ20
AJ25
AJ27
AJ28
AJ30
AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31
AK4
AK46
C
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28
r
o
F
9 OF 13
BG3
BG33
BG37
BG4
BG48
C12
C25
C30
C4
C48
C5
D12
D16
D17
D30
D33
D8
E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42
E8
F41
F43
F47
G44
G6
H8
J10
J26
J29
J4
J40
J46
J47
J48
J9
K11
K39
M16
M18
M21
5
12 OF 13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9
L
L
CNP-H
UH1J
RSVD7
RSVD8
RSVD6
RSVD5
RSVD3
RSVD4
E
D
CNP-H_BGA874
CNP-H_BGA874
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD2
RSVD1
PREQ#
PRDY#
CPU_TRST#
TRIGGER_OUT
TRIGGER_IN
D
e
r
Y14
Y15
U37
U35
N32
R32
AH15
AH14
TP@
TP@
TP@
TP@
TH1
TH2
TH3
TH4
TP@
TP@
TH5
TH6
TP@
TP@
TH7
TH8
C
To be confirm
AL2
AM5
AM4
AK3
AK2
XDP_PREQ#
XDP_PRDY#
CPU_XDP_TRST#
PCH_TRIGOUT RH6651
CPU_TRIGOUT_R
2 30_0402_5% PCH_TRIGOUT_R
XDP_PREQ# 10,38
XDP_PRDY# 10,38
CPU_XDP_TRST# 10,38
PCH_TRIGOUT_R 13
CPU_TRIGOUT_R 13
B
10 OF 13
CNP-H_BGA874
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
2017/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (7/7) VSS
Size
3
2
R ev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
22
of
78
4
2
1
UTPM1
+3VS
SA0000AQ200
SA00008EL90
750@
650@
S IC NPCT750JAAYX QFN 32P TPM
S IC NPCT650VBBYX QFN 32P TPM
RTPM7 1
RTPM6 1 TPM@
TPM_PIRQ#
10K_0402_5%
CTPM1
0.1U_0402_16V7K
TPM@
1
1
2
2
w
e
i
v
1
2
UTPM1 place colse to UH4
E
D
1
BAS40C_SOT23-3
MAIN@
C1
0.47U_0402_6.3V6K
@
5
S
D
3
B
D7
2
GEN9_M@
1
RB751S40T1G_SOD523-2
D
2
1
R78 GEN9@
2
RTCRST_ON
RTCRST_ON
G
1M_0402_5%
S
20
1
2
Q1
2N7002K_SOT23-3
MAIN@
1
2
1
D
S
RTC_DET#
+RTC_CELL
Q25
L2N7002WT1G_SC-70-3
GEN9_M@
C
18,26
C61 @
0.1U_0402_25V6
1
2
2
CTPM3, CTPM4: colse to Pin8
R79 GEN9@
100K_0402_5%
2
G
3
2
C60 GEN9@
22P_0402_50V8J
r
o
F
R2
10M_0402_5%
1
1
anode
cathode
anode
1
2
1
Q26 GEN9_M@
LP2301ALT1G_SOT23-3
R73 GEN9@
10K_0402_5%
3
C59 GEN9@
1U_0402_6.3V6K
RTC_PWR
2
D1
2
R1
1K_0402_5%
2
1
B
2
1
+3VLP
1
1
CTPM5, CTPM6: colse to Pin14
CTPM7: colse to Pin22
3
+RTC_VCC
1
+3V_PCH_PRIM
0_0402_5%
+RTC_CELL_PCH
1
+RTC_CELL
A
L
L
GEN9@
2
Main Func = RTC
2
@
RTPM10
e
r
9
16
23
32
33
12
NPCT650VB2YX_QFN32_5X5
@
NPCT650:TPM@/650@/650@750@
NPCT750:TPM@/750@/650@750@
ChinaTPM:TPM@/cTPM@
SW TPM:fTPM@
1
+3VS
0_0402_5%
CTPM5 TPM@
10U_0402_6.3V6M
PP
TEST
GND1
GND2
GND3
GND4
PGND
Reserved
2
RTPM8
CTPM6 TPM@
0.1U_0402_10V7K
C
LCLK/SCLK
LFRAME#/SCS#
LRESET#/SPI_RST#/SRESET#
SERIRQ
CLKRUN#/GPIO4/SINT#
LPCPD#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
2
7
10
11
25
26
31
CTPM7 TPM@
0.1U_0402_10V7K
2
1
17 PCH_SPI_CLK_R
17 PCH_SPI_CS2#
17,26,33,34,35,41,48
PLTRST#
PCH_SPI_CLK_TPM 19
20
17
27
13
28
RTPM4
4
10K_0402_5%
5
650@
2 33_0402_5%
LAD0/MISO
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3
8
14
22
2
TPM_PIRQ#
RTPM3 1 TPM@
24
21
18
15
VDD1
VHIO1
VHIO2
CTPM4 TPM@
10U_0402_6.3V6M
17
PCH_SPI_SO_TPM
PCH_SPI_SI_TPM
TPM_PIRQ#
2 33_0402_5%
2 33_0402_5%
GPIO0/SDA
GPIO1/SCL
GPIO2/GPX
GPIO3/BADD
1
CTPM3 TPM@
0.1U_0402_10V7K
RTPM1 1 TPM@
RTPM2 1 TPM@
17 PCH_SPI_SO_R
17,38 PCH_SPI_SI_R
D
+3VS
VSB
2
SIO_SLP_S0#
2 0_0402_5%
CTPM2
10U_0402_6.3V6M
TPM@
1
18,26
29
30
3
6
+3VALW
2 0_0402_5%
Place CTPM1,CTPM2 as close as UTPM.1
UTPM1
2 750@
1
RTPM11
0_0402_5%
2 650@
1
RTPM12
0_0402_5%
@
1
1 TPM@
RTPM9
2
2
UTPM1
+3V_PCH_PRIM
D
3
G
5
Main Func = TPM TPM@, cTPM@
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
TPM/RTC/Screw Holes
Size
3
2
Rev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
23
of
78
5
4
Main Func = Audio
3
2
1
EMI@, RF@, @EMI@, @ESD@, @RF@
moat
0_0603_1%
1
1
3
1
2
0_0402_5%
@
2
29
1
2
Layout Note:
Layout Note:
Close pin39
Close pin34
1
L5
DMIC_CLK_EDP
1
CA40
10P_0402_50V8J
@RF@
2
DMIC_CLK
2 BLM15PX221SN1D_2P
CA9,L5 place colse to UA1.3
CA9
6.8P_0402_50V
@RF@
G
2
DMIC_DATA
33_0402_5%
1
2
2
EMI_M@
change to shortpad 11/23 2
CA12
w
e
i
v
Place close to Pin 26
+3VS
1
Close pin33
AUD_AGND
+1.8V_CPVDD
AUD_AGND
1
2
0_0402_5%
@
RA6
change to shortpad 11/23
2
1 CA14
RA8
1
RA41
CA20 1
CA21 1
CA22 1
AUD_AGND
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
25
RA10
AUD_SENSE_A
1 100K_0402_5%
2
200K_0402_1%
DMIC_DATA
DMIC_CLK
10
2
3
40
LDO1_CAP
LDO2_CAP
LDO3_CAP
21
32
6
AUD_SPK_L+
AUD_SPK_LAUD_SPK_RAUD_SPK_R+
35
36
37
38
AUD_SENSE_A
12
AUD_AGND
B
4
29
33
AVSS1
AVSS2
THERMAL_PAD
18
17
11
25
26
RA12
1
CA26
2 SLEEVE 25
10U_0603_6.3V6M
RING2
MIC_CAP
LINE1_L
LINE1_R
AUD_PC_BEEP
1
1
moat
2 0_0402_5%
@
@
2
0_0402_5% 10 mils
change to shortpad 11/23
Layout Note:
Width>40mil, to improve
Headpohone Crosstalk noise
Change it to sharp will be better.
Add 2 vias (>0.5A) when trace layer
change.
25
AUD_AGND
25
25
AUD_HP1_JACK_L
AUD_HP1_JACK_R
25
25
19
31
41
moat
change to shortpad 11/23
RA17 1
RA18 1
AUD_AGND
1
2
3
4
G1
G2
2
ACES_50224-00401-001
CONN@
SP02000GC10
Net name
Pin1
SPK_R+
Pin2
SPK_R-
Pin3
SPK_L+
Pin4
SPK_L-
2 0_0402_5%
2 0_0402_5%
B
AUD_AGND
RA22 1
2
CONN Pin
@
@
AUD_AGND
1
1
2
1
2
AUD_AGND
to shortpad 11/23
@ change
2
0_0805_5%
Layout Note:
Tied at point only under
Codec or near the Codec
Place on the moat between GND & GNDA.
DA3
L03ESDL5V0CC3-2_SOT23-3
3
DA2
2
1
2
3
4
5
6
L03ESDL5V0CC3-2_SOT23-3
DA1
2
@ESD@
1
EMI@ CA30
2
1
1000P_0402_50V7K
EMI@ CA29
2
1
1000P_0402_50V7K
1
1000P_0402_50V7K
2
EMI@ CA28
3
5
1
LINE1-L
LINE1-R
PCBEEP
HP-OUT-L
HP-OUT-R
HP/LINE1_JD1
E
D
JSPK1
AUD_SPK_R+_C
AUD_SPK_R-_C
AUD_SPK_L+_C
AUD_SPK_L-_C
BLM15PD800SN1D_2P
BLM15PD800SN1D_2P
BLM15PD800SN1D_2P
BLM15PD800SN1D_2P
1000P_0402_50V7K
EMI@ CA27
A
CPVDD
20
SPK-OUT-LP
SPK-OUT-LN
SPK-OUT-RN
SPK-OUT-RP
13
14
15
10 mils
C
+3VALW +RTC_CELL
0.1U_0402_25V6
EMI@
CA51
EMI_M@ 2
EMI_M@ 2
EMI_M@ 2
EMI_M@ 2
MIC2-L/RING2
MIC2-R/SLEEVE
MIC2-CAP
RA11
2
1U_0603_16V7
AUD_AGND
0.1U_0402_25V6
EMI@
CA52
r
o
F
1
1
1
1
CPVEE
e
r
1
CA25
Speaker
Speaker trace width >40mil @ 2W4ohm speaker power
RA13
RA14
RA15
RA16
CPVEE
2
2.2U_0603_6.3V6K
2
2.2U_0603_6.3V6K
0.1U_0402_25V6
EMI@
CA53
Layout Note:
AUD_SPK_R+
AUD_SPK_RAUD_SPK_L+
AUD_SPK_L-
V3D3_STB
27
1
CA23
1
CA24
2
ALC3204-CG_MQFN40_5X5
@ESD@
1
2
VD33STB
LDO1-CAP
LDO2-CAP
LDO3-CAP
Layout Note: Place close to Pin 12
CA7
.1U_0402_16V7K
16
L
L
DC_DET
GPIO0/DMIC-DATA12
GPIO1/DMIC-CLK
PDB
1
@
moat
AUD_VREF
CBN
CBP
1
18
SPKR
26
BEEP
2
1
AUD_PC_BEEP_C
1
RA23
2
1K_0402_5%
1
CA31
2
0.1U_0402_16V7K
AUD_PC_BEEP
3
1
2
1
JACK_PLUG
HDA_CODEC_SDIN0
+MIC2-VREFO
23
22
28
30
Close pin29
BAT54CW_SOT323-3
RA24
10K_0402_5%
A
2
RA3
AVDD2
AVDD1
34
8
1
39
PVDD2
PVDD1
DVDD-IO
DVDD
2
1
2
+3V_DVDD
EC_MUTE#
26
@EMI@
CA38
33P_0402_50V8J
1
1
2
33_0402_5%
2
0_0402_5%
2
@
100K_0402_5%
2
100K_0402_5%
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
@
MIC2-VREFO
VREF
CBN
CBP
2
CA50 RF@
1
RA9
SYNC
BIT-CLK
SDATA-OUT
SDATA-IN
RF@
1
RA7
9
5
4
7
2
CA46
PCH_AZ_CODEC_SYNC
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_SDOUT
PCH_AZ_CODEC_SDIN0
24
2
1
10P_0201_50V8J
@EMI@
RA43
33_0402_5%
18
18
18
18
RA43,CA38: close to UA1.6
+3V_DVDD
+LINE1_VREFO_L
LINE1-VREFO-L
PCH_AZ_CODEC_BITCLK
2
CA49 RF@
C
2
1
68P_0201_50V8J
UA1
2
RF@
CA16
.1U_0402_16V7K
2
CA45
2
2
1
+1.8V_CPVDD
10P_0201_50V8J
2
+1.8V_CPVDD
1
CA48 RF@
CA15
10U_0603_6.3V6M
1
1
68P_0201_50V8J
+1.8V_AVDD
1
1
RF@
Close pin8
1
CA44
+5V_PVDD +5V_AVDD
+5V_AVDD
10P_0201_50V8J
2
+3V_DVDD
CA47 RF@
CA6
68P_0201_50V8J
1
RF@
1
CA5
CA43
2
change to shortpad 11/23
+3V_DVDD
10P_0201_50V8J
2
0_0402_5%
68P_0201_50V8J
RA2
+5V_PVDD
.1U_0402_16V7K
@
10U_0603_6.3V6M
1
1
CLOSE TO UA1
+3V_DVDD
10U_0603_6.3V6M
CA13
+3VS 25mA
D
.1U_0402_16V7K
2
1
RA42
DMIC_DATA_EDP
change to shortpad 11/23
CA11
10U_0603_10V6M
1
29
1 CA4
.1U_0402_16V7K
2
CA3
2
2
D
1 CA2
10U_0603_10V6M
CA1
1
change to shortpad 11/23
CA10
.1U_0402_16V7K
1
0_0805_5%
10U_0603_6.3V6M
@
RA5
2
.1U_0402_16V7K
@
+1.8V_AVDD
LN2306LT1G_SOT23-3
MAIN@
D
+5V_PVDD
2A
1
RA1
10U_0603_10V6M
+5VS
RA4
2
moat
+1.8V_PRIM QA1
+5VS
S
+5V_AVDD
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Audio Codec ALC3204
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
24
of
78
5
4
Main Func = Audio Jack
3
2
1
ESD@
Universal Jack
(Global Headset Jack + mic phone in + line in support)
w
e
i
v
D
2
1
+LINE1_VREFO_L
24
3
AUD_HP1_JACK_R
24 LINE1_R
BAT54ATB_SOT-523-3
MAIN@
24
1
2 2.2K_0402_5%
RA26
1
2 2.2K_0402_5%
1
CA32
2 LINE1-L_C
10U_0603_10V6M
RA28 1
RA29 1
2 1K_0402_5%
2 4.7K_0402_5%
1
CA33
2 LINE1-L_R
10U_0603_10V6M
RA32 1
RA33 1
2 1K_0402_5%
2 4.7K_0402_5%
RA27 1
2 10_0402_1%
RA31 1
2 10_0402_1%
LA1
AUD_HP1_JACK_L1 LA2
1
1
ESD_M@2 BLM15PX330SN1D_2P RING2_R
ESD_M@2 BLM15PX330SN1D_2P HPOUT_L
AUD_HP1_JACK_R1 LA3
LA4
1
1
ESD_M@2 BLM15PX330SN1D_2P HPOUT_R
ESD_M@2 BLM15PX330SN1D_2P SLEEVE_R
SLEEVE
e
r
Layout Note:
Close to UA1
C
E
D
2
2
3
2
3
#3 M/G
#1 L
B
#5
#6 AGND
#2 R
#4 G/M
GND
SINGA_2SJ3095-136111F~D
CONN@
1
2
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
A
1
2
1
CA37 @ESD@
680P_0402_50V8J
2
CA36 @ESD@
680P_0402_50V8J
2
DA5
2
1
AZ5123-02S.R7G_SOT23-3
ESD_M@
2
1
CA41 ESD@
680P_0402_50V8J
@
1
CA42 ESD@
680P_0402_50V8J
change to shortpad 11/23
@
1
CA35 EMI@
100P_0402_50V8J
@
0_0402_5%
RA40
CA34 EMI@
100P_0402_50V8J
3
2
4
7
RA30
10K_0402_5%
1
6
HPOUT_R
RING2_R
JACK_PLUG_DET
10 mils
DA7
L03ESDL5V0CC3-2_SOT23-3
ESD_M@
DA4
L03ESDL5V0CC3-2_SOT23-3
ESD_M@
5
JACK_PLUG_DET
RA34
10K_0402_5%
r
o
F
JACK_PLUG
JACK_PLUG_DET
5
1
HPOUT_R
HPOUT_L
JACK_PLUG
2
CLOSE TO JHP1
JACK_PLUG
JHP1
3
1
1
24
C
Universal Jack
(Global Headset Jack + mic phone in + line in support)
SLEEVE_R
HPOUT_L
2
B
A
L
L
EMI@, @ESD@, ESD@
1
Main Func = Audio Jack
2
24
DA8
24 RING2
AUD_HP1_JACK_L
24 LINE1_L
RA25
1
+MIC2-VREFO
D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Audio Jack
Size
3
2
Rev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
25
of
78
5
4
23
24
22
GC6_THM_DIS#
85
20
25
CMP_VOUT0
CMP_VIN0 RE37 1
VCREF0
83
21
26
PROCHOT
WLAN_PWR_EN
118
117
116
109
110
111
113
114
115
CMP_STRAP0
ICSP_CLK
ICSP_CLR
2 0_0201_5%
ICSP_DAT
@
61,62
1
RE70
HW_ACAV_IN
MODEL_ID
I_ADP
BOARD_ID
LCD_VCC_TEST_EN
I_BATT
CMP_VOUT0
2 0_0402_5%
EC_MUTE#
24
2
+RTC_CELL
100K_0402_5%
18,59,60,61
60
56,62
WLAN_PWR_EN
LCD_TST 29
VCIN0_PH
31
1
1
2
2
2
2
1
@
1
@
2
10K_0402_5%
2
10K_0402_5%
2
1K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
RE19
BKLT_IN_EC
1
RE157
USB_POWERSHARE_VBUS_EN 1
RE168
1
RE43
1
RE161
2
1K_0402_5%
2
100_0402_5%
C
POWER_SW#_MB
2
DOCK@
PWR_TB_DOCK#
10K_0402_5%
27
40
+3V_PCH_PRIM
+3VLP
GPU_THM_SMBDAT1
RE10
GPU_THM_SMBCLK 1
RE11
2
2.2K_0402_5%
2
2.2K_0402_5%
+3VALW_EC
RE49
100K_0402_5%
33
CMP_VIN0
1
RE52
@
CMP_VOUT0
2
100K_0402_5%
PANEL_BKEN_EC 29
SIO_EXT_WAKE# 20
LCD_VCC_TEST_EN
@
1
FAN1_TACH
29
CE28
2
B
220P_0402_50V8J
+3VALW_EC
RE51 300_0402_5%
1
2
1
CE25
EC_AGND
1
1
HW_ACAVIN_NB_EC
I_ADP_R
61
2
CE34
RE167
10K_0402_1%
@
1
IMVP_VR_ON
CE31
2
2
RE46
10K_0402_1% @
EC_AGND
I_ADP
+3VLP
HW_ACAV_IN
2
CE32
1
EC_AGND 2
+3VALW_EC
1
100P_0402_50V8J
2
1000P_0402_50V7K
1
100P_0402_50V8J
Close to UE1 each pin
RE48
10K_0402_1%
2200P_0402_25V7K
SMBus address 0x40
2
+3VALW
RE54 300_0402_5%
1
2
I_BATT
1
EC_AGND
I_BATT_R
RE164
100K_0402_5%
61
1
2200P_0402_25V7K
2
GEN9@ RC442
1
2
VCCDSW_ON
PCH_PRIM_EN
21,37,65,66
0_0402_5%
EC_AGND
A
DC2
59,62,66
1
POK
2
RB751S40T1G_SOD523-2
HOST_DEBUG_TX
Pin8 5085_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug
1
RE29
+3VALW_EC
GC6_THM_DIS# 17
HW_ACAVIN_NB_EC
@
2
1
EC_MUTE#
2 0_0402_5%
ALWON
1
VR_CAP
1
VCI_IN1
POWER_SW_IN#
@
1
1
NB_MUTE#
RE28
SYSPWR_PRES
POWER_SW_IN#
PTP_DIS# 31
PECI_EC 10,16
1
RE68
RE16
ME_FWP
+3VS
2
100K_0402_5%
2
119
120
121
126
127
128
1
ICSP_CLK
ICSP_DAT
ICSP_CLR
e
r
2
101
102
87
33
2 43_0402_1% PECI_EC
1
IMVP_VR_ON
1
VREF_CPU
RE23
SYS_PWROK
+RTC_CELL
1
95
TP74
@
1
RE156
2
PTP_DIS#
H_PECI
VREF_CPU
30
30
ME_FWP 18
HOST_DEBUG_TX
FPR_SCAN#
0_0402_5%
RE162
2
90
94
CE30
2 0_0201_5%
2 0_0201_5%
1
43
82
103
5
19
65
VTR
VTR
VTR
VTR
VTR
VTR
122
124
8
7
6
5
2
JXT_FP241AH-010GAAM
SP010021O00
Close UE1
GEN9_M@
RE62
10K_0201_5%
GND
GND
ME_FWP
HOST_DEBUG_TX
BAT2_LED#
BAT1_LED#
1U_0603_16V7
RE58
10K_0201_5%
11
12
80
81
FAN1_PWM 31
FAN2_PWM 31
LANWAKE# 18
PS_ID 59
PCIE_WAKE# 18,33,34,35,41
PCIE_WAKE#
+3VALW
RPE7
10K_0804_8P4R_5%
RE63 1
BAT2_LED#
BAT1_LED#
AUX_EN_WOWL
31
VCREF0
Need to change 0201
RE60 1
RE61 1
1
106
70
ESR <100m ohms
RE57
10K_0201_5%
17,23,33,34,35,41,48
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
MSCLK
MSDATA
FAN1_PWM
FAN2_PWM
+1.05VALW
2
CE4
12P_0402_50V8J
RE55
10K_0201_5%
JXT_FP241AH-010GAAM
SP010021O00
PLTRST#
CONN@
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10
1
CE24
EC_AGND
RE59
49.9_0402_1%
JDEG1
2
0_0603_5%
RE56
100K_0201_5%
GND
GND
CONN@
1
1 2
2 3
ESPI_IO0_R
3 4
ESPI_IO1_R
4 5
ESPI_IO2_R
5 6
ESPI_IO3_R
6 7
ESPI_CS#
7 8
2
1
@
8 9
RE65
0_0402_5%
9 10
ESPI_CLK_R
10
+3VALW
47
34
35
36
4
TBTA_HRESET 40
TBT_RESET_N_EC# 40,41
2
+3VALW_EC
32.768KHZ_9PF_X1A000141000200
20ppm / 9pF
1
ESR <50kohm (MAX)
CE3
10P_0402_50V8J
2
2
1
1
Debug Connector
PROCHOT
1
2
2
KB_LED_PWM
BEEP 24
EC_AGND
5
1
CE26
47P_0402_50V8J
INA
GND
VR_CAP
Close UE1
YE1 MAIN@
MEC_XTAL1 1
2 MEC_XTAL2
RE53
100K_0201_5%
NL17SZ06DFT2G_SC70-5 NC
MAIN@
1
3
H_PROCHOT#
1
RE50
UE2
44
45
31
31
GPU_THM_SMBCLK
GPU_THM_SMBDAT
CE23
0.1U_0402_25V6
32 KHz Clock
r
o
F
VCC
4 OUT Y
FAN1_TACH
FAN2_TACH
TP44
1
CE22
0.1U_0402_10V7K
FAN1_TACH
FAN2_TACH
MEC1416-NU-D0_VTQFP128_14X14
2
1
2
JESPI1
XTAL2
XTAL1
@
+3VS
RE67,CE35: close to UE1.57
A
E
D
nRESET_IN/GPIO014
GPIO057/VCC_PWRGD
GPIO107/nRESET_OUT
125
123
GPIO024/ADC7
GPIO023/ADC6/A20M
GPIO022/ADC5
GPIO153/ADC4
GPIO154/ADC3
GPIO155/ADC2
GPIO122/ADC1
GPIO121/ADC0
ADC_VREF
18
MEC_XTAL2
MEC_XTAL1_R
1
1 0_0402_5%
1 0_0402_5%
2
@
AVSS
RE45 2
MEC_XTAL1 RE47 2
13
48
73
1
RUNPWROK
RESET_OUT#
Modify 5/2
PBAT_CHG_SMBDAT
PBAT_CHG_SMBDAT 59,61
PBAT_CHG_SMBCLK
PBAT_CHG_SMBCLK 59,61
GPU_THM_SMBDAT
GPU_THM_SMBCLK
GPU_THM_SMBDAT 18,31,48
GPU_THM_SMBCLK 18,31,48
TYPEC_SMBDA
TYPEC_SMBDA 40
TYPEC_SMBCLK
TYPEC_SMBCLK 40
1
2 0_0402_5%
RE89
@
TBT_RESET_N_EC#
2
1
2
1
2
1
2
1
2
VBAT
2 0_0402_5%
2 0_0402_5%
2
SUSCLK_EC
@
@
RE42
RE158
1
18
1
1
IMVP_VR_ON
GPIO120/CMP_VOUT1
GPIO021/CMP_VIN1
GPIO166/CMP_VREF1/UART_CLK
1
2
3
4
2
1
2
1
27 USB_EN#
ALL_SYS_PWRGD
18 IMVP_VR_ON
GPIO124/CMP_VOUT0
GPIO020/CMP_VIN0
GPIO165/CMP_VREF0
GPIO101/SPI_CLK
GPIO103/SPI_IO0
GPIO105/SPI_IO1
GPIO052/SPI_IO2
GPIO062/SPI_IO3
GPIO001/SPI_CS#/32KHZ_OUT
CE15
1
2
CE21
0.1U_0402_25V6
@EMI@
@EMI@
CE35
RE67
33P_0402_50V8J
33_0402_5%
18
TP_WAKE_KBC#
TP_WAKE_KBC#
35 AUX_ON
GPIO160/DAC_0
GPIO161/DAC_1
DAC_VREF
GPIO126/SHD_SCLK
GPIO133/SHD_IO0
GPIO134/SHD_IO1
GPIO135/SHD_IO2
GPIO136/SHD_IO3
GPIO123/SHD_CS#[BSS_STRAP]
67
69
71
42
33
3
USB_POWERSHARE_VBUS_EN
1 0_0402_5%
@
17,31
B
PCH_RSMRST#
BGPO/GPIO004
SYSPWR_PRES/GPIO003
VCI_OUT/GPIO036
VCI_IN1#/GPIO162
VCI_IN0#/GPIO163
VCI_OVRD_IN/GPIO164
1
RE165
1
RE14
1
RE30
TYPEC_SMBCLK
1
DE1
AZ5125-01H.R7G_SOD523-2
RE31
UPD1_ALERT
2
@
RE155
USB_EN#
1
RE17
1
KSO9
RE15
CMP_VIN0
1
RE166
USB_POWERSHARE_VBUS_EN 1
RE169
TP_WAKE_KBC#
TYPEC_SMBDA
L
L
VREF_CPU
GPIO145(ICSP_CLOCK)
GPIO146(ICSP_DATA)
ICSP_MCLR
2
RE85 2
FPR_SCAN#
RTCRST_ON
PCH_RSMRST#
BKLT_IN_EC
61 AC_DIS
GPIO035/SB-TSI_CLK
GPIO033/PECI_DAT/SB_TSI_DAT
2
4.7K_0402_5%
2
4.7K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
1
10K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
RE9
CMP_STRAP0
PECI_EC
RE32
100K_0402_5%
18,23
18,38
16
2
GPIO116/TFDP_DATA/UART_RX
GPIO117/TFDP_CLK/UART_TX
GPIO040/LAD0/ESPI_IO0
GPIO041/LAD1/ESPI_IO1
GPIO042/LAD2/ESPI_IO2
GPIO043/LAD3/ESPI_IO3
GPIO044/LFRAME#/ESPI_CS#
GPIO064/LRESET#
GPIO034/PCI_CLK/ESPI_CLK
GPIO067/CLKRUN#
GPIO063/SER_IRQ/ESPI_ALERT#
GPIO011/nSMI/nEMI_INT
GPIO060/KBRST
GPIO061/LPCPD#/ESPI_RESET#
GPIO100/nEC_SCI
32
28
29
30
31
27
PBAT_PRES#
GPIO157/LED0/TST_CLK_OUT
GPIO156/LED1
GPIO104/LED2
GPIO114/PS2_CLK0
GPIO115/PS2_DAT0
GPIO026/PS2_CLK1B
GPIO127/PS2_DAT1B
w
e
i
v
EC_AGND
RE8
PBAT_CHG_SMBCLK 1
CE20
0.1U_0402_25V6
CE19
0.047U_0402_16V4Z
PBAT_PRES#
GPIO143/KSI0/DTR#
GPIO144/KSI1/DCD#
GPIO005/SMB00_DATA/SMB00_DATA18/KSI2
GPIO006/SMB00_CLK/SMB00_CLK18/KSI3
GPIO147/KSI4/DSR#
GPIO150/KSI5/RI#
GPIO151/KSI6/RTS#
GPIO152/KSI7/CTS#
59
60
61
62
58
56
57
63
55
10
49
53
66
LID_CL_SIO#
GPIO053/PWM0
GPIO054/PWM1
GPIO056/PWM3
GPIO030/BCM_INT0#/PWM4
GPIO031/BCM_DAT0/PWM5
GPIO032/BCM_CLK0/PWM6
GPIO002/PWM7
40
41
RE6
100K_0402_1%
PBAT_CHG_SMBDAT 1
EC Chip CPN
0_0603_5%
8
9
11
12
89
91
96
97
Rb
2
+3VALW_EC
EC@
2
54
1
D
0.1U_0402_25V6
MEC1416
EC_AGND 112
ESPI_CLK_R
VTR_33_18
GPIO050/TACH0
GPIO051/TACH1
1
19
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CS#
UE1
+1.8VALW_EC
@
RE4
100K_0402_1%
Rb
2
EC_AGND
SA0000A8L00
GPIO007/SMB01_DATA/SMB01_DATA18
GPIO010/SMB01_CLK/SMB01_CLK18
GPIO012/SMB02_DATA/SMB02_DATA18
GPIO013/SMB02_CLK/SMB02_CLK18
GPIO130/SMB03_DATA/SMB03_DATA18
GPIO131/SMB03_CLK/SMB03_CLK18
GPIO141/SMB04_DATA/SMB04_DATA18
GPIO142/SMB04_CLK/SMB04_CLK18
2
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CS#
UPD1_ALERT
18 SYS_PWROK
PRIM_PWRGD
1
28
SD000002780
1
RE66
VSS
VSS
VSS
VSS
VSS
19
19
19
19
19
GPIO027/KSO00/PVT_IO1
GPIO015/KSO01/PVT_CS#
GPIO016/KSO02/PVT_SCLK
GPIO017/KSO03/PVT_IO0
GPIO045/BCM_INT1#/KSO04
GPIO046/BCM_DAT1/KSO05
GPIO047/BCM_CLK1/KSO06
GPIO025/KSO07/PVT_IO2
GPIO055/PWM2/KSO08/PVT_IO3
GPIO102/KSO09[CR_STRAP]
GPIO106/KSO10
GPIO110/KSO11
GPIO111/KSO12
GPIO112/PS2_CLK1A/KSO13
GPIO113/PS2_DAT1A/KSO14
GPIO125/KSO15
GPIO132/KSO16
GPIO140/KSO17
78
79
52
88
2
1
98
99
6
7
104
105
107
108
40
CE16
100P_0402_50V8J
11
12
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
CAP_LED#
19 ESPI_ALERT#
48 GPU_PWR_LEVEL
31 TP_EN#
19 ESPI_RESET#
LID_CL_SIO#
27,29
ESPI_CLK_R
10,59,61,67
2
14
15
16
37
38
39
50
46
68
72
74
75
76
77
86
92
93
MASK_SATA_LED#
LID_CL_SIO#
59,61
82.5K_0402_1%
SD034649280
1
RE1
100K_0402_1%
@
Ra
BOARD_ID
CE33
2.2U_0402_6.3V6M
RE25
100K_0402_5%
2
PRIM_PWRGD
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
31 CLK_TP_SIO
31 DAT_TP_SIO
18 SIO_PWRBTN#
1 0_0402_5%
30
64.9K_0402_1%
SD034499280
10K
17.8K
27K
49.9K
MEC1416-NU-D0_VTQFP128_14X14
UE1
KSI[0..7]
6/3
@
49.9K_0402_1%
2
KSO[0..16]
Del RE91 and del PWR_SELECT trace
RE90 2
For
Board ID Select
+1.8V_PRIM
+RTC_CELL_VBAT
0_0603_5% 1
VSS_VBAT
31
SIO_SLP_S0#
RE3
N17E_G1@TBT@
RE3
100K_0402_1%
@
Ra
MODEL_ID
RE41
100K_0402_5%
18,23
SD034374280
RE3
N17P_G1@TBT@
CE17
0.1U_0402_25V6
+3VALW
1
31
2 0_0201_5%
@
2
CE14
0.1U_0402_10V7K
PRIM_PWRGD
2 0_0201_5%
@
PRIM_PWRGD_R RE160 1
VCCDSW_ON RE163 2 GEN9@ 1 0_0402_5%
2
2
@
84
51
17
64
100
RE149 1
1V05PRIM_PG
PRIM_PWRGD_R
SD034270280
RE3
N17P_G0@TBT@
+3VALW_EC
Board ID
CE2
0.1U_0402_10V7K
65,66
BAT1_LED#
2
1
RE18
100K_0402_5%
BAT2_LED#
2
1
RE21
100K_0402_5%
PRIM_PWRGD_R
2
1
@
RE150 100K_0402_5%
@
1
RE7
1
CE39 RF@
CE38 RF@
2
10P_0201_50V8J
2
1
31
65
C
1
CE37 RF@
RPE6 100K_8P4R_5%
8
KSO8
7
KSO15
6
KSO14
5
KSO16
68P_0201_50V8J
1
2
3
4
CE36 RF@
RPE5 100K_8P4R_5%
8
KSO10
7
KSO11
6
KSO12
5
KSO13
10P_0201_50V8J
68P_0201_50V8J
1
2
3
4
2
SD034178280
EVT
DVT1
DVT2
Pilot
+3VALW_EC
RPE4 100K_8P4R_5%
1
8
KSO4
2
7
KSO5
3
6
KSO6
4
5
KSO7
37.4K_0402_1%
+1.8VALW_EC
+RTC_CELL
1
27K_0402_1%
Model ID
CE1
0.1U_0402_10V7K
CE13
0.1U_0402_25V6
CE12
0.1U_0402_25V6
1
CE11
0.1U_0402_25V6
1
CE10
0.1U_0402_25V6
+3VALW_EC
2
2
CE9
0.1U_0402_25V6
RPE3 100K_8P4R_5%
8
KSO0
7
KSO1
6
KSO2
5
KSO3
2
2
@ CE8
1000P_0402_50V7K
1
2
3
4
@
1
@ CE7
1000P_0402_50V7K
RPE2 10K_8P4R_5%
4
KSI7
3
KSI6
2
KSI5
1
KSI4
1
1 RB551V-30_SOD323-2
DT20 2
CE6
0.1U_0402_10V7K
5
6
7
8
2
0_0603_5%
RE2
CE5
10U_0603_6.3V6M
RPE1 10K_8P4R_5%
4
KSI0
3
KSI1
2
KSI2
1
KSI3
1
1
+3VALW
5
6
7
8
2
+3VALW
D
1 RB551V-30_SOD323-2+3VALW_EC
@
1
@
17.8K
27K
37.4K
49.9K
64.9K
82.5K 17.8K_0402_1%
2
DT21 2
N17P_G0 w/o TBT
N17P_G1 w/o TBT
N17E_G1 w/o TBT
N17P_G0 w/ TBT
N17P_G1 w/ TBT
N17E_G1 w/ TBT
+3VALW_EC
10K_0402_1%
17.8K_0402_1%
27K_0402_1%
37.4K_0402_1%
49.9K_0402_1%
64.9K_0402_1%
82.5K_0402_1%
107K_0402_1%
154K_0402_1%
200K_0402_1%
EC@
1
+3.3V_VBUS_IN
1 RB551V-30_SOD323-2
SD034100280
SD034178280
SD034270280
SD034374280
SD034499280
SD034649280
49.9K_0402_1%SD000002780
SD034499280 SD034107380
SD034154380
SD034200380
RE1
2
DT19 2
1
RE3
N17E_G1@NON_TBT@
1
+3.3V_ADP_DCIN
2
RE3
N17P_G1@NON_TBT@
RE3
N17P_G0@NON_TBT@
1
3
RE3 For
SKU ID Select
2
4
2
5
Main Func = EC
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
EC MEC1416
Size
2
Rev
0.3
LA-F611P
Date:
3
Document Number
Thursday, March 22, 2018
1
Sheet
26
of
78
5
4
3
2
1
Main Func = USB3.0 Port1
USB3.0 Port1
USB30_VCCA
Maximum Output
Current 2A
USB30_VCCA
1
USB20_N1_R
USB20_P1
3
4
USB20_P1_R
USB_EN#
CU5
1U_0402_10V6K
4
1
EN
3
OCB
USB_OC0#
2
w
e
i
v
JUSB1
USB20_N1_R
USB20_P1_R
19
USB3_PTX_L_DRX_N1
USB3_PTX_L_DRX_P1
2
1
1
80 mils
USB3_PRX_DTX_N1
3
4
USB3_PRX_L_DTX_N1
HCM1012GH900BP_4P
C
1
2
HCM1012GH900BP_4P
1
2
1
2
1
2
Main Func = USB2.0 Port2 + Card Reader+Power BTN on IO/B
+5VALW
CU17
1
1
2USB3_PTX_C_DRX_N3 3
.1U_0402_16V7K
1
USB3_PTX_L_DRX_P3
4
USB3_PTX_L_DRX_N3
HCM1012GH900BP_4P
A
5
8
USB3_PRX_L_DTX_P3
7
7
USB3_PTX_L_DRX_N3
USB3_PTX_L_DRX_P3
5 5
6
6
USB3_PTX_L_DRX_P3
4
USB3_PTX_L_DRX_N1
5 5
6
6
USB3_PTX_L_DRX_P1
USB20_N6_R
USB20_P2
19
USB20_N2
2
3
1
USB20_P2_R
4
USB20_N2_R
LU6 EMI@
USB3_PRX_DTX_N3
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
USB20_P6_R
USB20_N6_R
USB20_P2_R
USB20_N2_R
+3VALW
+RTC_VCC
+3VS
USB20_VCCB
POWER_SW#_MB
LID_CLOSE#
19
20
MCM1012B900F06BP_4P
EMI_M@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND1
GND2
TWVM_FPC1020-18RC-TA0HC
B
USB30_VCCA
USB3.0 Port2
JUSB2
1
2
3
4
5
6
7
8
9
USB20_N3_R
USB20_P3_R
USB3_PRX_L_DTX_N3
USB3_PRX_L_DTX_P3
USB3_PTX_L_DRX_N3
USB3_PTX_L_DRX_P3
USB30_VCCA
1
USB3_PRX_L_DTX_P3
4
USB3_PRX_L_DTX_N3
HCM1012GH900BP_4P
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
GND
GND
GND
GND
10
11
12
13
LOTES_AUSB0172-P001A
CONN@
ESD_M@
AZC199-02SPR7G_SOT23-3
DU4
1
2
Issued Date
Layout Note: Close JUSB2
80 mils
1
2
1
2
1
2
1
2
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
USB3.0 & I/O
Size
2
Document Number
Rev
0.3
LA-F611P
Date:
3
C
JIOB1
TPS10
L05ESDL5V0NA-4_SLP2510P8-10-9
ESD_M@
USB3_PRX_DTX_P3
L05ESDL5V0NA-4_SLP2510P8-10-9
ESD_M@
80 mils
LU9
19
8
19
8
CardReader
USB2.0 Port3
3 3
19
3 3
100U_1206_6.3V6M
CU15
CU4
LU5 EMI@
USB20_N6
USB20_P6_R
4
22U_0805_10V6M
CU14
2USB3_PTX_C_DRX_P3 2
.1U_0402_16V7K
CU3
9
4 4
USB3_PRX_L_DTX_P1
7
e
r
1
22U_0805_10V6M
CU13
1
3
1U_0402_10V6K
CU12
USB3_PTX_DRX_N3
EMI_M@
19
USB20_P6
1U_0402_10V6K
CU11
USB3_PTX_DRX_P3
19
2 2
USB3_PTX_L_DRX_N3
r
o
F
LU4
19
USB20_N3_R
USB3_PRX_L_DTX_N3
8
7
2
1
9
9
4 4
2
2
10
9
2 2
USB3_PTX_L_DRX_N1
1
USB20_N3
2
10
USB3_PRX_L_DTX_P1
1
19
DU3
1 1
USB3_PRX_L_DTX_P3
USB20_P3_R
19
E
D
USB3_PRX_L_DTX_N3
MCM1012B900F06BP_4P
4
68P_0201_50V8J
Main Func = USB3.0 Port2
B
2
1
RF@
@ESD@
2 .1U_0402_16V7K
CU22
1
10P_0201_50V8J
CC300
2
1
RF@
@
LID_CLOSE#
3
1
1 1
USB3_PRX_L_DTX_N1
USB3_PTX_L_DRX_P1
MCM1012B900F06BP_4P
EMI_M@
USB20_VCCB
For EMI Reserved
USB20_P3
USB_OC1#
SY6288D20AAC_SOT23-5
MAIN@
DC1
L03ESDL5V0CC3-2_SOT23-3
@ESD@
2
L
L
3
OCB
@
19
LU8
19
2
GND
EN
CU21
2
USB_EN#
1
OUT
IN
4
22U_0805_10V6M
1
2
SW1
TST71-N-220-T170-S017_2P
1000P_0402_50V7K
CC299
1 @ESD@
26
LID_CLOSE#
2 100_0402_5%
5
2
26,29 LID_CL_SIO#
26 POWER_SW#_MB
1
3
R22
1
1U_0402_10V6K
2
10
11
12
13
USB2.0/Card Reader connector
USB20_VCCB
UU3
2
CU16
1
GND
GND
GND
GND
DU1
3
19
USB3_PRX_DTX_P1
USB3_PRX_L_DTX_P1
D
USB3_PRX_L_DTX_N1
3
USB3_PTX_L_DRX_N1
19
1
100U_1206_6.3V6M
CU10
CU2
4
LU3 EMI@
2
22U_0805_10V6M
CU9
USB3_PTX_C_DRX_N1 3
2
.1U_0402_16V7K
USB3_PTX_L_DRX_P1
22U_0805_10V6M
CU8
USB3_PTX_DRX_N1
1
CU1
1
1U_0402_10V6K
CU7
19
USB3_PTX_DRX_P1
LU2 EMI@
1U_0402_10V6K
CU6
19
USB3_PTX_C_DRX_P1 2
2
.1U_0402_16V7K
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
LOTES_AUSB0172-P001A
CONN@
ESD_M@
AZC199-02SPR7G_SOT23-3
DU2
Layout Note: Close JUSB1
USB30_VCCA
1
1
2
3
4
5
6
7
8
9
USB3_PRX_L_DTX_N1
USB3_PRX_L_DTX_P1
SY6288D20AAC_SOT23-5
MAIN@
2
MCM1012B900F06BP_4P
GND
2
3
USB20_P1
2
2
2
USB20_N1
19
USB20_N1
1
OUT
IN
3
19
EMI_M@
1
CU20 RF@
5
LU1
CU19 RF@
UU1
D
1
68P_0201_50V8J
10P_0201_50V8J
USB30_VCCA
+5VALW
Thursday, March 22, 2018
Sheet
1
27
of
78
5
4
3
2
1
Main Func = Finger Printer
+3VS
D
1
C37
2
0.1U_0402_16V7K
2
26
8
7
6
5
4
3
2
1
FPR_SCAN#
1
2
8
7
6
5
4
3
2
1
G2
G1
10
9
ACES_51522-00801-001
CONN@
0_0201_5%
RF1
2
1
@
1
3
DF1
AZC199-02SPR7G_SOT23-3
w
e
i
v
JFP
FP_VCC
USB20_N9
USB20_P9
3
19
19
FP_VCC
1
C50
C46
2
RF@
RF@
2
10P_0201_50V8J
68P_0201_50V8J
1
C
L
L
B
A
5
r
o
F
4
e
r
E
D
D
C
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Finger Print
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
28
of
78
5
4
3
Main Func = LCD
2
+PWR_SRC
+LCDVDD_LCD
1
0_0805_5%
1
2
+3VS
1
@
2 0_0402_5%
DBC_PANEL_EN
20
change to shortpad 11/23
TC103TP@
2
+3VS_CAM
DMIC_DATA_EDP 24
DMIC_CLK_EDP 24
1
2
3
4
USB20_N5_R
USB20_P5_R
BKLT_CTRL
BLON_OUT_C
EDP_HPD
8
7
6
5
USB20_N8_R
USB20_P8_R
100K_8P4R_5%
TS_EN
RP2
BLON_OUT_C
LCD_BRIGHTNESS
LCD_TST_C
+TPAN_VDD
1
2
3
4
1
C6
C7
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_TXN0_C
EDP_TXP0_C
C8
C9
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_TXN1_C
EDP_TXP1_C
C10
C11
1
1
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
EDP_AUXN_C
EDP_AUXP_C
@
2
R9
0_0402_5%
D3
eDP_BKLT_CTRL
2
8
7
6
5
PANEL_BKEN_EC
BKLT_CTRL
LCD_TST
26
LCD_TST
3
LCD_TST
26
USB20_N5_R
EC (BIST MODE)
BAT54CW_SOT323-3
BKLT_CTRL = INV_PWM
4
@
2 0_0402_5%
OUT
eDP_BKLT_CTRL
16
2
EDP_VDD_EN
LCD_VCC_TEST_EN
High Active
R10
BAT54CW_SOT323-3 100K_0402_5%
2
EC (BIST MODE)
1
26
80 mils
5
IN
OUT
20
3.3V_TS_EN
4
EN
OC
1
USB20_P5
19
USB20_N5
19
C
2
RB551V-30_SOD323-2
R19
1
2
@
33_0402_5%
TS_EN
Touch Panel
1
2
TOUCH_SCREEN_PD#
17
C16
10P_0402_50V8J
B
USB20_P8_R
1 EMI@
2
R20
0_0402_5%
USB20_P8
19
USB20_N8
19
@EMI@
1
3
4
MCM1012B900F06BP_4P
USB20_N8_R
1 EMI@
R21
2
0_0402_5%
USB20_P8_R
USB20_N8_R
80 mils
2
3
1
R30
@
2
10K_0402_5%
+TPAN_VDD
1
2
DA6 @ESD@
AZC199-02SPR7G_SOT23-3
A
RF@
GND
1
LID_CL_SIO#
2
C48
A
4
D5
@
26,27
L4
+TPAN_VDD
2
0_0603_5%
U3
1
3
1
@
EMI_M@
2
MCM1012B900F06BP_4P
@
1
R13
2
D
+TPAN_VDD
68P_0201_50V8J
r
o
F
+5VS
1
Main Func = TS
E
D
B
C31
1U_0402_10V6K
2
1
@
R57
2
1
10K_0402_5%
3
L
L
LCDVDD_EN
1
3
OC
+3VS
2
SY6288C20AAC_SOT23-5
MAIN@
D4
change to shortpad 11/23
EN
40mil
1
3
1
R8
IN
3
L_BKLT_CTRL
U1
5
GND
Brightness
16
+LCDVDD
L3
2
C15
4.7U_0603_6.3V6K
1
EDP_AUXN
EDP_AUXP
+3VS
C17
1U_0402_6.3V6K
2
1
e
r
USB20_P5_R
1
C
6
6
w
e
i
v
RP1
1
2
IR_CAM_DETECT#
LCD_BRIGHTNESS
BLON_OUT_C
+3VS_CAM
DMIC_DATA_EDP
DMIC_CLK_EDP
1
2 0_0603_1%
@
change to shortpad 11/23
RF@
EDP_TXN1
EDP_TXP1
+3VS_CAM
1
RF@
R6
+3VS_CAM
R16
C47
DBC_PANEL_EN_R
68P_0201_50V8J
6
6
+3VS
+DCBAT_LCD
100_8P4R_5%
EDP_TXN0
EDP_TXP0
EE note: Never change R16 to short pad after MP
C49
R5
10K_0402_5%
EDP_TXN1_C
EDP_TXP1_C
ACES_51540-04001-P01
SP010029F00
6
6
C5
2
C14 @
33P_0402_50V8J
EDP_TXN0_C
EDP_TXP0_C
2
1 RF@
C12
C3
1
C4
68P_0201_50V8J
2
16
TC104TP@
1
10P_0402_50V8J
EDP_HPD
LCD_CBL_DET#
EDP_AUXP_C
EDP_AUXN_C
C2
2
1U_0402_10V6K
LCD_TST_C
DBC_PANEL_EN_R
EDP_HPD
1
1000P_0402_50V7K
EE note: Never change R3 to short pad after MP
0.1U_0603_50V7K
@
+LCDVDD_LCD
Trace width = 60mil
2
1.5A_24V_SMD1812P150TF-24
MAIN@
1
2
2
@
change to shortpad 11/23
0.1U_0402_16V7K
D
1
R3
+DCBAT_LCD
850mA
F1
2
G1
G2
+DCBAT_LCD
+LCDVDD
1
41
42
CONN@
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
8 9
9 10
10 11
11 12
12 13
13 14
14 15
15 16
16 17
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24 25
25 26
26 27
27 28
28 29
29 30
30 31
31 32
32 33
33 34
34 35
35 36
36 37
37 38
38 39
39 40
40
2
JEDP1
1
Main Func = CAM
INVERTER POWER
SY6288C20AAC_SOT23-5
@
5
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
LCD/Camera/Mic
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
Thursday, March 22, 2018
1
Sheet
29
of
78
5
4
3
2
1
w
e
i
v
D
D
Main Func = Battery LED
C
BJT
R1: 47 K
R2: 10 K
Low actived from KBC GPIO
+3VALW
e
r
+5VALW
Need to confirm with Reno, this pin is push pull
3
L
L
MASK_SATA_LED#
26
1
BAT1_LED#
2
1
5
D
AMBER_LED_BAT
2
R68
1
W
1
4
200_0402_5%
3
Y
LTW-295DSKS-5A_YEL-WHITE~D
AMBER_LED_BAT
R2
26
4
BAT2_LED#
BATT_WHITE_LED_R#
3
Q17B
DMN66D0LDW-7_SOT363-6
E
D
WHITE_LED_BAT
R83
100K_0402_5%
4
2
1
3
SATA_LED#_R
2
Q27B
DMN66D0LDW-7_SOT363-6
PCH_SATA_LED#
4
6
5
Q27A
DMN66D0LDW-7_SOT363-6
2
1
r
o
F
PCH_SATA_LED#
R82
100K_0402_5%
B
+3VS
+3VS
16,34
Q19
DDTA144VCA-7-F_SOT23-3
MAIN@
R1
B
2
1
S
Q22
LN2306LT1G_SOT23-3
MAIN@
5
Q18
DDTA144VCA-7-F_SOT23-3
MAIN@
LED1
1
2
200_0402_5%
3
BATT_WHITE_LED_R#
2
R69
1
1
2
R1
3
CHG_AMBER_LED_R#
6
Q17A
DMN66D0LDW-7_SOT363-6
G
SATA_LED#_R
A
WHITE_LED_BAT
R2
26
2
10K_0402_5%
2
1
RC224
C
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Power Button/LED
Size
2
Rev
0.3
LA-F611P
Date:
3
Document Number
Thursday, March 22, 2018
Sheet
1
30
of
78
4
3
+TP_VDD
KB Backlight Power Consumption: 285mA
2
1
2
1
1
2
KBBL@
C34
.1U_0402_16V7K
2
+TP_VDD Discharge
Q12
PCH/I2C
20
I2C1_SCL_TCH_PAD
I2C1_SCL_TCH_PAD
S
26
2
e
r
2
2
R46
2.2K_0402_5%
G
I2C_SCL_TP
1
D
3
NCT7718_DXN
T_CRIT#
DIMM
2
4
CPU
SCL
D+
SDA
DT_CRIT#
ALERT#
GND
8
THM_SML1_DATA
7
6
ALERT#
5
NCT7718W_MSOP8
MAIN@
Layout Note:
Layout Note:
VDD
+3VS
+3VS
1
2
2
Close to Thermal sensor
1
THM_SML1_CLK
@
+3VS
R29
1
5
2 18.7K_0402_1%
ALERT#
2 2K_0402_1%
T_CRIT#
S
D
RE82
10K_0402_5%
@
DE7
2
FAN1_TACH
1
2
5VS_FAN1
FAN1_TACH_D
FAN1_PWM_OUT
1
RB751S40T1G_SOD523-2
CE99
MAIN@
0.01U_0402_16V7K
JFAN2
3
@
RE101
10K_0402_5%
1
2
3
4
5
6
Q24
1
1
2
3
4
G1
G2
ACES_50224-00401-001
CONN@
FAN2_PWM_OUT
+3VS
+5VS
L2N7002LT1G_SOT23-3
MAIN@
Close to KBC
VD_IN1 for system thermal sensor
2 22U_0805_10V6M
change to shortpad 11/23
RE104
0_0603_1%
FAN2_PWM_OUT
FAN2_TACH_D
5VS_FAN2
1
RE153
100K_0402_5%
26
C148
2 22U_0805_10V6M
RE151
10K_0402_5%
@
RE105
0_0603_1%
DE9
2
FAN2_TACH
1
1
change to shortpad 11/23
5VS_FAN2
FAN2_TACH_D
FAN2_PWM_OUT
A
RB751S40T1G_SOD523-2
CE100 MAIN@
0.01U_0402_16V7K
2
26
1
VCIN0_PH
1
2
1
@
FAN2_PWM
R43
7.5K_0402_1%
RH1
100K_0402_1%_B25/50 4250K
R28
1
RE152
100K_0402_5%
1
R42
7.15K_0402_1%
B
+5VS
C30
+5VS
+3VALW_EC
2
S
D
4
DMN66D0LDW-7_SOT363-6
ACES_50224-00401-001
CONN@
2
Q11A
2
3
GPU_THM_SMBCLK
+3VLP
1
5
R49
2.2K_0402_5%
G
18,26,48
A
RE122
10K_0201_5%
1
2
3
4
G1
G2
FAN1_PWM_OUT
+3VS
+3VS
26
C
D
S
GPU_THM_SMBDAT
RE100
10K_0402_5%
L2N7002LT1G_SOT23-3
MAIN@
S
THM_SML1_DATA
6
1
DMN66D0LDW-7_SOT363-6
D
18,26,48
G
Q11B
1
26
Main Func = OTP
R48
2.2K_0402_5%
FAN1_PWM
@
Q23
3
G
r
o
F
C23 close U2
DXN and DXP routing width and spacing is 10 mil / 10 mil.
@
1
C23
2200P_0402_50V7K
10
9
G2
G1
1
2
3
4
5
6
FAN1_PWM_OUT
FAN1_TACH_D
5VS_FAN1
2
2
8
7
6
5
4
3
2
1
ACES_51524-0080N-001
CONN@
+5VS
2
1
1
@
C22
470P_0603_50V8J
2
1
2
INT_TP#
TP_LOCK#
DAT_TP_SIO
CLK_TP_SIO
RB551V-30_SOD323-2
MAIN@
2
B
E MAIN@
26
RE121
10K_0201_5%
2
2
3
LMBT3904LT1G_SOT23-3
1
1
C
THM_SML1_CLK
1
JTP
8
7
6
5
4
3
2
1
I2C_SDA_TP
I2C_SCL_TP
D6
PTP_DIS#
1
U2
R40
100K_0402_5%
D
NCT7718_DXP
Q14
R41
2
B
C19
2
1
C21
0.1U_0402_16V7K
1
JFAN1
+3VS
S
E
D
1
1
2
1
NTP_WAKE@
2
+3VS
4.7K_0402_5%
2
Main Func = Thermal
2
2
PWM FAN
2
0.1U_0402_16V7K
+TP_VDD
1
CAP_LED
PTP_DIS#
2
+TP_VDD
1
2
1K_0402_5%
2
R25
1
G
L
L
1
CAP_LED_Q
2
R1
Q6
LN2306LT1G_SOT23-3
MAIN@
2
26
2
D
S
Q7
DDTA144VCA-7-F_SOT23-3
MAIN@
D
S
3
2
2
2
I2C_SDA_TP
3
DMN66D0LDW-7_SOT363-6
1
1
R2
CAP_LED_R#
1
1
RF@
3
CAP_LED#
4
C51
68P_0201_50V8J
G
26
I2C1_SDA_TCH_PAD
+5VS
R24
100K_0402_5%
CAP LED Control
LOW actived from KBC GPIO
G
+5V_KB_BL
Q10A
1
1
C
2
5
+3VS
R47
2.2K_0402_5%
2
S
1
6
DMN66D0LDW-7_SOT363-6
1
Q10B
+TP_VDD
INT_TP#
3
Q9 LN2306LT1G_SOT23-3
MAIN@
+3VS
I2C1_SCL_TCH_PAD
1
TP_WAKE_KBC#
+TP_VDD
1
@ESD@
1
2 .1U_0402_16V7K
+TP_VDD
RF@
C150
S
C52
+5V_KB_BL
C149
D
Q13
2N7002K_SOT23-3
MAIN@
G
68P_0201_50V8J
For EMI Reserved
@ESD@
1
2 .1U_0402_16V7K
D
2
R39
10K_0402_5%
17,26
KB_BL_CTRL#
2
R37
100_0603_5%
1
KBBL@
31
32
CONN@
ACES_51698-03001-001
2
2
+TP_VDD
ESD depop locat i on
GND1
GND2
TP_WAKE_M@
R38
20K_0402_1%
Q8
DMN65D8LW-7_SOT323-3
G
1
TP_EN#
1
2
1
3
2
1
2
D
2
KB_LED_PWM
TP_WAKE@
C18
.1U_0402_16V7K
3
5
6
G1
G2
ACES_51575-00401-001
CONN@
@ESD@ C27
10P_0402_50V8J
26
w
e
i
v
CLK_TP_SIO
CLK_TP_SIO
I2C1_SDA_TCH_PAD
1
2
26
I2C1_SDA_TCH_PAD
20
1
1
KB_BL_CTRL#
KBBL@
R27
100K_0402_5%
1
2
3
4
1
1
EC/PS2
JKBBL
1
2
3
4
KB_LED_DET_C
2
KBBL@
R26
1
2
51K_0402_5%
KB_LED_BL_DET
3
G
20
DAT_TP_SIO
D
26
+TP_VDD
NTK3139PT1G_SOT723-3
DAT_TP_SIO
G
2
R35
0_0402_5%
S
D
1
0.5A_13.2V_MF-NSMF050-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
@ESD@ C26
10P_0402_50V8J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
CAP_LED
R34
2.2K_0402_5%
JKB
KB_DET#
R33
2.2K_0402_5%
+5V_KB_BL
1
R32
4.7K_0402_5%
KBBL_M@
R31
4.7K_0402_5%
F3
+TP_VDD
NTP_WAKE@
2
R36 1
0_0603_5%
@
+5VS
2
20
+3VS
max.
1
KSO[0..16]
+3VS
1
Keyboard Backlight (Reserved)
KSI[0..7]
26
1
+3VALW
2
26
2
Main Func = TPAD
1
5
Main Func = KB
2
@
C32
0.1U_0402_16V7K
VD_IN1_C
1
2
C33
100P_0402_50V8J
1
2 0_0402_5%
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
R45
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
KB/KBBL/TP/Thermal/FAN
Size
3
2
R ev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
1
Sheet
31
of
78
Main Func = HDD&FFS
GND
S1
1
A+
S2
2
A-
S3
3
GND
S4
4
B-
S5
5
B+
S6
6
GND
S7
7
DEVSLP
P3
5V
P7
10
+5V_HDD
5V
P8
11
1
5V
P9
12
GND
Device
Act i vi t y
P10
JHDD
SATA3_PRX_DTX_N0
SATA3_PRX_DTX_P0
19
2
2
0.01U_0201_16V7
0.01U_0201_16V7
SATA3_PTX_C_DRX_P0
SATA3_PTX_C_DRX_N0
CS3
CS4
1
1
2
2
0.01U_0201_16V7
0.01U_0201_16V7
SATA3_PRX_C_DTX_N0
SATA3_PRX_C_DTX_P0
1
HDD_DEVSLP
RS1
@
1
2
3
4
5
6
7
8
9
10
11
12
HDD_DEVSLP_R
FFS_INT2_Q
2
0_0402_5%
+5V_HDD
13
14
JP5
80 mils
1
2
1
2
CS32 RF@
FFS@
FFS@ RS3
100K_0402_5%
LNG2DM
3
4
1
2
VDD_IO
VDD
SDO/SA0
SDA/SDI/SDO
SCL/SPC
CS
RES
INT 1
INT 2
GND
GND
GND
5
12
11
US2_5VHDD 1
RS8
+5VS
FFS_INT1
FFS_INT2
FFS_INT1
FFS_INT2
17,20
17
80 mils
17
LNG2DMTR_LGA12_2X2
1
2
r
o
F
5
2
0_0603_5%
+5V_HDD
80 mils
US2
6
7
8
@
2
10
9
OUT
IN
1
6
@
e
r
+3VS
US2_5VHDD
2
L
L
4
HDD_EN_PCH
GND
EN
3
OCB
RS5
SY6288D20AAC_SOT23-5
MAD@
CS8
1U_0402_10V6K
MAD@
1 MAD@
2
10K_0402_5%
FFS_INT2
+5VS
RS4 FFS@
100K_0402_5%
FFS_INT2_Q
P11
QS1B FFS@
DMN66D0LDW-7_SOT363-6
5
QS1A FFS@
DMN66D0LDW-7_SOT363-6
2
1
14,15,18 PCH_SMBDATA
14,15,18 PCH_SMBCLK
2
CS30
10U_0805_10V6K
CS29 FFS@
0.1U_0402_25V6K
2
US1
2
1
CS7
68P_0201_50V8J
2
1
CS6
10U_0805_10V6K
CS5
0.1U_0402_25V6K
1
+3VS
w
e
i
v
+5V_HDD
80 mils
1000P_0402_50V7K
1
PJP@
2
2
JUMP_43X79
1
+5V_HDD
JP5
Always Short
GND
GND
ACES_51625-01201-001
CONN@
1
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
2
16
16
SATA3_PTX_DRX_P0
SATA3_PTX_DRX_N0
1
1
3
16
16
CS1
CS2
4
SOC TX
SOC RX
1
FFC
CONN
E
D
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
HDD/FFS
Size
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
32
of
78
5
4
3
2
1
Main Func = WLAN / CNVi
High Active
+3VALW
1
+3V_PCH_PRIM
2
4
1
2
1
2
1
2
EN
OC
+3VALW
1
2
3
2
RW12
1
10K_0402_5%
@
20
w
e
i
v
D
2
CNVi_EN#
G
@
75K_0402_1%
RW30
S
Q30
L2N7002WT1G_SC-70-3
@
2
2
OUT
SY6288C20AAC_SOT23-5
@
1
1
IN
GND
RF@
10P_0402_50V8J
CW9
2
1 0_0805_5%
.1U_0402_16V7K
CW8
1
@
2
0_0805_5%
2 @
.1U_0402_16V7K
CW7
2
1
10U_0603_6.3V6M
CW6
1
RW5
RW3
10U_0603_6.3V6M
CW5
2
.1U_0402_16V7K
CW4
@
.1U_0402_16V7K
CW3
1
D
5
75K_0402_1%
RW11
@
3
1.1A
+3.3V_WLAN
422.18mA
1
+3VS
+3.3V_WLAN
UW1
26
WLAN_PWR_EN
WLAN_PWR_EN
D
+1.8V_PRIM
20
UART_2_CRXD_DTXD
20
UART_2_CTXD_DRXD
0_0402_5%
2 @
1 RW27
CNV_BRI_PRX_R_DTX
UART_2_CTXD_DRXD
0_0402_5%
2 @
1 RW28
CNV_RGI_PTX_R_DRX
+3.3V_WLAN
JWLAN1
19
19
20
20
CNVi Rx
20
20
20
20
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P
PCIe X1
(link to PICe Port 14)
R3004
R3005
USB20_P7
USB20_N7
1 CNV@
1 CNV@
2 0_0201_5% CNV_PRX_R_DTX_N1
2 0_0201_5% CNV_PRX_R_DTX_P1
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
R3006
R3007
1 CNV@
1 CNV@
2 0_0201_5% CNV_PRX_R_DTX_N0
2 0_0201_5% CNV_PRX_R_DTX_P0
CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P
R3008
R3010
1 CNV@
1 CNV@
2 0_0201_5% CLK_CNV_PRX_R_DTX_N
2 0_0201_5% CLK_CNV_PRX_R_DTX_P
.1U_0402_16V7K
.1U_0402_16V7K
16
16
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15
16
16
PCIE_PRX_DTX_P15
PCIE_PRX_DTX_N15
17
17
CNVi Tx
CNV_PRX_DTX_N1
CNV_PRX_DTX_P1
CNV_PRX_DTX_N1
CNV_PRX_DTX_P1
CW2 1
CW1 1
PCIE_PTX_C_DRX_P15
PCIE_PTX_C_DRX_N15
2
2
PCIE_PRX_DTX_P15
PCIE_PRX_DTX_N15
CLK_PCIE_P15
CLK_PCIE_N15
CLK_PCIE_P15
CLK_PCIE_N15
17 CLKREQ_PCIE#15
18,26,34,35,41
PCIE_WAKE#
CNV_PTX_DRX_N1
20 CNV_PTX_DRX_N1
CNV_PTX_DRX_P1
20 CNV_PTX_DRX_P1
CNV_PTX_DRX_N0
20 CNV_PTX_DRX_N0
CNV_PTX_DRX_P0
20 CNV_PTX_DRX_P0
CLK_CNV_PTX_DRX_N
20 CLK_CNV_PTX_DRX_N
CLK_CNV_PTX_DRX_P
20 CLK_CNV_PTX_DRX_P
B
2 0_0402_5% CLKREQ_PCIE#15_R
2 0_0201_1% PCIE_WAKE#_R
RW9
RW31
1
1
R3019
R3021
1 CNV@
1 CNV@
R3023
R3024
R3025
R3026
@
2 0_0201_5% CNV_PTX_R_DRX_N1
2 0_0201_5% CNV_PTX_R_DRX_P1
1
3
5
7
9
11
13
15
17
19
21
23
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
GND1
USB_D+
USB_DGND2
SDIO_CLK
SDIO_CMD
SDIO_DAT0
SDIO_DAT1
SDIO_DAT2
SDIO_DAT3
SDIO_WAKE#
SDIO_RESET#
2 0_0201_5% CNV_PTX_R_DRX_N0
2 0_0201_5% CNV_PTX_R_DRX_P0
1 CNV@
1 CNV@
2 0_0201_5% CLK_CNV_PTX_R_DRX_N
2 0_0201_5% CLK_CNV_PTX_R_DRX_P
CONN@
2
4
6
8
10
12
14
16
18
20
22
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
e
r
TC105 TP@
CNV_RF_RESET#_D
CLKREQ_CNV#_D
CNV_RGI_PTX_R_DRX
CNV_RGI_PRX_R_DTX
CNV_BRI_PTX_R_DRX
EC_TX_R
EC_RX_R
CNV_RF_RESET#
A
5
4
1
4.7K_0201_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+3V_PCH_PRIM
CNV_RF_RESET#
RH724
1
@
2 1K_0201_5%
CLKREQ_CNV#
RH725
1
@
2 1K_0201_5%
2 0_0402_5%
TC110 TP@
2 0_0402_5% HOST_DEBUG_TX
HOST_DEBUG_TX
3.3V
1.8V
1 RW18 CNV_RGI_PTX_DRX
CNV_RGI_PTX_DRX
20
1 RW21 CNV_RGI_PRX_DTX
CNV_RGI_PRX_DTX
20
1 RW20 CNV_BRI_PTX_DRX
CNV_BRI_PTX_DRX
20
1 RW25
1 RW26
2
2
2
2
2
CNV_BRI_PRX_DTX
CNV@
CNV@
CNV@
CNV@
CNV@
26
SUSCLK_WLAN
18
PLTRST# 17,23,26,34,35,41,48
REFCLK_CNV
REFCLK_CNV
17
+3.3V_WLAN
DN1
WLAN_RADIO_DIS#_R
2
76
77
MAIN@
1
WLAN_RADIO_DIS#
20
RB751S40T1G_SOD523-2
DN2
BT_RADIO_DIS#_R
2
B
MAIN@
1
BT_RADIO_DIS#
20
RB751S40T1G_SOD523-2
Device side
1
3
CLKREQ_CNV#_D
RH745
100K_0201_5%
2
2
PCH side
5
6
4
2
C
20
@
+3V_PCH_PRIM
5
QH8B
L2N7002DW1T1G_SC88-6
18
CLKREQ_CNV#
CLKREQ_CNV#
2
QH9B
L2N7002DW1T1G_SC88-6
1
1
2
TC107 TP@
TC108 TP@
QH8A
L2N7002DW1T1G_SC88-6
CNV@
75K_0402_1%
RW29
QH9A
L2N7002DW1T1G_SC88-6
2
2
CNV@
1
1 RW19 CNV_BRI_PRX_DTX
Device side
RH744
100K_0201_5%
75K_0402_1%
RW4
RH723
4
CNV_RF_RESET#
CLKREQ_CNV#_D
CNV_RF_RESET#_D
1
18
4.7K_0201_5%
RW13 1
RW15 1
TC109 TP@
SUSCLK_WLAN
PLTRST#
BT_RADIO_DIS#_R
WLAN_RADIO_DIS#_R
LOTES_APCI0136-P001A
6
r
o
F
PCH side
2
2 CNV@
A Key CONN
+3V_PCH_PRIM
1
TC106 TP@
CNV_BRI_PRX_R_DTX 0_0402_5%
L
L
UART_TXD
GND4
UART_CTS
PETp0
UART_RTS
PETn0
VENDER_DEFINED1
GND5
VENDOR_DEFINED2
PERp0
VENDOR_DEFINED3
PERn0
COEX3
GND6
COEX2
REFCLKP0
COEX1
REFCLKN0
SUSCLK(32kHz)
GND7
PERST0#
CLKREQ0#
W_DISABLE2#
PEWAKE0#
W_DISABLE1#
GND8
I2C_DATA
RESERVED/PETp1
I2C_CLK
RESERVED/PETn1
ALERT#
GND9
RESERVED
RESERVED/PERp1
UIM_SWP/PERST1#
RESERVED/PERn1 UIM_POWER_SNK/CLKREQ1#
GND10
UIM_POWER_SRC/GPIO1/PEWAKE1#
RESERVED/REFCLKP1
3.3V3
RESERVED/REFCLKN1
3.3V4
GND11
GND12
GND13
E
D
1 CNV@
1 CNV@
3.3V1
3.3V2
LED1#
PCM_CLK/I2S_SCK
PCM_SYNC/I2S_WS
PCM_IN/I2S_SD_IN
PCM_OUT/I2S_SD_OUT
LED2#
GND3
UART_WAKE#
UART_RXD
1
C
USB20_P7
USB20_N7
RH722
3
Reserved for NGFF Debug Card
UART_2_CRXD_DTXD
CNV_RF_RESET#_D
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
NGFF WLAN
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
33
of
78
5
4
Main Func = SSD
3
2
1
M Key CONN
Update OK
w
e
i
v
D
+3VS_SSD
JP10
1
16
16
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
16
16
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
16
16
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
16
16
PCIE_PRX_DTX_N11
PCIE_PRX_DTX_P11
16
16
PCIE_PTX_DRX_N11
PCIE_PTX_DRX_P11
16
16
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12
16
16
PCIE_PTX_DRX_N12
PCIE_PTX_DRX_P12
17
17
CS16
CS17
1
1
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9
CS18
CS19
1
1
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_PTX_C_DRX_N10
PCIE_PTX_C_DRX_P10
CS20
CS21
1
1
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11
CS22
CS23
1
1
2
2
0.22U_0402_16V7K
0.22U_0402_16V7K
PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12
CLK_PCIE_N9
CLK_PCIE_P9
+3V_PCH_PRIM
2
RS2
1
10K_0402_5%
GND1
GND2
PETn3
PETp3
GND3
PERn3
PERp3
GND4
PETn2
PETp2
GND5
PERn2
PERp2
GND6
PETn1
PETp1
GND7
PERn1
PERp1
GND8
PETn0/SATA-B+
PETp0/SATA-BGND9
PERn0/SATA-APERp0/SATA-A+
GND10
REFCLKN
REFCLKP
GND11
3.3VAUX1
3.3VAUX2
N/C1
N/C2
DAS/DSS#
3.3VAUX3
3.3VAUX4
3.3VAUX5
3.3VAUX6
N/C3
N/C4
N/C5
N/C6
N/C7
N/C8
N/C9
N/C10
N/C11
DEVSLP
N/C12
N/C13
N/C14
N/C15
N/C16
PERST#
CLKREQ#
PEW ake#
N/C17
N/C18
SSD_LED#
R77
1
e
r
@
2 PCH_SATA_LED#
0_0402_5%
PCH_SATA_LED#
L
L
SSD_DEVSLP
2
1
PJP@
2
2
JUMP_43X79
16,30
+3VS_SSD
SSD_DEVSLP2
RS9
SSD_DEVSLP
2
1
CS33
47U_0805_6.3V6M
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
2
1
CS34
47U_0805_6.3V6M
C
16
16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
2
1
CS35
22U_0603_6.3V6M
+3VS_SSD
JSSD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
2
1
CS36
22U_0603_6.3V6M
2
1
CS27
1000P_0402_50V7K~D
2
1
CS26
0.1U_0402_25V6K~D
1
CS25
1U_0402_6.3V6K~D
2
NGFF Key M
CS24
10U_0805_25V6K~D
1
D
+3VS
@
C
1
10K_0402_5%
19
PLTRST# 17,23,26,33,35,41,48
CLKREQ_PCIE#9
17
PCIE_WAKE#_SSD_R
1
RS10
@
2
0_0201_5%
PCIE_WAKE#
18,26,33,35,41
Key M
16
E
D
67
69
71
73
75
M2_SSD_DETECT
B
77
N/C19
SUSCLK(32kHz)(O)(0/3.3V)
PEDET(OC-PCIe/GND-SATA)
3.3VAUX7
GND13
3.3VAUX8
GND15
3.3VAUX9
GND17
PTH2
PTH1
68
70
72
74
B
76
LCN_DAN05-67306-0103
PEDET
A
5
r
o
F
Module Type
0
SATA
1
PCIE
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
NVMe SSD
Size
3
2
Rev
0.3
LA-F611P
Date:
4
Document Number
Sheet
Thursday, March 22, 2018
1
34
of
78
5
4
Update OK
2
RTL8106E-CG
SA000080P00
SA000065Y00
LDO mode
LDO mode
CL10
2
LANXIN_R
1
40 mils
1
1
CL19
1
CL6
CL5
CL15
1
3
CL11
2
1
10/100/1000M
1
10/100M
1 EMI@
XTAL0 GND0
XTAL1 GND1
+3VS
2
LANXIN
33_0402_5%
RL8
YL1 MAIN@
1
1
RTL8111H-CG
2
RL3
1K_0402_5%
4
25MHZ_10PF_7V25000014
LANXOUT_R
1 EMI@
RL9
2
LANXOUT
33_0402_5%
w
e
i
v
ISOLATE#
2
UL1
Layout:
For RTL8111H-CG
* Place CL20 and CL7 and CL8 close to each VDD33 pin 11, 32 ,23
For RTL8106E
* Place CL7 and CL8 close to each VDD33 pin 23, 32
LAN_MDIP0
LAN_MDIN0
+LAN_VDD33
VDD10
LAN_MDIP3
LAN_MDIN3
+LAN_VDD33
CLKREQ_PCIE#14_R
PCIE_PTX_C_DRX_P14
PCIE_PTX_C_DRX_N14
CL8
17
1
.1U_0402_16V7K
2
1
16
16
CL8: close to Pin23
CL20: close to Pin11
CL7: close to Pin32
2
RL13 1
CLKREQ_PCIE#14
PCIE_PTX_DRX_P14
PCIE_PTX_DRX_N14
17
17
CL3
CL4
CLK_PCIE_P14
CLK_PCIE_N14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PCIE_PRX_C_DTX_P14
PCIE_PRX_C_DTX_N14
PLTRST#
ISOLATE#
PCIE_WAKE#
17,23,26,33,34,41,48
PCIE_PRX_DTX_P14
PCIE_PRX_DTX_N14
16
16
PCIE_WAKE# 18,26,33,34,41
2 1U_0402_10V6K
CL22 1
CL23 1
TP@ T45
2 0_0402_5%
2 .1U_0402_16V7K
+LAN_VDD33
TP@ T47
RL2
1 2.49K_0402_1%
2
e
r
LAN TransFormer (10/100/1000M & 10/100M co-layout)
1
2
CL25
4.7U_0603_6.3V6K
@
TL1
L
L
LAN_MDIN3
12
LAN_MDIP3
11
10
+LAN_VDD33 Rising time (10%~90%) need
>0.5mS and <100mS.
9
LAN_MDIN2
8
LAN_MDIP2
7
LAN_MDIN1
6
LAN_MDIP1
5
4
3
LAN_MDIN0
LAN_MDIP0
2
1
LOM_TCT
E
D
TD4-
TX4-
TD4+
TX4+
TDCT4
TXCT4
TDCT3
TXCT3
TD3-
TX3-
TD3+
TX3+
TD2-
TX2-
TD2+
TX2+
TDCT2
TXCT2
TDCT1
TXCT1
TD1-
TX1-
TD1+
TX1+
MHPC_NS692417
MAIN@
RJ45_MDIN3
13
RJ45_MDIP3
14
15
MCT0
16
MCT1
RJ45_MDIN2
17
+LAN_VDD33
UL2
2
CL9
1
1U_0402_6.3V6K
5
4
AUX_ON
2
High Active
IN
+3VALW
1
OUT
2
GND
3
EN
OC
SY6288C20AAC_SOT23-5
MAIN@
2
RL7
1
2
1
10K_0402_5%
RJ45_MDIN1
19
RJ45_MDIP1
20
21
MCT2
22
MCT3
23
RJ45_MDIN0
24
RJ45_MDIP0
1
A
5
1
2
CL13
100P_1206_2KV8J
ESD@
Layout note:
30 mil spacing between MDI differential pairs.
B
Follow Reference Schematic 0.01uF~0.4uF
RL6
100K_0402_5%
r
o
F
CL12
0.01U_0402_50V7K
MCT3
MCT2
MCT1
MCT0
RJ45_MDIP2
18
Layout note:
30 mil spacing between MDI differential pairs.
+3VALW
B
C
1
1
1
1
Layout:
CL24: close to Pin32
CL25: close to Pin11
26
2 .1U_0402_16V7K
2 .1U_0402_16V7K
PLTRST#
VDD10
+LAN_VDD33
VDD10
LED1
RL17 1
@
LED0
LANXIN
LANXOUT
VDD10
RSET
+LAN_VDD33
1
1
CL1
CL2
2 75_0603_5%
2 75_0603_5%
2 75_0603_5%
2 75_0603_5%
2
1
1
HSOP
HSON
PERSTB
ISOLATEB
LANWAKEB
DVDD10
VDDREG
REGOUT
LED2
LED1/GPO
LED0
CKXTAL1
CKXTAL2
AVDD10
RSET
AVDD33
GND
RTL8111H-CG_QFN32_4X4
+LAN_VDD33
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
C
CL24
4.7U_0603_6.3V6K
@
2 0_0402_5%
@
MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
MDIP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
CLKREQB
HSIP
HSIN
REFCLK_P
REFCLK_N
MCT RL14
RL15
RL19
RL20
CL7
.1U_0402_16V7K
CL20
.1U_0402_16V7K
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD10
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
40 mils
1
D
RL4
15K_0402_5%
2
2
2
.1U_0402_16V7K
2
.1U_0402_16V7K
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
10P_0402_50V8J
D
2
CL5: close to Pin8
CL6: close to Pin30
CL18: close to Pin3
CL19: close to Pin22
10P_0402_50V8J
VDD10
1
LAN Chip (10/100/1000M & 10/100M co-layout)
Layout:
For RTL8111H-CG
* Place CL5,CL6,CL18,CL19 close to each VDD10 pin 8, 30, 3, 22
For RTL8106E
* Place CL5,CL6 close to each VDD10 pin 8, 30
CL18
CL15,RL1:
Only for
RTL8111 LDO mode.
3
1
Main Func = LAN
JLAN1
1.0V Source RL1
RTL8111H-CG
RTL8111G-CGT
(71.08111.U03)
LDO
RTL8106E-CG
(071.08106.0003)
LDO
O
X
CL15
O
X
CL18
O
X
CL19
O
X
CL20
O
X
CL8
X
RJ45_MDIN3
8
RJ45_MDIP3
7
RJ45_MDIN1
6
RJ45_MDIN2
5
RJ45_MDIP2
4
RJ45_MDIP1
3
RJ45_MDIN0
2
RJ45_MDIP0
1
PR4PR4+
PR2PR3PR3+
PR2+
PR1PR1+
GND
GND
GND
GND
SINGA_2RJ3076-058211F
CONN@
O
9
10
11
12
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
LAN RTL8111
Thursday, March 22, 2018
1
Sheet
35
of
78
5
4
3
2
1
Main Func = DC/DC
+VCCSTG Load Switch
+VCCPLL_OC Load Switch
D
7
+5VALW
EN_VCCSTG_VCCPLL_OC
3
4
+5VALW
1
2
CZ50
0.1U_0402_10V7K
VOUT
VOUT
ON
CT
VBIAS
GND
GND
1
2
C
VIN
VIN
7
8
2
@
2
1
0_0603_1%
2
CZ571
@
2200P_0402_25V7K
6
1
2
5
9
L
L
E
D
+3V_PCH_PRIM
1
2
B
UC12
Y
A
G
CPU_VCCIO_PWR_GATE#
1
3
20
2
RZ237
@ 2
RZ234
P
5
2
5
VIN thermal
r
o
F
EN_VCCSTG_VCCPLL_OC
EN_VCCSTG_VCCPLL_OC
6
VOUT
2
@
1
0_0603_1%
VBIAS
ON
1
5
GND
CZ47
0.1U_0402_10V6K
2
TPS22961DNYR_WSON8
SA00007XR00
MAIN@
4.4mohm/6A
TR=12.5us@Vin=1.05V
e
r
VCCSTG_EN
1
1
CZ111
0.1U_0402_10V6K
C
2
B
64
TC7SH08FUF_SSOP5
S0IX@
AND GATE
MAX delay time:14ns
1
0_0201_5%
A
4
CC148
0.1U_0201_10V6K
S0IX@
D
+VCCSTG
RZ48
DVT1.
Add RZ49 10K, CZ111 0.1uF for +VCCSTG t i m
i ng t uni ng.
B
SIO_SLP_S3#
1
0_0201_5%
CPU_VCCIO_PWR_GATE#
1
0_0201_5%
4
VIN1
VIN2
EN_VCCSTG_VCCPLL_OC
2
RZ49
10K_0402_5%
AOZ1336DI_DFN8_2X2
CZ51
MAIN@
0.1U_0402_10V7K
+1.05VALW TO +1.0VS_VCCSTG
SIO_SLP_S3#
VCCSTG_EN
CZ49
0.1U_0402_10V7K
Power Gating by Modern Standby Control
18,37,41
2
RZ67
UZ16
@ CZ86
0.1U_0402_10V7K
+1.2V_VCCPLL_OC
CZ88
1U_0402_6.3V6K
1
+1.2V_VCCPLL_OC_OUT
1
3
1
2
+VCCSTG_OUT
UZ9
1
2
H-Processor Line - Quad Core GT2
Max : 130 mA
+1.2V_DDR
w
e
i
v
+1.05VALW
2
RZ238
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
DC/DC(1/2)
Size
3
2
Rev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
36
of
78
5
4
3
2
1
Main Func = DC/DC
+5VALW to +5VS
+3VALW to +3VS
+3VS
+3V_PCH_PRIM Load Switch
w
e
i
v
UZ1
6
7
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
14
13
12
CZ11 1
1
2
CZ9
0.1U_0402_10V7K
2 0.01U_0402_16V7K
CZ10 1
2 470P_0402_50V7K
11
DVT1.0 Change CZ10 to 470pF
10
@
CZ37 2
VOUT2
VOUT2
1U_0402_6.3V6K
21,26,65,66
PCH_PRIM_EN
RZ21 1 GEN9@ 2 0_0402_5%
+5VS
SA00007PM00
@
CZ46
0.1U_0402_16V7K
MAIN@
2
+1.2V_DDR Enable
DZ1
1
2
RB751S40T1G_SOD523-2
MAIN@
SIO_SLP_S4#
RZ102
1
2 100K_0402_5%
1
2
DVT1.0 Change CZ102 to 0.1uF
DZ2
1
+VCCIO Enable
2
RB751S40T1G_SOD523-2
MAIN@
r
o
F
SIO_SLP_S3#
RZ108
1
2 150K_0402_5%
1
2
A
VCCIO_EN
CZ108
0.22U_0402_10V4Z
2
1
2
2
1
@
CZ40
0.1U_0402_10V7K
1
2
63
18,66
SIO_SLP_S4#
SIO_SLP_S3#
ON
CT
1
7
8
2
6
VBIAS
GND
GND
5
9
CZ32
0.1U_0402_10V7K
CZ33 GEN9@
100P_0402_50V8J
1
TPS22967DSGR_SON8_2X2
GEN9_M@
C
+VCCST Load Switch
B
+1.05VALW
UZ15
1
2
7
+5VALW
3
1
DVT1.0
Add RZ111 connect to SIO_SLP_S4#
Add RZ112(@) connect to SIO_SLP_S3#
Add net VCCST_EN
18,36,41
VOUT
VOUT
2
4
+5VALW
VIN
VIN
e
r
L
L
E
D
1.2V_VDDQ_EN
CZ102
0.1U_0402_10V6K
1
C56 RF@
33P_0201_25V8F
CZ109
10U_0603_6.3V6M
2
2
C54 RF@
33P_0201_25V8F
CZ110
10U_0603_6.3V6M
1
RF@
2
@ CZ25
1U_0603_10V6K
2
C55
1
@ CZ23
1U_0603_10V6K
1
68P_0201_50V8J
1
RF@
B
+5VS
1
3
+3VS
C53
2
+3VS
68P_0201_50V8J
+3VALW
1
C
+5VS
Close JPZ1 and JPZ2
1
2
+3VALW
1
2
CZ12 0.1U_0402_10V7K
15
GPAD
+5VALW
1
UZ7
9
8
EM5209VF_DFN14_3X2
Close UZ1
D
+3V_PCH_PRIM
RZ111
1
RZ112
1
@
2
4
+VCCST
VIN1
VIN2
VIN thermal
VOUT
6
1
VBIAS
ON
GND
5
1
+5VALW
5
VOUT1
VOUT1
ON1
CZ28
0.1U_0402_10V6K
2
4
SIO_SLP_S3#
VIN1
VIN1
1
3
2
1
2
@ CZ97
0.1U_0402_25V6
+3VALW
SIO_SLP_S3#
CZ96
1U_0402_6.3V6K
D
2
C151
22U_0603_6.3V6M
TPS22961DNYR_WSON8
SA00007XR00
MAIN@
4.4mohm/6A
TR=12.5us@Vin=1.05V
VCCST_EN
2 0_0402_5%
2 0_0402_5%
64
A
DVT1.0 Change CZ108 to 0.22uF
5
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
DC/DC(2/2)
Size
4
3
2
Document Number
R ev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
37
of
78
5
4
3
2
1
Main Func = CMC
w
e
i
v
PRIMARY CMC CONN.
D
+1.05VALW
+1.05V_XDP
CMC@
RC251 1
+3V_PCH_PRIM
2 0_0603_5%
For Power consumption
Measurement
CMC@
RC252 1
XDP_SPI_SI
2 1K_0402_5%
RC264
1 CMC@
2 1K_0402_1%
PCH_SPI_SI_R
PCH_SPI_SI_R
17,23
SYMBOL
+VCCSTG
Place to CPU side
RC76
2 CMC@
1 51_0402_5%
CPU_XDP_TMS
RC77
2 CMC@
1 51_0402_5%
CPU_XDP_TDI
RC78
2 CMC@
1 51_0402_5%
CPU_XDP_TDO
RC80 1 CMC@
2 1K_0402_5%
XDP_ITP_PMODE
CPU_XDP_TMS
10,18
CPU_XDP_TDI
10,18
CPU_XDP_TDO
10,18
+1.05V_XDP
XDP_ITP_PMODE
18
2 CMC@
1 51_0402_5%
CPU_XDP_TCK0
RC84
2
1 51_0402_5%
PCH_JTAG_TCK1
C
@
2
@
1 51_0402_5%
CPU_XDP_TRST#
RC144 2
@
1 0_0402_5%
XDP_PRSENT_CPU
RC145 2
@
1 0_0402_5%
XDP_PRSENT_PCH
RC85
CPU_XDP_TCK0
10,18
PCH_JTAG_TCK1
18
CPU_XDP_TRST#
10,22
5
10
10
CFG17
CFG16
10
10
CFG19
CFG18
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
TPC10
TPC11
TPC12
TPC13
TPC14
TPC15
TPC16
TPC17
CFG17
CFG16
TPC18
TPC19
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
TPC20
TPC21
TPC22
TPC23
TPC24
TPC25
TPC26
TPC27
CFG19
CFG18
TPC28
TPC29
TPC6
TPC5
TPC4
TPC2
TPC3
TPC1
TPC30
TPC31
TPC32
TPC8
TPC7
TPC9
TPC33
SWAP @0415
L
L
B
A
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
10 CFG8
10 CFG9
10 CFG10
10 CFG11
10 CFG12
10 CFG13
10 CFG14
10 CFG15
Place to CPU side
RC83
10
10
10
10
10
10
10
10
r
o
F
4
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK0
PCH_JTAG_TCK1
CPU_XDP_TDO
e
r
XDP_PREQ#
XDP_PRDY#
XDP_PREQ#
XDP_PRDY#
XDP_HOOK0 1K_0402_5%
XDP_SPI_SI
XDP_ITP_PMODE
XDP_PRSENT_PCH
XDP_PRSENT_CPU
2 CMC@
1 RC86
1K_0402_5% 2 CMC@
1K_0402_5% 2 CMC@
10,22
10,22
PCH_RSMRST#
1 RC249
1 RC250
PCH_RSMRST#
PCH_SPI_WP#_R
CFG3
D
18,26
PCH_SPI_WP#_R
17
E
D
C
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
CMC
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
38
of
78
5
4
3
2
1
Main Func = Reserved
w
e
i
v
D
e
Reserved r
L
L
E
D
C
B
A
5
r
o
F
D
C
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Reserved
Size
4
3
2
Document Number
R ev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
39
of
78
5
4
3
2
1
Main Func = PD + TYPE C
+3VALW_PD
+5VALW
2 0_0603_5%
VBUS_P_CTRL_P1
TBTA_HPD
OVP_TRIP_P1
RT164
RT111
PWR_BTN_DOCK1# RT165
C
PD_EE_CLK_R
TBT@EMI@
RT123
2
2 PD@
2 PD@
2 DOCK@
1 0_0201_5%
TBT_CONFIG
1 15_0201_1%
Change RT123.2 connect to net PD_EE_CLK_R
RT62 2 PD@
1 0_0201_5%
1 1M_0201_1%
PD_EE_CLK
PD_EE_DI
PD_EE_DO
PD_EE_CS_N
A3
B4
A4
B3
USB20_P4_R
USB20_N4_R
L5
K5
PD_UART
E2
F2
1 100K_0201_5%
T62
TI's Request
T63
26,41
TBT_RESET_N_EC#
RT122
+3.3V_FLASH
2
@
+3.3V_TBT_SX
RT114 1
RT115 1
2 0_0201_5%
2 0_0201_5%
TBTA_MRESET
E11
TBTA_LSTX
TBTA_LSRX
L4
K4
TBTA_DIG_AUD_P
TBTA_DIG_AUD_N
L3
K3
TBTA_DEBUG1
TBTA_DEBUG2
L2
K2
TBT_A_AUX_P_C
TBT_A_AUX_N_C
TBT_A_AUX_P_C
TBT_A_AUX_N_C
1
41
41
TBTA_ROSC
G2
TBTA_HRESET
BUSPOWER#
RT118
RT119
2 PD@
2 PD@
1 0_0402_5%
1 0_0402_5%
TBTA_DEBUG1
TBTA_DEBUG2
PD@
RT75
15K_0402_0.1%
B9
A10
B10
HV_GATE2_A
HV_GATE1_A
MRESET
SENSEN
RPD_G1
RPD_G2
TBT_LSTX/R2P
TBT_LSRX/P2R
DIG_AUD_P/DEBUG3
DIG_AUD_N/DEBUG4
DEBUG_CTL1
DEBUG_CTL2
DEBUG1
DEBUG2
C_SBU1
AUX_P
AUX_N
BUSPOWER_N
R_OSC
HRESET
+3.3V_TBT_SX_R
+TBTA_VBUS
@
2
0_0201_5%
C_SBU2
RESET_N
e
r
+3.3V_FLASH
H11
J10
J11
K11
1
2
H2
1
CT102
1U_0201_6.3V6M
PD@
2
G1
K6
L6
TBT_A_USB20_PT
TBT_A_USB20_NT
K7
L7
TBT_A_USB20_PB
TBT_A_USB20_NB
L9
L10
TBT_A_CC1
TBT_A_CC2
CT103
10U_0402_6.3V6M
PD@
PD@
2 220P_0201_25V7K
CT112 1
2 220P_0201_25V7K
CT113 1
TI's Requirement
PD@
K9
K10
PD@
RT66
10K_0201_5%
K8
TBT_A_SBU1
L8
TBT_A_SBU2
F11
RESET_N
L11
NC
SN1610042ZQZR BGA 96P_BGA96
PD@
DT7
1
TBT_A_TRX_DTX_P1
DT8
1
2
TBT@ESD_M@
2
TBT@ESD_M@
1
RT102
@
1
DT9
2
TBT@ESD_M@
LT2 TBT@EMI_M@
TBT_A_USB20_PT
1
2
TBT_A_USB20_L_PT
TBT_A_USB20_NT
4
3
TBT_A_USB20_L_NT
TBT_A_USB20_NB
1
2
TBT_A_USB20_L_NB
TBT_A_USB20_PB
4
3
TBT_A_USB20_L_PB
C
SM070003Z00
LT3 TBT@EMI_M@
MCM1012B900F06BP_4P
SM070003Z00
DT10
TBT_A_USB20_L_PT
1
9
TBT_A_USB20_L_PT
TBT_A_USB20_L_NT
2
8
TBT_A_USB20_L_NT
TBT_A_USB20_L_NB
4
7
TBT_A_USB20_L_NB
TBT_A_USB20_L_PB
5
6
TBT_A_USB20_L_PB
Differential Signal
TVWDF1004AD0_DFN9
TBT@ESD_M@
TBT_RESET_N
2
0_0201_5%
TBT_RESET_N
41
DT11
TBT_A_CC2
1
9
TBT_A_CC2
TBT_A_CC1
2
8
TBT_A_CC1
TBT_A_SBU1
4
7
TBT_A_SBU1
TBT_A_SBU2
5
6
TBT_A_SBU2
+TBTA_VBUS
PD@
CT104
0.22U_0402_10V4Z
B
3
DT16
AZ4024-02S_SOT23-3~D
ESD_M@
TVWDF1004AD0_DFN9
TBT@ESD_M@
+TBTA_VBUS
+TBTA_VBUS
JUSBC1
A1
41
41
PD_EE_CLK_R
UT3
Close UT3
2
CT137
0.1U_0201_6.3V6K
PD@
SA00003GM30
@EMI@
1
A2
A3
TBT_A_TTX_C_DRX_P1
TBT_A_TTX_C_DRX_N1
TBT@
+3.3V_FLASH
PD_EE_HOLD#
PD_EE_CLK_R
PD_EE_DI
TBT@ESD_M@
MCM1012B900F06BP_4P
PD@
RT67
10K_0201_5%
DVT1.0
Un-pop RT102
PD_EE_DO
PD_EE_CS_N
PD_EE_WP#
PD_EE_HOLD#
8
CS#
VCC 7
DO
HOLD# 6
WP#
CLK 5
GND
DI
W25X20CLSNIG_SO8
2
3
+3.3V_FLASH
1 3.3K_0201_5%
1 3.3K_0201_5%
1 3.3K_0201_5%
1 3.3K_0201_5%
TBT_A_TTX_C_DRX_N1
+3.3V_FLASH
DEBUG_CTL1
DEBUG_CTL2
E4
D5
DVT1.0
Add RT125(3.3K), RT126(3.3K), RT127(3.3K), RT128(3.3K), UT5, CT117(0.1u)
1
2
3
4
1
D
TBT@ESD_M@
AZ5B75-01B.R7G_CSP0603P2Y2
TBTA_HRESET might be connected to EC
or PCH to allow TPS65982 FW load
Active high hardware reset input. Will re-load settings
from optional external flash memory. Ground pin when
HRESET functionality will not be used.
PD_EE_CS_N
PD_EE_DO
PD_EE_WP#
DT6
TBT_A_TRX_DTX_N1
+3.3V_TBT_SX
1
RT61
@EMI@
r
o
F
2
2 PD@
2 PD@
2 PD@
2 PD@
TBT_A_TTX_C_DRX_P1
2
AZ5B75-01B.R7G_CSP0603P2Y2
CT156
RT156
33P_0402_50V8J
33_0402_5%
5
SENSEP
A6
A7
A8
B7
PP_FCM
PP_FCM
PP_FCM
PP_FCM
A11
B11
C11
D11
H10
PP_5V0
PP_5V0
PP_5V0
PP_5V0
A2
K1
E1
PP_CABLE
LDO_BMC
LDO_1V8D
B1
H1
C_USB_BP
C_USB_BN
SWD_DATA
SWD_CLK
RT125
RT126
RT127
RT128
1
AZ5B75-01B.R7G_CSP0603P2Y2
L
L
UART_TX
UART_RX
1
PD@
RT108
0_0201_5%
BUSPOWERZ
Sampled by ADC at boot. Tie pin to LDO_3V3
through a 100-kohm resistor to disable PP_EXT
power path during dead-battery or no-battery boot
conditions.
A
D6
DT5
TBT@ESD_M@
AZ5B75-01B.R7G_CSP0603P2Y2
C_USB_TP
C_USB_TN
SA0000AX700
2
PD_I2C_SCL_R
PD_I2C_SDA_R
0_0402_5%
USB_RP_P
USB_RP_N
E
D
F10
TBTA_HRESET
26
J1
J2
2 BUSPOWER#
0_0201_5%
1
1 0_0201_5%
TBTA_DIG_AUD_P
TBTA_DIG_AUD_N
TBTA_DEBUG1
TBTA_DEBUG2
2
LDO_3V3
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS_N
A1
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
@
2
RT163 2
1
1
1
1
1
RT74
1
B
2 PD@
2 PD@
2
@
2
@
+3.3V_FLASH
2
RT68
RT69
RT71
RT72
PD@
RT73
100K_0201_5%
1
VOUT_3V3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
PD@
RT70
100K_0201_5%
2
PD@
RT113
100K_0201_5%
RT65 @
VBUS
VBUS
VBUS
VBUS
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
1
1
TBT_CONFIG
@
@
0_0402_5%
C_CC1
C_CC2
1 100K_0201_5%
41 TBTA_LSTX
41 TBTA_LSRX
PD@
RT112
10K_0201_5%
F4
G4
@
@
I2C_SDA2
I2C_SCL2
I2C_IRQ2_N
1 0_0201_5%
1
RT63 2 PD@
B2
C2
D10
G11
C10
E10
G10
D7
H6
TBT_A_TRX_DTX_N0
2
1
60
41
60
EN_PD_HV_1
2
2
60
T65
@
EN_PD_HV_1
1
TBT@
41
41
CT97 1
CT96 1
2 0.01U_0402_50V7K
A4
TBT_A_CC2
A5
TBT_A_USB20_L_PB
TBT_A_USB20_L_NB
A6
A7
TBT_A_SBU2
A8
2 0.01U_0402_50V7K
A9
A10
A11
TBT_A_TRX_DTX_N0
TBT_A_TRX_DTX_P0
A12
GND
GND
SSTXp1
SSTXn1
SSRXp1
SSRXn1
VBUS
VBUS
CC1
SBU2
Dp1
Dn1
Dn2
Dp2
SBU1
VBUS
SSRXn2
SSRXp2
Bottom
A5
B5
B6
I2C_SDA1
I2C_SCL1
I2C_IRQ1_N
DT4
TOP
PD_I2C_SDA_R
PD_I2C_SCL_R
PD_I2C_INT#
2
0_0402_5%
2
0_0402_5%
1 0_0402_5%
PD@
DVT1.0
Change net INT#_TYPEC to UPD_SMBINT#
2
D1
D2
C1
TBT_I2C_SDA
TBT_I2C_SCL
TBTA_I2C_INT
I2C_ADDR
1
1
1
RT59
1
RT60
RT120 2
41
41
41
F1
LDO_1V8A
2
RT58
10K_0201_5%
@
UT4
2 0_0201_5%
VDDIO
RT57
10K_0201_5%
@
Q29 DOCK@
26 TYPEC_SMBDA
26 TYPEC_SMBCLK
26 UPD1_ALERT
1
1
PWR_BTN_DOCK1#
S
3
D
DOCK@1 1
0_0201_5%
RT167
L2N7002WT1G_SC-70-3
RT83 1 PD@
2
2
G
PWR_TB_DOCK# 2
2
Master0:0 ohm
Slave1:93.1K ohm
2
PWR_TB_DOCK#
VIN_3V3
1
DOCK@
RT166
100K_0201_5%
PWR_TB_DOCK#
26
PD@
CT101
1U_0402_6.3V6K
RT64 @
A9
+3.3V_TBT_SX
1
TBT@ESD_M@
AZ5B75-01B.R7G_CSP0603P2Y2
+3VALW_PD
+3VS
2
w
e
i
v
CT100
4.7U_0603_10V6K
PD@
2
1
DT3
TBT_A_TRX_DTX_P0
2
CT99
4.7U_0603_10V6K
PD@
Co-Lay PCH USB2.0 for AR USB2 issue
TBT@ESD_M@
AZ5B75-01B.R7G_CSP0603P2Y2
1
3
2
Close to UT4
1
CT98
2.2U_0603_16V6K
PD@
2
AZ5B75-01B.R7G_CSP0603P2Y2
1
USB20_P4_R
USB20_N4_R
1
2 0_0402_5%
2 0_0402_5%
TBT_A_TTX_C_DRX_N0
2
@
@
1
1
DT2
AZ5B75-01B.R7G_CSP0603P2Y2
PD@
CT106
1U_0603_25V6K
2
1
1
RT132
RT133
USB20_P4_R
USB20_N4_R
TBT_A_TTX_C_DRX_P0
Change DT1 and add DT15 follow E-team's design for DELL dat.04/07
HV_GATE2
USB20_P4
USB20_N4
USB20_P4
USB20_N4
1 0_0402_5%
1 0_0402_5%
2
HV_GATE1
19
19
2
2
2
TBT_A_USB20_P RT130
TBT_A_USB20_N RT131
TBT_A_USB20_P
TBT_A_USB20_N
2
1
CT93
PD@
TBTA_LDO_BMC
+1.8VD_TBTA_LDO
+1.8VA_TBTA_LDO
D
41
41
2
1
CT92
PD@
22U_0603_6.3V6M
2
1
CT91
PD@
22U_0603_6.3V6M
1
CT90
PD@
22U_0603_6.3V6M
2
+TBTA_VBUS
60mil 3A
60mil 3A
CT88
0.1U_0402_10V6K
PD@
2
1
1
@
1
1
22U_0603_6.3V6M
Update OK
RT134
2
+3VALW
CC2
VBUS
SSTXn2
SSTXp2
GND
GND
GND1
GND2
GND3
GND4
GND5
GND6
B12
B11
B10
TBT_A_TRX_DTX_P1
TBT_A_TRX_DTX_N1
B9
TBT@
CT95 1
41
41
2 0.01U_0402_50V7K
TBT_A_SBU1
B8
TBT_A_USB20_L_NT
TBT_A_USB20_L_PT
B7
B6
TBT_A_CC1
B5
B4
TBT@
CT94 1
B3
B2
2 0.01U_0402_50V7K
TBT_A_TTX_C_DRX_N0
TBT_A_TTX_C_DRX_P0
41
41
B1
A
PD_M@
1
2
3
4
5
6
FOX_UT12113-116B2-7H
CONN@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
PD+USB3.1 TypeC
Thursday, March 22, 2018
1
Sheet
40
of
78
5
4
3
2
1
Main Func = Thunderbolt
ARC1R3@
From CPU
Reserve for common DP design
CPU_DP1_AUXN_C RT76 1
CPU_DP1_AUXP_C RT78 1
CLKREQ_PCIE#0
RT24 1
6
6
TBT@ 2 100K_0201_5%
16
TBT@ 2 100K_0201_5%
TBT@ CT5 1
TBT@ CT21 1
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
PCIE_PTX_C_DRX_P24
PCIE_PTX_C_DRX_N24
H23
H22
CLK_PCIE_P0
CLK_PCIE_N0
CLKREQ_PCIE#0
6
6
CPU_DP1_P0
CPU_DP1_N0
6
6
CPU_DP1_P1
CPU_DP1_N1
TBT@ CT119 1
TBT@ CT120 1
2 0.1U_0201_6.3V6K CPU_DP1_P1_C
2 0.1U_0201_6.3V6K CPU_DP1_N1_C
AB9
AC9
6
6
CPU_DP1_P2
CPU_DP1_N2
TBT@ CT121 1
TBT@ CT122 1
2 0.1U_0201_6.3V6K CPU_DP1_P2_C
2 0.1U_0201_6.3V6K CPU_DP1_N2_C
AB11
AC11
CPU_DP1_P3
CPU_DP1_N3
TBT@ CT123 1
TBT@ CT124 1
2 0.1U_0201_6.3V6K CPU_DP1_P3_C
2 0.1U_0201_6.3V6K CPU_DP1_N3_C
AB13
AC13
TBT@ CT125 1
TBT@ CT126 1
2 0.1U_0201_6.3V6K CPU_DP1_AUXP_C Y11
2 0.1U_0201_6.3V6K CPU_DP1_AUXN_C W11
CPU_DP1_AUXP
CPU_DP1_AUXN
CPU_DP1_HPD
2 10K_0201_5%
@
V19
T19
AC5
CLKREQ_PCIE#0_R
2
TBT@ 1
RT2
0_0201_5%
2 0.1U_0201_6.3V6K CPU_DP1_P0_C
TBT@ CT117 1
2 0.1U_0201_6.3V6K CPU_DP1_N0_C
TBT@ CT118 1
6
6
+3VS_TBT
M23
M22
AB7
AC7
CPU_DP1_HPD
AA2
DPSNK1_DDC_CLK
DPSNK1_DDC_DATA
Y5
R4
AB15
AC15
AB17
AC17
+3.3V_LC
AB19
AC19
1
TBT@
2
1
2
1
2
2
TBT@
RT9
AB21
AC21
10K_0201_5%
TBT@
RT8
10K_0201_5%
RT7
10K_0201_5%
TBT@
10K_0201_5%
RT6
1
C
Y12
W12
Y6
TBT_TDI
TBT_TMS
TBT_TCK
TBT_TDO
Y8
N4
2 TBT@ 1
RT19
14K_0402_1%
2 TBT@ 1
RT25
4.75K_0402_0.5%
+3VS_TBT
TBTA_LSTX
CLKREQ_PCIE#0_R
RT21 2
@
RT20 2 TBT@
1 10K_0201_5%
1 10K_0201_5%
40
40
TBTA_LSTX
RT40 1 TBT@
2 1M_0201_1%
TBTA_LSRX
RT42 1 TBT@
2 1M_0201_1%
DPSNK1_DDC_CLK
DPSNK1_DDC_DATA
CPU_DP1_HPD
TBTA_HPD
TBT_RBIAS
TBT_RSENSE
H6
J6
2 0_0201_5%
2 0_0201_5%
TBT_A_TRX_DTX_P1_R A15
TBT_A_TRX_DTX_N1_R B15
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
TBT_A_TTX_DRX_P1
TBT_A_TTX_DRX_N1
40
40
TBT_A_TTX_C_DRX_P0
TBT_A_TTX_C_DRX_N0
TBT@ CT41 1
TBT@ CT42 1
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
TBT_A_TTX_DRX_P0
TBT_A_TTX_DRX_N0
2 0_0201_5%
2 0_0201_5%
TBT_A_TRX_DTX_P0_R B21
TBT_A_TRX_DTX_N0_R A21
2 0.1U_0201_6.3V6K
2 0.1U_0201_6.3V6K
TBT_A_AUX_P
TBT_A_AUX_N
Y15
W15
TBT_A_USB20_P
TBT_A_USB20_N
E20
D20
TBTA_LSTX
TBTA_LSRX
TBTA_HPD
A5
A4
M4
PA_USB2_RBIAS
H19
RT161
RT162
TBT_A_TRX_DTX_P0
TBT_A_TRX_DTX_N0
40
40
TBT_A_AUX_P_C
TBT_A_AUX_N_C
40
40
TBT_A_USB20_P
TBT_A_USB20_N
2 TBT@ 1
RT43
499_0201_1%
1
2
3
4
AC23
AB23
V18
AC1
L15
N15
C23
C22
PERST_N
PCIE_RBIAS
DPSNK0_ML0_P
DPSNK0_ML0_N
DPSRC_ML0_P
DPSRC_ML0_N
DPSNK0_ML1_P
DPSNK0_ML1_N
DPSNK0_ML2_P
DPSNK0_ML2_N
DPSNK0_ML3_P
DPSNK0_ML3_N
DPSNK0_AUX_P
DPSNK0_AUX_N
DPSRC_ML1_P
DPSRC_ML1_N
DPSRC_ML2_P
DPSRC_ML2_N
DPSRC_ML3_P
DPSRC_ML3_N
DPSRC_AUX_P
DPSRC_AUX_N
DPSNK0_HPD
DPSRC_HPD
DPSNK0_DDC_CLK
DPSNK0_DDC_DATA
DPSRC_RBIAS
DPSNK1_ML0_P
DPSNK1_ML0_N
DPSNK1_ML1_P
DPSNK1_ML1_N
DPSNK1_ML2_P
DPSNK1_ML2_N
DPSNK1_ML3_P
DPSNK1_ML3_N
DPSNK1_AUX_P
DPSNK1_AUX_N
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
POC_GPIO_0
POC_GPIO_1
POC_GPIO_2
POC_GPIO_3
POC_GPIO_4
POC_GPIO_5
POC_GPIO_6
L
L
DPSNK1_HPD
TEST_EN
DPSNK1_DDC_CLK
DPSNK1_DDC_DATA
TEST_PWR_GOOD
DPSNK_RBIAS
RESET_N
TDI
TMS
TCK
TDO
XTAL_25_IN
XTAL_25_OUT
MISC
RBIAS
RSENSE
EE_DI
EE_DO
EE_CS_N
EE_CLK
PA_RX1_P
PA_RX1_N
PB_RX1_P
PB_RX1_N
PA_TX1_P
PA_TX1_N
PB_TX1_P
PB_TX1_N
PA_TX0_P
PA_TX0_N
PB_TX0_P
PB_TX0_N
PA_RX0_P
PA_RX0_N
PA_DPSRC_AUX_P
PA_DPSRC_AUX_N
PA_USB2_D_P
PA_USB2_D_N
PA_LS_G1
PA_LS_G2
PA_LS_G3
PB_RX0_P
PB_RX0_N
PB_DPSRC_AUX_P
PB_DPSRC_AUX_N
PB_USB2_D_P
PB_USB2_D_N
PA_USB2_RBIAS
PB_LS_G1
PB_LS_G2
PB_LS_G3
PB_USB2_RBIAS
THERMDA
THERMDA
MONDC_SVR
ATEST_P
ATEST_N
PCIE_ATEST
DEBUG
TEST_EDM
USB2_ATEST
FUSE_VQPS_64
FUSE_VQPS_128
MONDC_DPSNK_0
MONDC_DPSNK_1
MONDC_CIO_0
MONDC_CIO_1
MONDC_DPSRC
2
2
1 CT14
1 CT16
TBT@
TBT@
P23 PCIE_PRX_C_DTX_P22
P22 PCIE_PRX_C_DTX_N22
0.22U_0201_6.3V
0.22U_0201_6.3V
2
2
1 CT12
1 CT2
TBT@
TBT@
K23 PCIE_PRX_C_DTX_P23
K22 PCIE_PRX_C_DTX_N23
0.22U_0201_6.3V
0.22U_0201_6.3V
F23
F22
PCIE_PRX_C_DTX_P24
PCIE_PRX_C_DTX_N24
0.22U_0201_6.3V
0.22U_0201_6.3V
L4
TBT_RST#_R
RT1
1
2 0_0201_5%
N16 PCIE_RBIAS
RT3
1 TBT@
2 3.01K_0201_1%
PCIE_PRX_DTX_P21
PCIE_PRX_DTX_N21
19
19
PCIE_PRX_DTX_P22
PCIE_PRX_DTX_N22
19
19
PCIE_PRX_DTX_P23
PCIE_PRX_DTX_N23
19
19
PCIE_PRX_DTX_P24
PCIE_PRX_DTX_N24
19
19
2
2
1 CT109 TBT@
1 CT108 TBT@
2
2
1 CT111 TBT@
1 CT110 TBT@
PLTRST#
+3.3V_TBT_SX
Closed to UT1
N2
N1
L2
L1
J2
J1
W19
Y19
TBT_I2C_SDA
TBT_I2C_SCL
TBT_PCIE_WAKE_N
SIO_SLP_S3#_AR
BATLOW#
TBTA_I2C_INT
TBTB_I2C_INT
NC_B4
TBT_FORCE_PWR_R
RTD3_CIO_PWR_EN_R
RTD3_USB_PWR_EN_R
RT26 2
RT27 2
RT28 2
RT30 2
RT31 2
RT32 2
RT33 2
RT86 2
RT94 2
RT152 2
RT153 2
TBT_CIO_PLUG_EVENT#
RT29 2 TBT@
TBT_SRC_HPD
N6
DPSRC_RBIAS
U1
U2
V1
V2
W1
W2
Y1
Y2
AA1
J4
E2
D4
H4
F2
D2
F1
TBT_EE_WP_N
TBT_TMU_CLK_OUT
TBT_PCIE_WAKE_N
RT10
TBT_CIO_PLUG_EVENT#
TBT_HDMI_DDC_DATA
TBT_HDMI_DDC_CLK
TBT_SRC_CFG1
RT11
TBTA_I2C_INT
TBTB_I2C_INT
RTD3_USB_PWR_EN_R RT12
TBT_FORCE_PWR_R
RT13
BATLOW#
RT14
SIO_SLP_S3#_AR
RT15
RTD3_CIO_PWR_EN_R RT16
E1
TBT_TEST_EN
RT4
1 TBT@
2 1M_0201_1%
RT5
1 TBT@
2 14K_0402_1%
1
@
T2
2 0_0201_5%
1 TBT@
@
T7
@
T9
2 1M_0201_1%
1
1
1
1
1
2
2
2
2
2
e
r
AB5 TBT_TEST_PWG
@
@
@
TBT_I2C_SDA
TBT_I2C_SCL
PCIE_WAKE# 18,26,33,34,35
TBT_CIO_PLUG_EVENT# 20
TBTA_I2C_INT
2 100_0201_5%
2 100_0201_5%
RT23 1 TBT@
2 0_0201_5%
TBT_RESET_N
F4
D22 TBT_XTAL_25_IN
D23 TBT_XTAL_25_OUT
AB3
AC4
AC3
AB4
TBT_RESET_N 40
TBT_RESET_N_EC#
26,40
Metal Shielding Type
TBT_EE_DI
TBT_EE_DO
TBT_EE_CS_N
TBT_EE_CLK
YT1
25MHZ 20PF +-10PPM 7M25000153
TBT_XTAL_25_IN_R
TBT_XTAL_25_OUT_R
B7
A7
1
TBT_XTAL_25_IN
RT154
TBT_XTAL_25_OUT RT155
A11
B11
1TBT@EMI@2 0_0201_5%
1TBT@EMI@2 0_0201_5%
Y16
W16
E19
D19
NC_B4
NC_B5
NC_G2
F19
PB_USB2_RBIAS
1
3
3
1
GND
GND
TBT_M@
2
4
2
2
CT38
27P_0402_50V8J
TBT@
TBT_XTAL_25_IN_R
TBT_XTAL_25_OUT_R
A13
B13
B4
B5
G2
1
CT37
27P_0402_50V8J
TBT@
Reserve for RF immunity
A9
B9
C
From CPU pin AR41
From CPU pin P43
From CPU pin BD13
From EC pin 116
From CPU pin AR44
RTD3_USB_PWR_EN
17
TBT_FORCE_PWR 17
PCH_BATLOW# 18
SIO_SLP_S3# 18,36,37
RTD3_CIO_PWR_EN
17
RT18 1 TBT@
To KB9022
To CPU pin AN43
40
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
RT17 1 TBT@
1 10K_0201_5%
40
40
TBT_TMU_CLK_OUT
TBT_FORCE_PWR_R
RTD3_CIO_PWR_EN_R
RTD3_USB_PWR_EN_R
TBT_RESET_N
RT34
RT35
RT36
RT37
RT80
TBT_RESET_N_EC#
RT129 1
NC_B4
NC_B5
NC_G2
1
1
1
1
1
TBT@
TBT@
TBT@
TBT@
2
2
2
2
2
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
B
2 100K_0201_5%
@
RT45 1 TBT@
RT46 1 TBT@
RT47 1 TBT@
2 100K_0201_5%
2 100K_0201_5%
2 100K_0201_5%
1 TBT@ 2
RT44
499_0201_1%
D6
A23
B23
E18
W13
Close to UT1
W18
TBT_EE_CLK
RT101 1
AB2
2 15_0201_1%
TBT@EMI@
TBT_EE_CLK_R
+3.3V_FLASH
2
1
1
2
RT50 1 TBT@
RT49 1 TBT@
RT48 1 TBT@
2 2.2K_0402_5%
2 2.2K_0402_5%
2 3.3K_0402_5%
TBT_EE_CS_N
TBT_EE_DO
TBT_EE_WP_N
UT2
1
2
3
4
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
8
7
6
5
TBT_HOLD_N 3.3K_0402_5%
TBT_EE_CLK_R
2 TBT@
1 RT51
A
TBT_EE_DI
Compal Electronics, Inc.
Compal Secret Data
2016/01/06
CT45
0.1U_0201_6.3V6K
TBT@
W25Q80DVSSIG_SO8
TBT_M@
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Thunderbolt (1/2)
Size
2
Document Number
R ev
0.3
LA-F611P
Date:
3
3.3K_0201_5%
3.3K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
+3V_PCH_PRIM
G1
Security Classification
Issued Date
1
1
1
1
1
1
1
1
1
1
1
TBT@
TBT@
@
@
TBT@
TBT@
TBT@
@
@
@
@
TBT_EE_CLK_R
Close to UT2
D
17,23,26,33,34,35,48
ALPINE-RIDGE_BGA337
@
4
CLIP2
CLIP_10P2X7P2_SHIELDING_CASE1
EC0XQ000G00
w
e
i
v
R2
R1
@EMI@ @EMI@
r
o
F
A19
B19
PCIE_TX3_P
PCIE_TX3_N
PCIE_REFCLK_100_IN_P
PCIE_REFCLK_100_IN_N
PCIE_CLKREQ_N
E
D
1
1
TBT@ CT43 1
TBT@ CT44 1
40 TBTA_LSTX
40 TBTA_LSRX
40 TBTA_HPD
A17
B17
PCIE_RX3_P
PCIE_RX3_N
PCIE_TX2_P
PCIE_TX2_N
0.22U_0201_6.3V
0.22U_0201_6.3V
CT157
RT157
33P_0402_50V8J
33_0402_5%
5
Y4
V4
T4
W4
TBT@ CT39 1
TBT@ CT40 1
100K_0804_8P4R_5%
A
TBT_TDI
TBT_TMS
TBT_TCK
TBT_TDO
TBT_A_TTX_C_DRX_P1
TBT_A_TTX_C_DRX_N1
TBT@
RPT1 8
7
6
5
1
1
Y18
40
40
40
40
B
RT159
RT160
TBT_A_TRX_DTX_P1
TBT_A_TRX_DTX_N1
DPSNK_RBIAS
PCIE_RX2_P
PCIE_RX2_N
PCIE_TX1_P
PCIE_TX1_N
V23 PCIE_PRX_C_DTX_P21
V22 PCIE_PRX_C_DTX_N21
2 1
S IC JHL6340 SLLSP C1 THUNDERBOLT A31!
SA00009YL3L
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
PCIE_RX1_P
PCIE_RX1_N
POC
17
17
17
TBT@ CT4 1
TBT@ CT18 1
PCIe GEN3
PEG CLK
(From PCH CLKOUT0)
T23
T22
PCIE_PTX_C_DRX_P23
PCIE_PTX_C_CRX_N23
SOURCE PORT 0
UT1
PCIE_PTX_C_DRX_P22
PCIE_PTX_C_DRX_N22
LC GPIO
PCIE_PTX_DRX_P24
PCIE_PTX_DRX_N24
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
PCIE_TX0_P
PCIE_TX0_N
POC GPIO
19
19
D
TBT@ CT1 1
TBT@ CT13 1
PCIE_RX0_P
PCIE_RX0_N
Misc
PCIE_PTX_DRX_P23
PCIE_PTX_DRX_N23
Y23
Y22
PORT B
19
19
PCIE_PTX_C_DRX_P21
PCIE_PTX_C_DRX_N21
SINK PORT 0
PCIE_PTX_DRX_P22
PCIE_PTX_DRX_N22
2 0.22U_0201_6.3V
2 0.22U_0201_6.3V
SINK PORT 1
19
19
UT1A
TBT@ CT3 1
TBT@ CT15 1
Port A
PCIE_PTX_DRX_P21
PCIE_PTX_DRX_N21
TBT PORTS
PCIE X4 Bus
19
19
POC
Update OK
Thursday, March 22, 2018
Sheet
1
41
of
78
5
4
3
2
1
Main Func = Thunderbolt
Delete RT52 for layout @12/31
VCC3V3_S0
VCC3P3A
VCC3P3_S0
H9
R13
F8
VCC3P3_SX
VCC3P3_LC
2
CT53
TBT@
1
2
TBT@
A2
A3
B3
1
TBT@
2
CT64
1
TBT@
2
CT65
1
TBT@
2
V5
V6
V8
V9
V15
V16
V20
W5
W6
W8
W9
W20
W22
W23
Y9
Y13
Y20
AA22
AA23
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
D5
E4
E5
E6
F5
F6
H5
H8
J8
J12
J13
J15
L13
M11
M12
N8
N9
N11
N12
N13
T6
T8
T9
T13
T15
T16
T18
AB1
AC2
TBT@
CT81
TBT@
L
L
1
2
1
1
CT68
TBT@
2
CT69
TBT@
2
1
TBT@
1
TBT@
2
1
2
CT155
TBT@
1
2
D
e
r
CT73
+0.9V_LVR_OUT
1
1
CT67
TBT@
2
LT1 TBT_M@
TBT_SVR_IND 1
2
0.6UH_MND-04ABIR60M-XGL_20%
A1
B1
B2
F18
H18
J11
H11
1
CT66
2
CT154
47U_0603_6.3V6M
C1
C2
D1
+0.9V_SVR
CT63
1
1U_0201_6.3V6M
L9
M9
E12
E13
F11
F12
F13
F15
J9
+3VS_TBT
LT4 MAIN@
1
2
1UH_LQM18PN1R0MFHD_20%
w
e
i
v
CT153
1U_0201_6.3V6M
VCC
1
47U_0603_6.3V6M
TBT@
CT82
TBT@
1
2
2
CT83
TBT@
CT74
TBT@
1
2
2
CT84
TBT@
CT75
TBT@
1
2
1U_0201_6.3V6M
@
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
CT52
47U_0603_6.3V6M
TBT@
2
E
D
B
r
o
F
CT86
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
1
1U_0201_6.3V6M
TBT@
2
1
A6
A8
A10
A12
A14
A16
A18
A20
A22
B6
B8
B10
B12
B14
B16
B18
B20
B22
D8
D9
D11
D12
D13
D15
D16
D18
E8
E9
E11
E15
E16
E22
E23
F9
F16
F20
G22
G23
H1
H2
H12
H13
H15
H16
H20
J5
J18
J19
J20
J22
J23
K1
K2
L5
L20
L22
L23
M1
M2
M5
M19
M20
N5
N20
N22
N23
VCC0P9_LVR
VCC0P9_LVR
VCC0P9_LVR
VCC0P9_LVR_SENSE
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2
TBT@
1U_0201_6.3V6M
1
L16
J16
SVR_VSS
SVR_VSS
SVR_VSS
2
CT51
47U_0603_6.3V6M
TBT@
2
+3.3V_ANA_PCIE
+3.3V_ANA_USB2
1U_0201_6.3V6M
TBT@
2
1
VCC0P9_SVR
VCC0P9_SVR
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_SENSE
1
1U_0201_6.3V6M
CT80
VCC3P3_SVR
VCC3P3_SVR
VCC3P3_SVR
SVR_IND
SVR_IND
SVR_IND
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
TBT@
10U_0402_6.3V6M
1
VCC0P9_USB
VCC0P9_USB
CT50
1U_0201_6.3V6M
CT79
CT85
5
1
TBT@
2
R8
R9
R11
R12
1U_0201_6.3V6M
TBT@
2
A
CT72
VCC0P9_PCIE
VCC0P9_PCIE
VCC0P9_PCIE
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
1
TBT@
2
10U_0402_6.3V6M
1
1U_0201_6.3V6M
CT78
C
1
TBT@
2
2
+0.9V_CIO
1U_0201_6.3V6M
TBT@
2
CT71
TBT@
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSNK
VCC0P9_ANA_DPSNK
VCC0P9_ANA_DPSNK
CT49
1U_0201_6.3V6M
1
1U_0201_6.3V6M
TBT@
2
CT56
TBT@
2
M13
M15
M16
L19
N19
L18
M18
N18
2
R15
R16
1U_0201_6.3V6M
1
1U_0201_6.3V6M
CT77
1
CT70
+0.9V_PCIE
TBT@
1U_0201_6.3V6M
+0.9V_USB
2
1U_0201_6.3V6M
TBT@
2
1U_0201_6.3V6M
1
CT55
TBT@
CT62
1
TBT@
2
1U_0201_6.3V6M
2
CT61
1
1U_0201_6.3V6M
TBT@
1U_0201_6.3V6M
2
CT60
L8
L11
L12
M8
T11
T12
L6
M6
V11
V12
V13
1
1U_0201_6.3V6M
TBT@
CT59
1
1U_0201_6.3V6M
2
CT58
1
1U_0201_6.3V6M
TBT@
1
1U_0201_6.3V6M
2
CT57
1U_0201_6.3V6M
TBT@
1U_0201_6.3V6M
CT54
1
CT48
47U_0603_6.3V6M
UT1B
1
TBT@
2
1U_0201_6.3V6M
+0.9V_DP
1
CT47
10U_0402_6.3V6M
1
TBT@
2
10U_0402_6.3V6M
CT46
10U_0402_6.3V6M
2 0_0402_5%
D
10U_0402_6.3V6M
@
+3VS_TBT
VCC3V3_S0
+3VS
RT168
+3.3V_TBT_SX
1U_0201_6.3V6M
1
+3.3V_LC
1U_0201_6.3V6M
2 0_0402_5%
1U_0201_6.3V6M
RT97
@
0.1U_0201_6.3V6K
2
0_0402_5%
@
+3VS_TBT
RT95 1
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
1
+3VALW
GND
+3.3V_TBT_SX
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
+3VALW
R6
Delete RT104 for layout @12/31
2
C
B
ALPINE-RIDGE_BGA337
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Thunderbolt (2/2)
Size
4
3
2
Document Number
R ev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
42
of
78
5
4
3
2
1
Main Func = Retimer
CP29
1
2
ADJ
VDD
PGOOD
EN
GND
PGND
1
RP30
4.99K_0402_1%
PS8409@
3
4
9
1
1U_0603_6.3V6M
PS8409@
CP28
1
NC
RP31
10K_0402_1%
PS8409@
RT9041E-15GQW_WDFN8_2X2
PS8409@
+3V_RTM
+3VS
1
w
e
i
v
@
RP28
0_0603_1%
2
6
30
11
43
46
15
18
37
49
49
+1.2V_RTM
+1.2V_RTM_IN
IFPC_TX2_P
IFPC_TX2_N
IFPC_TX1_P
IFPC_TX1_N
49
49
IFPC_TX0_P
IFPC_TX0_N
49
49
IFPC_CLK_P
IFPC_CLK_N
CP15 1
CP16 1
CP17 1
CP18 1
2
2
2
2
[email protected]_0201_6.3V6K
[email protected]_0201_6.3V6K
IFPC_TX2_CP
IFPC_TX2_CN
[email protected]_0201_6.3V6K
[email protected]_0201_6.3V6K
IFPC_TX1_CP
IFPC_TX1_CN
2
2
[email protected]_0201_6.3V6K
[email protected]_0201_6.3V6K
CP21 1
CP22 1
2
2
[email protected]_0201_6.3V6K
[email protected]_0201_6.3V6K
IFPC_CLK_CP
IFPC_CLK_CN
47
48
RTM_DCIN_ENB
RTM_EQ
RTM_I2C_ADDR
3
5
31
CP14
2
RP32
4.53K_0402_1%
PS8409@
1
2
+3V_RTM
RP33
RP34
RP35
RP36
RP37
1
1
1
1
1
2
2
2
2
2
PS8409@ RP38
1
2 10K_0201_5%
1
1
1
1
1
1
2
2
2
2
2
2
@PS8409@
@PS8409@
@PS8409@
@PS8409@
@PS8409@
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
RTM_DCIN_ENB
RTM_EQ
RTM_I2C_ADDR
RTM_PRE
RTM_HDMI_ID
B
A
PS8409@
@PS8409@
@PS8409@
@PS8409@
@PS8409@
@PS8409@
RP39
RP40
RP41
RP42
RP43
RP44
5
RTM_RST#
r
o
F
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
44
45
10
25
26
1
Close Pin 15,18
1
2
CP13
2
PS8409@
CP27
1U_0402_6.3V6K
0.1U_0201_6.3V6K
1
41
42
CP19 1
CP20 1
PS8409@
CP12
2
PS8409@
1
0.01U_0402_16V7K
RP52
0_0603_1%
38
39
IFPC_TX0_CP
IFPC_TX0_CN
1
0.1U_0201_6.3V6K
@
PS8409@
2
RTM_PDB
RTM_RST#
RTM_PRE
36
4
35
27
2
VDD12
VDD12
VDDA12
VDDRX12
VDDRX12
VDDTX12
VDDTX12
POWERSWITCH
IN_D2p
IN_D2n
IN_D1p
IN_D1n
IN_D0p
IN_D0n
IN_CLKp
IN_CLKn
DCIN_ENB
EQ
I2C_ADDR
RSV1
NC
RSV2
VDD33
VDD33
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
OUT_D0p
OUT_D0n
OUT_CLKp
OUT_CLKn
SDA_SRC/AUXN
SCL_SRC/AUXP
SDA_SNK
SCL_SNK
1
24
23
22
20
19
17
16
14
13
33
34
8
7
IFPC_I2C_8409_DAT
IFPC_I2C_8409_CLK
44
44
HDMI_TX_P1
HDMI_TX_N1
44
44
HDMI_TX_P0
HDMI_TX_N0
44
44
HDMI_CLKP
HDMI_CLKN
44
44
HDMI_ID
HDMI_CEC
CEC_EN
REXT
PDB
RESETB
PRE
TESTMODEB
CSCL
CSDA
EPAD
40
21
PS8409@ RP45 1
2 1K_0201_5%
RTM_HDMI_ID
1
2 0_0201_5%
32
9
12
RP11
29
28
RTM_CSCL
RTM_CSDA
HDMI_CLKP
HDMI_CLKN
IFPC_I2C_8409_DAT
49
IFPC_I2C_8409_CLK
49
HDMI_CTRL_DAT
44,49
HDMI_CTRL_CLK
44,49
L
L
HPD_SRC
HPD_SNK
e
r
HDMI_TX_P2
HDMI_TX_N2
PS8409@
PS8409@
0.1U_0201_6.3V6K
Close Pin 24
UP2
49
49
C
CP25
2
+3V_RTM
1
1
CP23
2
CP26
2
Close Pin 1
0.1U_0201_6.3V6K
2
+3V_RTM
@PS8409@
Close Pin 6,11
+1.2V_RTM
CP11
0.1U_0201_6.3V6K
Close Pin 43,46
1
PS8409@
2
PS8409@
CP10
0.01U_0402_16V7K
2
1
0.1U_0201_6.3V6K
CP9
PS8409@
2
1
0.1U_0201_6.3V6K
CP8
PS8409@
2
1
4.7U_0603_6.3V6K
PS8409@
2
CP7
PS8409@
1
CP6
0.01U_0402_16V7K
PS8409@
0.1U_0201_6.3V6K
2
1
0.1U_0201_6.3V6K
CP5
1
CP24
2
0.01U_0402_16V7K
+1.2V_RTM
1
1
D
+3V_RTM
PS8409@
+1.2V_RTM
2
Close Pin 30
10U_0603_6.3V6M
PS8409@
PS8409@
0.01U_0402_16V7K
2
0.1U_0201_6.3V6K
2
D
5
CP4
PS8409@
1
CP3
2
CP32
1
6
+5VALW
1
1
2
1
@
VOUT
2
2
VIN
2
7
RP51
0_0603_1%
+1.2V_RTM_IN
UP1
8
10U_0603_6.3V6M
PS8409@
+3VS
+1.2V_RTM
+1.2V_RTM_IN
GPU_HPD_RT
48
HDMI_HPD
44
HDMI_CEC
44
+3V_RTM
IFPC_I2C_8409_DAT
IFPC_I2C_8409_CLK
RP24
@PS8409@
@PS8409@
1
1
2 47K_0402_5%
2 47K_0402_5%
RP25
RTM_CSCL
RTM_CSDA
@PS8409@
@PS8409@
RP48 1
RP49 1
2 10K_0201_5%
2 10K_0201_5%
49
PS8409AQFN48GTR2-A2_QFN48_6X6
PS8409@
E
D
B
RTM_DCIN_ENB
RTM_EQ
RTM_I2C_ADDR
RTM_PRE
RTM_HDMI_ID
RTM_PDB
4
C
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Re-Timer 8409A
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
43
of
78
5
4
3
2
1
Main Func = HDMI
HDMI conn
Place close to JHDMI1
43
43
HDMI_TX_N1
HDMI_TX_P1
HDMI_TX_N1
1 EMI@ 2
RV642
2.2_0402_1%
LV5
@EMI@
4
3
HDMI_TX_P1
1
43
HDMI_TX_N2
43
HDMI_TX_P2
HDMI_TX_N2
1 EMI@ 2
RV645
2.2_0402_1%
LV6
@EMI@
4
3
HDMI_TX_P2
1
1
1
5
HDMI_L_TX_P1
HDMI_L_TX_N2
HDMI_L_TX_N1
RV30
0_0402_5%
2
@
@ CV599
1
2 0.1U_0402_25V6
HDMI_HPD
@ CV600
1
2 0.1U_0402_25V6
HDMI_Reserved
@ CV601
1
2 0.1U_0402_25V6
HDMI_CEC
HDMI_L_TX_P1
RV33
0_0402_5%
2
@
HDMI_L_TX_N2
1
RV34
0_0402_5%
2
@
HDMI_L_TX_P2
e
r
20
L
L
23
22
21
20
ACON_HMRBL-AK120D
CONN@
For EMI Reserve
HDMI_L_TX_P0
D
+3VS
C
2
QX3
MMBT3904W H_SOT323-3
1
HDMI_HPD
2
B
E
RX6
150K_0402_5%
1
HDMI_HPD_PCH
2
C
CX2
0.1U_0402_16V7K
RX8
100K_0402_5%
E
D
B
A
HDMI_L_TX_P0
HDMI_L_TX_N1
MAIN@
1
RV503
619_0402_1%
@EMI@
r
o
F
HDMI_CEC
HDMI_L_CLKP
HDMI_L_TX_N0
Close to JHDMI
RV502
619_0402_1%
@EMI@
2
HCM1012GH900BP_4P
1 EMI@ 2
RV638
2.2_0402_1%
RV28
0_0402_5%
1
2
@
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Utility
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND1
D2GND2
D2_shield GND3
D2+
GND4
w
e
i
v
43
HDMI_L_TX_P2
RV29
0_0402_5%
1
2
@
2
HCM1012GH900BP_4P
1 EMI@ 2
RV639
2.2_0402_1%
C
RV501
619_0402_1%
@EMI@
2
HCM1012GH900BP_4P
1 EMI@ 2
RV646
2.2_0402_1%
SA00004ZA00
HDMI_CTRL_DAT
HDMI_CTRL_CLK
HDMI_Reserved
HDMI_CEC
HDMI_L_CLKN
HDMI_CTRL_DAT
HDMI_CTRL_CLK
1
1
2
43,49
43,49
3
HDMI_TX_P0
HDMI_L_TX_N0
2
1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
HDMI_TX_P0
1
43
AP2330W -7_SC59-3
2
2
HDMI_TX_N0
HDMI_L_CLKP
RV674
0_0402_5%
1
2
@
1
43
1 EMI@ 2
RV643
2.2_0402_1%
LV4
@EMI@
4
3
GND
RV675
0_0402_5%
1
2
@
1
IN
JHDMI1
HDMI_HPD
HDMI_HPD
2
HCM1012GH900BP_4P
1 EMI@ 2
RV640
2.2_0402_1%
HDMI_TX_N0
RV500
619_0402_1%
@EMI@
2
43
3
2
1
2
HDMI_CLKP
W=40mils
OUT
2
HDMI_CLKP
UV17
HDMI_L_CLKN
1
1
43
HDMI_CLKN
RV673
0_0402_5%
2
@
CV597
10U_0603_6.3V6M
HDMI_CLKN
1
CV598
0.1U_0402_10V6K
43
D
1 EMI@ 2
RV641
2.2_0402_1%
LV3
@EMI@
4
3
+VDISPLAY_VCC
+5VS
B
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
HDMI
Size
3
2
Rev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
44
of
78
5
4
3
2
1
Main Func = 2nd source list
F1
2ND@
UH14
2ND@
UZ21
2ND@
SP040001G00
S FUSE 1812L150/24MR 1.5A 24V UL/TUV
UG25
2ND@
UG27
SA007080120
SA007080120
S IC TC7SH08FU SSOP 5P AND
S IC TC7SH08FU SSOP 5P AND
2ND@
U2
SA00001OF00
SA00001OF00
S IC TC7SZ32FU SSOP 5P OR 0.65A
S IC TC7SZ32FU SSOP 5P OR 0.65A
TL1
2ND@
2ND@
SA007810140
UG22
2ND@
UG31
2ND@
UV14
2ND@
UV19
2ND@
UV20
2ND@
S IC G781P8F MSOP 8P TEMP. SENSOR
SP050006P00
Q6
2ND@
Q9
2ND@
Q22
2ND@
QA1
w
e
i
v
2ND@
S X'FORM_ IH-115-F LAN
SA00001DG90
SA00001DG90
SA00001DG90
SA00001DG90
SA00001DG90
S IC TC7SZ08FU SSOP 5P AND
S IC TC7SZ08FU SSOP 5P AND
S IC TC7SZ08FU SSOP 5P AND
S IC TC7SZ08FU SSOP 5P AND
S IC TC7SZ08FU SSOP 5P AND
CD27
2ND@
D
UE2
2ND@
D
SB00000QM00
SB00000QM00
SB00000QM00
SB00000QM00
S TR AP2324GN-HF 1N SOT-23-3
S TR AP2324GN-HF 1N SOT-23-3
S TR AP2324GN-HF 1N SOT-23-3
S TR AP2324GN-HF 1N SOT-23-3
SGA00002680
S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9
F3
DU1
SA00004H300
ESD_2@
DU3
KBBL_2@
ESD_2@
S IC TC7SZ05FU SSOP 5P INVERTER OD
UV17
2ND@
SC300001Y00
SC300001Y00
AZ1045-04F
AZ1045-04F
DA5
SA000080300
SP040006R00
S FUSE 1206L050/15YR 0.5A 15V UL/TUV
ESD_2@
S IC G5250Q1T73U SOT-23 3P POWER SWITCH
QV3
N17P_2@
QV20
N17P_2@
QV21
N17P_2@
SCA00003400
UG12
S ZEN ROW L18E3V3CC3-2C 3P C/A SOT-23
SB00000S700
SB00000S700
SB00000S700
DA4
S TR MESS138W-G 1N SOT323-3
S TR MESS138W-G 1N SOT323-3
S TR MESS138W-G 1N SOT323-3
Q23
Q24
ESD_2@
DA7
ESD_2@
2ND@
SCA00002M00
SCA00002M00
MESC5V02BD03
MESC5V02BD03
RA13
SA00007QK00
EMI_2@
RA14
EMI_2@
RA15
EMI_2@
RA16
UZ16
2ND@
2ND@
EMI_2@
S IC G5016KD1U TDFN2X3 14P LOAD SWITCH
SB00000EN00
SB00000EN00
S TR 2N7002K 1N SOT23-3 PANJIT
S TR 2N7002K 1N SOT23-3 PANJIT
2ND@
SM01000NX00
SM01000NX00
SM01000NX00
SM01000NX00
Q26
GEN9_2@
S SUPPRE_ TAI-TECH HCB1005KF-800T20 0402 S SUPPRE_ TAI-TECH HCB1005KF-800T20 0402 S SUPPRE_ TAI-TECH HCB1005KF-800T20 0402S SUPPRE_ TAI-TECH HCB1005KF-800T20 0402
L5
SA00009PI00
EMI_2@
S IC FA7607OTR DFN 8P LOAD SWITCH
UZ7
SB00000T900
GEN9_2@
S TR PJ2301 1P SOT23-3
SM01000Q500
QH4
2ND@
S SUPPRE_ TAI-TECH HCB1005KF-221T15 0402
SA00009PI00
LA1
ESD_2@
LA2
ESD_2@
LA3
ESD_2@
LA4
ESD_2@
S IC FA7607OTR DFN 8P LOAD SWITCH
SB00000PV00
U1
2ND@
UL2
2ND@
S TR L2N7002DW1T1G 2N SC88-6
SM01000OZ00
SM01000OZ00
SM01000OZ00
SM01000OZ00
QG23
N17P_2@
S SUPPRE_ TAI-TECH HCB1005PF-330T30 0402 S SUPPRE_ TAI-TECH HCB1005PF-330T30 0402 S SUPPRE_ TAI-TECH HCB1005PF-330T30 0402 S SUPPRE_ TAI-TECH HCB1005PF-330T30 0402
SA00008R900
SA00008R900
S IC EM5203AJ-20 SOT23 5P LOAD SWITCH
S IC EM5203AJ-20 SOT23 5P LOAD SWITCH
L3
EMI_2@
LU1
EMI_2@
LU4
EMI_2@
LU8
EMI_2@
LU9
EMI_2@
SB00001FN00
S TR LBSS139DW1T1G 2N SOT-363-6 ESD
UU1
2ND@
UU3
2ND@
SM070004400
SM070004400
SM070004400
SM070004400
SM070004400
S COM FI_ PANASONIC EXC24CQ900U
S COM FI_ PANASONIC EXC24CQ900U
S COM FI_ PANASONIC EXC24CQ900U
S COM FI_ PANASONIC EXC24CQ900U
S SUPPRE_ TAI-TECH HCB1005KF-221T15 0402
LT2
LT3
DT10
C
SA00008RA00
SA00008RA00
S IC EM5203J-20 SOT23 5P LOAD SWITCH
S IC EM5203J-20 SOT23 5P LOAD SWITCH
UZ1
2ND@
TBT@EMI_2@
SM070004400
SM070004400
S COM FI_ PANASONIC EXC24CQ900U
S COM FI_ PANASONIC EXC24CQ900U
Q7
Q18
2ND@
TBT@ESD_2@
DT11
TBT@ESD_2@
TBT@EMI_2@
2ND@
Q19
SC300002C00
S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD
S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD
2ND@
LV7
SA00007QK00
N17P_2@
LV13
N17P_2@
S IC G5016KD1U TDFN2X3 14P LOAD SWITCH
UC10
2ND@
UC16
2ND@
SB00001H300
SB00001H300
SB00001H300
S TR LDTA144VLT1G PNP SOT23-3
S TR LDTA144VLT1G PNP SOT23-3
S TR LDTA144VLT1G PNP SOT23-3
D6
SA00005U600
S IC 74AUP1G07GW TSSOP 5P BUFFER
S IC 74AUP1G07GW TSSOP 5P BUFFER
2ND@
UZ15
S SUPPRE_ TAI-TECH HCB1005KF-300T25 0402
XTAL_2@
CH47
XTAL_2@
CH48
YH2 CH47 CH48 2nd X76 control
2ND@
X7676731L78
S SCH DIO LRB551V-30T1G SOD323-2
SJ10000YS00
SE071120J80
S CRYSTAL 24MHZ 12PF X3S024000BC1H-HU
S CER CAP 12P 50V J NPO 0402
UT2
SA00008A800
SA00008A800
S IC AOZ1334DI-01 DFN 8P SINGLE LOAD SW
S IC AOZ1334DI-01 DFN 8P SINGLE LOAD SW
UH3
SM01000NV00
S SUPPRE_ TAI-TECH HCB1005KF-300T25 0402
L
L
2ND@
SCS00007H00
UZ9
SM01000NV00
YH2
SA00005U600
2ND@
S IC FL 8M MX25L8006EM2I-12G SOP 8P 3V
QG10
S IC SN74AHC1G08DCKR SC-70 5P AND
DU2
ESD_2@
DU4
ESD_2@
C
XTAL_2@
SE071120J80
TBT_2@
SA000041O00
SA007080180
e
r
SC300002C00
S CER CAP 12P 50V J NPO 0402
N17P_2@
SB00001GC00
S TR LBSS139WT1G 1N SC70-3
DT2
SCA00001L00
S ZEN ROW L30ESDL5V0C3-2 C/A SOT23 ESD
S ZEN ROW L30ESDL5V0C3-2 C/A SOT23 ESD
Q1
Q13
2ND@
TBT@ESD_2@
DT3
TBT@ESD_2@
DT4
TBT@ESD_2@
2ND@
SB00000M700
SB00000M700
S TR ME2N7002D-G 1N SOT-23-3 ESD 2KV
S TR ME2N7002D-G 1N SOT-23-3 ESD 2KV
DT6
TBT@ESD_2@
DT7
TBT@ESD_2@DT8
TBT@ESD_2@
DT9
TBT@ESD_2@
SC40000DM00
SC40000DM00
SC40000DM00
SC40000DM00
SC40000DM00
SC40000DM00
SC40000DM00
PESD5V0C1BSF
PESD5V0C1BSF
PESD5V0C1BSF
PESD5V0C1BSF
PESD5V0C1BSF
PESD5V0C1BSF
PESD5V0C1BSF
PESD5V0C1BSF
QV10
2ND@
TP_WAKE_2@
SB000013D00
S TR BSS138PS 2N SC88-6
SB00000PJ00
QG502
2ND@
QG503
2ND@
QG504
2ND@
S TR DMG2301U-7 1P SOT23-3
Q14
TBT@ESD_2@
SC40000DM00
B
Q12
DT5
DT16
SCA00001L00
2ND@
SB00001DD00
SB00001DD00
SB00001DD00
E
D
QG505
2ND@
SB00001DD00
S TR PJT138K 2N SOT363-6 S TR PJT138K 2N SOT363-6 S TR PJT138K 2N SOT363-6 S TR PJT138K 2N SOT363-6
SB000006A00
S TR MMBT3904 NPN SOT23-3 T/R-3K
QV1
N17P_2@
SB00001DD00
S TR PJT138K 2N SOT363-6
D1
2ND@
SCS00009E00
S SCH DIO LBAS40-05LT1G SOT23
YV1
N17P_2@
TBT_2@
SH00001BK00
S CRYSTAL 27MHZ 10PF X3G027000BA1H-U
Q25
r
o
F
LT1
SJ10000B300
S COIL 0.6UH TMPC404012HB-R60MG-Z02 6.6A
GEN9_2@
LT4
SB00000UO00
2ND@
SHI0000NV00
DMN65D8LW-7 1N SOT323-3
S INDUC_ 1UH +-20% CPI160809UF-1R0M-0A7
D7
GEN9_2@
DC2
GEN9_2@
DV9
N17P_2@
DV11
N17P_2@
LG8
SCS00008100
SCS00008100
SCS00008100
S SCH DIO LRB521S-40T1G SOD523-2 S SCH DIO LRB521S-40T1G SOD523-2
SCS00008100
N17P_2@
ESD_2@
SCA00000R00
S ZEN ROW PESD24VS2UT 3P C/A SOT23
DA8
2ND@
SCS00009K00
S SCH DIO BAT54AT-7-F SOT-523
YH1
XTAL_2@
CH45
XTAL_2@
CH46
XTAL_2@
B
YH1 CH45 CH46 2nd X76 control
X7676731L92
SJ10000SX00
SE07168AC80
SE07168AC80
S CRYSTAL 32.768KHZ 9PF EXS00A-MU00688
S CER CAP 6.8P 50V C NPO 0402
S CER CAP 6.8P 50V C NPO 0402
YT1
TBT_2@
SJ10000U200
S CRYSTAL 25MHZ 20PF X3S025000BK1H-CHV
UH15
2ND@
SA0000A8J10
S IC FL 128M GD25B127DSIGR SOP 8P SPI
UT3
PD_2@
SA00007XO10
S IC FL 2M GD25Q20CTIGR SOP 8P SPI ROM
SM01000HU00
S SCH DIO LRB521S-40T1G SOD523-2 S SCH DIO LRB521S-40T1G SOD523-2
S SUPPRE_ TAI-TECH HCB1608KF-300T20 0603
DE7
A
2ND@
SCS00008100
DE9
2ND@
SCS00008100
DG3
2ND@
DG4
SCS00008100
2ND@
SCS00008100
DG7
2ND@
A
SCS00008100
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
DG10
2ND@
SCS00008100
DH2
2ND@
SCS00008100
DN1
2ND@
DN2
SCS00008100
2ND@
SCS00008100
DZ1
2ND@
SCS00008100
DZ2
2ND@
SCS00008100
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
S SCH DIO LRB521S-40T1G SOD523-2
YL1
2ND@
SJ10000DE00
S CRYSTAL 25MHZ 10PF X3G025000DA1H-X
YE1
2ND@
SJ10000SX00
S CRYSTAL 32.768KHZ 9PF EXS00A-MU00688
5
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
Title
2nd source list
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Si ze
2
Document
Number
Rev
0.3
LA-F611P
Dat
Date:
e:
3
1
Thursday, March 22, 2018
Sheet
45
of
78
5
4
3
2
CPU
1
+VCC_CORE
VCC
+1.0VS_VCCIO
VCCIO
+VCC_GT
VCCGT
VCCGTX
Timing Diagram for S5 to S0 mode
+1.2V_DDR +1.2V_VCCSFR_OC
VDDQ
VDDQC
VCCPLL_OC
(Loki)
w
e
i
v
+1.0V_VCCST
D
8d
DDR_VTT_CNTL
+VCC_SA
VCCSA
+1.0VS_VCCOPC
VCCOPC
+1.8V_PRIM
VCC_OPC_1P8
+1.0VS_VCCOPC
VCCEOPIO
SKYLAKE-U 2+3e only
1a +RTC_CELL
ADAPTER
1b
PCH
+RTC_CELL_PCH
VCCRTC
(Loki)
VCCPRIM_1P0
DCPDSW _1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~6
+1.0V_MPHYGT
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
+1.0V_PRIM
C
EXT_PWR_GATE#
+3VALW
3
+19VB
SY8180
Power Button
VCCDSW _3P3
VL
+5VALW
3
2
EN_3V
SY8286
+3VLP
+3VALW
RT6228
+1.0V_PRIM
RT8061
2a
SIO_SLP_SUS#
RUNPW ROK
ALL_SYS_PW RGD
10b
5
11
RESET_OUT#
12
SYS_PWROK
PCH_RSMRST#
r
o
F
+3VALW
EM5209
5a
+1.0V_PRIM
VCCPRIM_CORE
13
E
D
PRIM_PW RGD
A
+1.8V_PRIM
PRIM_PW RGD
SIO_PW RBTN#
VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
VCCPGPPG
VCCATS
+3VALW
EC 1416
+3VALW_PCH
+1.8V_PRIM
POK
POK
+3.3V_SPI
L
L
+19VB
+19VB
6b
PCH_PW ROK
RESET_OUT#
11
e
r
SYS_PWROK
12
SYS_PWROK
+3VALW_PCH
4
PCH_PLTRST#
PWRBTN#
SLP_S5#
SLP_S4#
+VCC_SA
+VCC_CORE
+VCC_GT
6b
SIO_PW RBTN#
SIO_SLP_S5#
7
8a
SIO_SLP_S4#
+1.0V_PRIM
TPS22967
+1.0V_VCCST
8b
+3VALW
PLTRST#
RT9059GSP
+2.5V_MEM
B
+19VB
8d
+1.2V_DDR
VDDQ
+0.6V_DDR_VTT
VTT
RT8207
DDR4
0.6V_DDR_VTT_ON
PGOOD
8c
1.2V_VTT_PW RGD
+5VALW
SLP_S3#
9a
SIO_SLP_S3#
+5VS
EM5209VF
+3VS
+3VALW
+1.0V_PRIM
AND
SLP_S0#
TPS22961
+1.0V_VCCSTG
+1.0VS_VCCIO
9b
A
+3VALW
EM5209
Issued Date
+1.2V_VCCSFR_OC
(Loki)
+1.2V_DDR
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
POWER SEQUENCE
Size
Document Number
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Rev
0.3
LA-F611P
Date:
4
C
+PWR_SRC
IMVP_VR_ON
NCP81218
EN_5V
4
5b
10a
+3.3V_ALW_DSW
2
B
PCH_DPW ROK_R
+1.0V_PRIM
+19VB
BATTERY
6a
PCH_RSMRST#_Q
RSMRST#
DSW_PWROK
D
+1.0V_VCCSTG
VCCST
VCCPLL
VCCSTG
0.6V_DDR_VTT_ON
Thursday, March 22, 2018
1
Sheet
46
of
78
5
4
3
2
1
Main Func = Screw hole
w
e
i
v
Screw hole/FD
D
H_3P5X3P0N
1
H_4P0
1
H_7P0
1
H_4P0
1
H_2P3
HGPU4
HOLEA
H_3P7
H_3P7
H_3P7
H_3P7
H_3P7
H_3P7
H_3P7
H_3P7
FD1
FD2
FD3
FD4
FD5
1
H_4P0
H16
HOLEA
1
H_4P0-G
H15
HOLEA
1
H_4P0-G
H14
HOLEA
1
H_4P0-G
HGPU3
HOLEA
1
H13
HOLEA
HGPU2
HOLEA
1
H12
HOLEA
HGPU1
HOLEA
1
H11
HOLEA
HCPU4
HOLEA
1
H10
HOLEA
HCPU3
HOLEA
1
H9
HOLEA
HCPU2
HOLEA
1
H8
HOLEA
HCPU1
HOLEA
GPU
1
H_3P0X3P3
CPU
1
H_4P0
1
H_3P2
1
H_3P0
1
H_5P6N
1
H_3P3
1
H_3P7-G
1
1
H7
HOLEA
1
H6
HOLEA
1
H5
HOLEA
1
H4
HOLEA
1
H3
HOLEA
1
H2
HOLEA
1
H1
HOLEA
C
L
L
A
5
e
r
C
E
D
B
r
o
F
D
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Reserved
Size
Date:
4
3
2
Document Number
LA-F611P
Thursday, March 22, 2018
1
Re v
0.3
Sheet
47
of
78
4
PEG_CRX_C_GTX_P5
PEG_CRX_C_GTX_N5
PEG_CRX_GTX_P6
PEG_CRX_GTX_N6
CV543
CV544
2
2
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
PEG_CRX_C_GTX_P6
PEG_CRX_C_GTX_N6
2
2
CV545
CV546
PEG_CRX_C_GTX_P7
PEG_CRX_C_GTX_N7
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
+1V8_AON
5
1
OUT Y
4
0_0201_5%
RV56
UV19
NL17SZ08DFT2G_SC70-5
2 1
SA00003R000
MAIN@
CLKREQ_PCIE#7
1
3
PEX_CLKREQ#
S
CLKREQ_PCIE#7
RV57
10K_0402_5%
D
17,48
+1V8_AON
2
IN A
1
DGPU_PWROK 2
ALL_GPWRGD
2
DGPU_PWROK
IN B
G
18,48,56,76
NVVDD1_PGOOD1
VCC
NVVDD1_PGOOD
3
56,72
GND
C
CV530
0.1U_0201_6.3V6K
2
BSS138W 1N SOT-323-3
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
QV3
N17P_M@
AJ11
DGPU_PWROK
CLKREQ_PCIE#7
CLK_PCIE_P7
CLK_PCIE_N7
18,48,56,76
DGPU_PWROK
17,48 CLKREQ_PCIE#7
17,48 CLK_PCIE_P7
17,48 CLK_PCIE_N7
17,48
17,48
DGPU_PEX_RST#
1
0_0201_5%
1
RV50
2
RV40
DGPU_PEX_RST#_R
PEX_TERMP
1
CV212
0.1U_0201_6.3V6K
2
@
IN A
RV572
1
2 0_0402_5%
DGPU_PEX_RST#
RV571
1 @
2 0_0402_5%
VGA_SMB_CK2
4
2
A
VGA_SMB_DA2
1
3
+1V8_AON
2
QV1B N17P_M@
DMN53D0LDW-7 2N SOT363-6
SB000018X00
GPU_THM_SMBCLK
3
QV1A N17P_M@
DMN53D0LDW-7 2N SOT363-6
GPU_THM_SMBDAT
6 SB000018X00
Vgs(th):0.8V~1.5V
5
DGPU_PEX_RST#
r
o
F
5
ALL_GPWRGD
NC
T4
T3
VGA_SMB_CK2
VGA_SMB_DA2
GPU_THM_SMBCLK
GPU_THM_SMBDAT
4
+GPCPLL_AVDD
+XS_PLLVDD
2
2
J4
H1
XTALOUT
2
XTALSSIN 1
10K_0402_5% N17P@ RV49
3
3XTAL_OUT
RV51
10K_0402_5%
N17P@
2
VGA_SMB_CK2
VGA_SMB_DA2
N17P@
N17P@
RV191 1
RV192 1
2 1.8K_0402_5%
2 1.8K_0402_5%
I2CB_SCL
I2CB_SDA
N17P@
N17P@
RV512 1
RV513 1
2 1.8K_0402_5%
2 1.8K_0402_5%
RV514 1
RV515 1
2 1.8K_0402_5%
2 1.8K_0402_5%
1
RV583
@
2
2
2
1
GPU_EVENT#
DV11
2
1
GPU_PWR_LEVEL
@
Low Performace
High Performace
+1.8V_PLLVDD
1
RV585
@
C
2
0_0402_5%
1
change to shortpad 11/27
2
+XS_PLLVDD
change to shortpad 11/27
N17P@
DV9
GPU_PWR_LEVEL
Low
High
0_0402_5%
1
D
RB751S40T1G_SOD523-2
N17P_M@
+1.8V_PLLVDD
Under
1
2 10K_0402_5%
2 100K_0402_5%
10K_0201_5%
1
2
Under
+1.8V_PLLVDD
Under
1
RV584
@
+VID_PLLVDD
0_0402_5%
1
2
+1.8V_PLLVDD
1
RV586
@
2
2
change to shortpad 11/27
N17P@
0_0402_5%
1
change to shortpad 11/27
N17P@
2
12/21 follow NV spec.
12/21 follow NV spec.
B
N17P@
CV71
10P_0402_50V8J
4
GPU_HPD_RT
RG575 1
@
1
2
4
G
S
43,48
+1V8_AON
D
OUT Y
RG573
100K_0402_5%
18,26,31
GPU_HPD_RT
2 0_0402_5%
HPD_IFPC
QG10
SB00001JN00
S TR MESS139W-G 1N SOT323-3
N17P_M@
@
RV37 1
RV27 1
EC_AC_BAT#
Under
DVT1.0 Change CV50 to SE00000M000
+VID_PLLVDD
2
RB751S40T1G_SOD523-2
N17P_M@
+SP_PLLVDD
N17P@
CV50
22U_0603_6.3V6M
+SP_PLLVDD
XTALIN
XTAL_OUT
E
D
49,56
1
N17P@
N17P@
GC6_EVENT#_D
N17P@
1
H3
H2
GND
1
N17P_M@ +1V8_MAIN
LV7
2
BLM15AX300SN1D
N17P@
+GPCPLL_AVDD
XTAL_OUTBUFF
XTAL_SSIN
1
1
GND
N17P@
CV70
2
10P_0402_50V8J
Near
L
L
AD7
XTAL_IN
XTAL_OUT
e
r
S
+1.8V_PLLVDD
W=40mils
W=40mils
W=40mils
W=40mils
AE8
SP_PLLVDD
VID_PLLVDD
XTALIN
DGPU_PEX_RST#
4
SA00003R000
MAIN@
I2CC_SCL_R
I2CC_SDA_R
AD8
XS_PLLVDD
PEX_RST_N
PEX_TERMP
R2
R3
H26
GPCPLL_AVDD
NC
NC
I2CB_SCL
I2CB_SDA
YV1 N17P_M@
27MHZ_10PF_7V27000050
RV573
100K_0402_5%
UV14
NL17SZ08DFT2G_SC70-5
I2CS_SCL
I2CS_SDA
R7
R6
CV529
0.1U_0201_6.3V6K
2
IN B
IN A
1
GPU_HPD_RT
2
DGPU_PEX_RST#
UV20
NL17SZ08DFT2G_SC70-5
SA00003R000
A
P. P MAIN@
2
PLTRST#
OUT Y
1
IN B
2
VCC
2
5
17,23,26,33,34,35,41
DGPU_HOLD_RST#
GND
20
1
I2CC_SCL
I2CC_SDA
S
SB000016K00
SJ100009700
RV39
10K_0402_5%
2
10K_0402_5%
I2CB_SCL
I2CB_SDA
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
G
1
1
RV58
RES
RES
RES
QV10A
S TR PJT138KA 2N SOT363-6
MAIN@
QV10B
S TR PJT138KA 2N SOT363-6
MAIN@
AG10
AP9
AP8
1
2
@ RV52 10M_0402_5%
+1V8_AON
D
G
AM9
AN9
RES
RES
GPU_GC6_FB_EN
MEM_VREF
I2CC_SCL_R
I2CC_SDA_R
D
GPU_GC6_FB_EN 5
N17P-GT_BGA908
+1V8_AON
1
AJ12
AP29
AK9
AL10
AL9
RES
RES
RES
PEX_TERMP
2
2.49K_0402_1%
Close to UG9
B
AL13
AK13
AK12
AJ26
AK26
DGPU_HOLD_RST#
PLTRST#
20 DGPU_HOLD_RST#
7,23,26,33,34,35,41
PLTRST#
CLK_PCIE_P7
CLK_PCIE_N7
PEX_CLKREQ#
CLK_PCIE_P7
CLK_PCIE_N7
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
w
e
i
v
GPU_GC6_FB_EN_H
2
3
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
PEG_CRX_C_GTX_P0
PEG_CRX_C_GTX_N0
PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1
PEG_CRX_C_GTX_P2
PEG_CRX_C_GTX_N2
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3
PEG_CRX_C_GTX_P4
PEG_CRX_C_GTX_N4
PEG_CRX_C_GTX_P5
PEG_CRX_C_GTX_N5
PEG_CRX_C_GTX_P6
PEG_CRX_C_GTX_N6
PEG_CRX_C_GTX_P7
PEG_CRX_C_GTX_N7
2 10K_0402_5%
1
CV53
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
RV682 1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
RG9
0.1U_0402_10V7K
2
2
N17P@
2
2
2
2
2
2
2
CV72
CV541
CV542
RG50
100K_0402_5%
HPD_IFPC
OVERT#
CV52
PEG_CRX_GTX_P5
PEG_CRX_GTX_N5
HPD_IFPC
6
PEG_CRX_C_GTX_P4
PEG_CRX_C_GTX_N4
1
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
CV833
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
2
2
CV939
2
2
CV539
CV540
N17P@
N17P@
N17P@
N17P@
N17P@
RV42 1
RV574 1
RV526 1
RV60 1
RV532 1
RV55 1
RV41 1
+1V8_AON
RG51
100K_0402_5%
0.1U_0402_10V7K
CV537
CV538
PEG_CRX_GTX_P4
PEG_CRX_GTX_N4
+3VS
3
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
GPU_PEX_RST_HOLD#
4
PEG_CRX_C_GTX_P2
PEG_CRX_C_GTX_N2
N17P@
OVERT#
+3VS
CV51
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
49,56
SYS_PEX_RST_MON#
0.1U_0402_10V7K
2
2
20
59
4.7U_0603_6.3V6K
CV535
CV536
72
1V8_MAIN_EN
56
NVVDD_PSI
72
MEM_VDD_CTL
76
MEM_VREF 53,54
GPU_PWR_LEVEL
26
GPU_GC6_FB_EN_H
20,56
GPU_HPD_RT
43,48
1
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
EC_AC_BAT#
NVVDD_VID
GPU_EVENT#
GC6_EVENT#_D
NVVDD_PSI
NV_ALERT#
EC_AC_BAT#
SYS_PEX_RST_MON#
1V8_MAIN_EN
GPU_PEX_RST_HOLD#
2
PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1
EC_AC_BAT#
5
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
MEM_VDD_CTL
NV_ALERT#
MEM_VREF
VCC
2
2
NVVDD_PSI
GND
1 0.22U_0201_6.3V6M
1 0.22U_0201_6.3V6M
CV533
CV534
1V8_MAIN_EN
NVVDD_PSI
MEM_VDD_CTL
MEM_VREF
GPU_PWR_LEVEL
GPU_GC6_FB_EN_H
GPU_HPD_RT
GPU_EVENT#
3
2
2
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
1V8_MAIN_EN
1
CV531
CV532
PEG_CRX_C_GTX_P0
PEG_CRX_C_GTX_N0
RES
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
NVVDD_VID
2
D
NVVDD_VID
GPU_GC6_FB_EN
GC6_EVENT#_D
CV940
0.1U_0402_10V7K
PEG_CTX_C_GRX_N[0..7]
I2C
PEG_CTX_C_GRX_N[0..7]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
CLK
9
PEG_CTX_C_GRX_P[0..7]
PCI EXPRESS
PEG_CRX_GTX_N[0..7]
PEG_CTX_C_GRX_P[0..7]
P6
M3
L6
P5
P7
L7
M7
N8
L3
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
P8
T8
L2
R4
R5
U3
0.1U_0402_10V7K
PEG_CRX_GTX_N[0..7]
9
9
+1V8_AON
Part 1 of 7
0.1U_0402_10V7K
PEG_CRX_GTX_P[0..7]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
1
PEG_CRX_GTX_P[0..7]
9
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
1
2
PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_N1
PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_N2
PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3
PEG_CTX_C_GRX_P4
PEG_CTX_C_GRX_N4
PEG_CTX_C_GRX_P5
PEG_CTX_C_GRX_N5
PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_N6
PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_N7
2
@
1
Update OK
3
UV1A
GPIO
5
Main Func = GPU
18,26,31
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
N17P-G1(1/9)PCIE/DAC/GPIO
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
48
of
78
5
4
Main Func = GPU
3
2
1
1
+1V8_AON
change to shortpad 11/27
@
DGPU_PEX_RST#
1 RV684
0_0402_5%
@PS8409@
RP10
0_0402_5%
1
2
QV96A
1
DMN61D9UDW -7 2N SOT363-6
SB00001GW 00
IFPC_I2C_DAT
IFPC_I2C_CLK
Vgs:0.5V~1V
HDMI_CTRL_DAT
@
Part 4 of 7
48,56
IFPC_I2C_8409_DAT
RV680
0_0402_5%
1
2
@
IFPC_I2C_DAT_R
6
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
43
43,44
IFPA_L3
IFPA_L3_N
IFPA_L2
IFPA_L2_N
IFPA_L1
IFPA_L1_N
IFPA_L0
IFPA_L0_N
IFPA_AUX_SCL
IFPA_AUX_SDA_N
change to shortpad 11/27
5
2
2
RV679
10K_0402_5%
2
1
1
D
RV678
10K_0402_5%
DGPU_PEX_RST#
QV96B
4
3
IFPC_I2C_CLK_R
DMN61D9UDW -7 2N SOT363-6
SB00001GW 00
RV681
0_0402_5%
1
2
@
@PS8409@
RP9
0_0402_5%
1
2
HDMI_CTRL_CLK
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
43,44
IFPC_I2C_8409_CLK
43
IFPB_L3
IFPB_L3_N
IFPB_L2
IFPB_L2_N
IFPB_L1
IFPB_L1_N
IFPB_L0
IFPB_L0_N
IFPB_AUX_SCL
IFPB_AUX_SDA_N
V32
NC
e
r
L4
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
L
L
A
5
r
o
F
1
2.2K_0402_5%
1
RV677
2
2.2K_0402_5%
IFPC_I2C_DAT_R
IFPC_I2C_CLK_R
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
E
D
2
RV676
+VDISPLAY_VCC
B
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
IFPC_I2C_CLK
IFPC_I2C_DAT
AG3
AG2
AK3
AK2
AB3
AB4
AF3
AF2
L5
GND_SENSE
TMDS
C
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
D
trace width: 16mils
dif f er ent ial vol t age s ens i ng
dif f er ent ial s i gnal r out in
.g
VDD_SENSE
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
43 IFPC_TX2_P
43 IFPC_TX2_N
43 IFPC_TX1_P
43 IFPC_TX1_N
43 IFPC_TX0_P
43 IFPC_TX0_N
43 IFPC_CLK_P
43 IFPC_CLK_N
w
e
i
v
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TEST
NVJTAG_SEL
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
AK11
TESTMODE
AM10
AM11
AP12
AP11
AN11
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_JTAG_TRST#
1
VDD_SENSE_VGA
72
GND_SENSE_VGA
72
C
1
2
PAD~D T98 @
PAD~D T99 @
PAD~D T100 @
PAD~D T101 @
2
N17P@
RV62
10K_0402_5%
2
2
UV1D
+1V8_AON
NC
RV683
@ 0_0402_5%
RV63
10K_0402_5%
N17P@
SERIAL
H6
H4
H5
H7
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO
PAD~D T97
@
ROM_SCLK 55
ROM_SI 55
ROM_SO 55
GENERAL
E1
BUFRST_N
IFPC_AUX_SCL
IFPC_AUX_SDA_N
IFPD_AUX_SCL
IFPD_AUX_SDA_N
B
M1
OVERT
J2
J7
J6
J5
J3
J1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5
IFPE_AUX_SCL
IFPE_AUX_SDA_N
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5
OVERT#
48,56
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5
55
55
55
55
55
55
K3
K4
THERMDP
THERMDN
IFPF_AUX_SCL
IFPF_AUX_SDA_N
N17P-GT_BGA908
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
N17P-G1(2/9)eDP/HDMI/mDP
Size
3
2
Rev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
49
of
78
5
4
3
2
1
Main Func = GPU
N17P@
2
1
2
N17P@
1
2
N17P@
B
N17P@
76
1
2
1
2
N17P@
1
B16
E16
H15
H16
V27
W27
W30
W33
2
N17P@
GDDR5
40.2 ohm
40.2 ohm
60.4 ohm
r
o
F
W=10mils
2
F2
1
2
RV77 N17P@ 40.2_0402_1%
J27
1
2
RV78 N17P@ 40.2_0402_1%
H27
1
2
RV79 N17P@ 60.4_0402_1%
H25
IFPCD_PLLVDD
IFPCD_RSET
IFPEF_PLVDD
IFPEF_RSET
AH8
AJ8
AF7
AF8
IFPCD_PLLVDD
IFPCD_RSET
1
2
N17P@
CV96
1
2
CV97
1
CV95
22U_0603_6.3V6M
CV94
10U_0603_6.3V6M
N17P@
2
N17P@
+1V8_MAIN
RV590
1
@
C
0_0402_5%
1
change to shortpad 11/27
2
N17P@
+1V8_MAIN
+1V8_AON
Under GPU Near GPU
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
Under GPU Near GPU
2
N17P@
N17P@
1
2
1
2
N17P@
1
2
N17P@
1
2
N17P@
AB8
AD6
B
FBVDDQ_SENSE
PROBE_FB_GND
IFP_IOVDD
IFP_IOVDD
FB_CAL_PD_VDDQ
IFP_IOVDD
IFP_IOVDD
FB_CAL_PU_GND
IFP_IOVDD
IFP_IOVDD
FB_CAL_TERM_GND
NC
NC
AG8
AG9
IFP_IOVDD
AF6
AG6
N17P@
RG37
1K_0402_1%
1
2
IFPCD_RSET
AC7
AC8
+1V8_MAIN
AG7
AN2
+IFPX_PLLVDD
IFPCD_PLLVDD
2
LG8 1
PBY160808T-300Y-N_2P
N17P_M@
1
2
Under GPU
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
N17P-G1(3/9)Power
Size
2
Document Number
Rev
0.3
LA-F611P
Date:
3
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
4
CV93
22U_0603_6.3V6M
CV92
10U_0603_6.3V6M
CV91
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV90
CV89
1U_0402_6.3V6K
CV88
1U_0402_6.3V6K
CV87
1U_0402_6.3V6K
1U_0402_6.3V6K
J8
K8
L8
M8
2
N17P@
IFP_IOVDD
Under GPU
5
F1
AG26
Near GPU
CG48
0.1U_0402_10V7K
A
1
IFPAB_PLLVDD
IFPAB_RSET
e
r
N17P@
1
N17P-GT_BGA908
2 0_0402_5%
N17P@
@
1U_0402_6.3V6K
N17P@ CG310
RV655 1
1V8_AON
1V8_AON
VDD18
VDD18
Place near balls
change to shortpad 11/27
+1VS_GFX
L
L
NC
+1V8_AON
E
D
FBVDDQ_SENSE
+1.35VS_VGA
CALIBRATION PIN
FB_CAL_x_PD_VDDQ
FB_CAL_x_PU_GND
FB_CAL_xTERM_GND
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
AG12
N17P@
2
2
CV213
1
1
CV208
2
CV207
1U_0402_6.3V6K
Under GPU(below 150mils)
NC
+PEX_PLL_HVDD
N17P@
2
1
CV214
4.7U_0603_6.3V6K
N17P@
PEX_PLL_HVDD
AH12
2
1
1A
1U_0402_6.3V6K
CV113
CV112
1U_0402_6.3V6K
CV102
1U_0402_6.3V6K
CV101
1U_0402_6.3V6K
CV100
1U_0402_6.3V6K
CV103
1U_0402_6.3V6K
N17P@
2
N17P@
+1V8_MAIN
CV202
N17P@
N17P@
2
1
2
1
D
N17P@
CV843
0.1U_0402_10V7K
N17P@
2
1
CV206
1U_0402_6.3V6K
1
N17P@
CV209
1U_0402_6.3V6K
2
CV844
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.35VS_VGA
N17P@
2
1
N17P@
2
1
2
0.1U_0402_10V7K
N17P@
2
1
2
1
N17P@
1
CG47
0.1U_0402_10V7K
N17P@
2
1
CV210
1U_0402_6.3V6K
N17P@
1
1
CV211
1U_0402_6.3V6K
10uF x 4
22uF x 10
1
2
CV842
1U_0402_6.3V6K
Near GPU
C
2
CV845
1U_0402_6.3V6K
10U_0603_6.3V6M
1uF x 12
10uF x 4
CV841
10U_0603_6.3V6M
Under GPU
1
N17P@
Near GPU
Under GPU
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
3A
w
e
i
v
N17P@
1
N17P@
FBVDDQ
N17P@
2
2
CV840
10U_0603_6.3V6M
Under GPU(below 150mils)
N17P@
1
CV120
N17P@
PEX_HVDD_0
PEX_HVDD_1
PEX_HVDD_2
PEX_HVDD_3
PEX_HVDD_4
PEX_HVDD_5
PEX_HVDD_6
PEX_HVDD_7
PEX_HVDD_8
PEX_HVDD_9
PEX_HVDD_10
PEX_HVDD_11
PEX_HVDD_12
PEX_HVDD_13
N17P@
CV839
4.7U_0603_6.3V6K
1
N17P@
CV119
4.7U_0603_6.3V6K
N17P@
CV80
CV79
10U_0603_6.3V6M
1
2
2
4.7U_0603_6.3V6K
N17P@
CV86
10U_0603_6.3V6M
CV84
22U_0603_6.3V6M
CV85
22U_0603_6.3V6M
N17P@
2
2
CV838
N17P@
2
1
1
1U_0402_6.3V6K
+1.35VS_VGA
2
1
2
CV118
N17P@
1
CV837
1U_0402_6.3V6K
N17P@
2
CV834
22U_0603_6.3V6M
2
1
1
CV114
N17P@
1
CV83
22U_0603_6.3V6M
1
CV943
22U_0603_6.3V6M
2
2
CV117
0.1U_0402_10V7K
N17P@
1
CV944
10U_0603_6.3V6M
CV947
10U_0603_6.3V6M
2
2
AG19
AG21
AG22
AG24
AH21
AH25
1
CV836
1U_0402_6.3V6K
N17P@
1
PEX_DVDD_0
PEX_DVDD_1
PEX_DVDD_2
PEX_DVDD_3
PEX_DVDD_4
PEX_DVDD_5
2
0.1U_0402_10V7K
N17P@
2
CV946
22U_0603_6.3V6M
CV942
22U_0603_6.3V6M
2
1
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_11
FBVDDQ_12
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_43
2
1
0.1U_0402_10V7K
N17P@
1
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B19
E13
E19
H10
H11
H12
H13
H14
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
Y27
1
1U_0402_6.3V6K
N17P@
2
CV945
22U_0603_6.3V6M
2
1
Part 5 of 7
Near GPU
11A
@
POWER
N17P@
1
12/21 follow NV spec.
CV941
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.35VS_VGA
CV835
1U_0402_6.3V6K
UV1E
D
+1VS_GFX
Near GPU
Under GPU
Thursday, March 22, 2018
Sheet
1
50
of
78
5
4
3
2
1
Main Func = GPU
UV1F
@
Part 6 of 7
+GPU_CORE
UV1G
AA14
AA21
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC16
AC19
AC23
M12
M16
M19
M23
N13
N15
N17
N18
N20
N22
P14
P21
R13
R15
R17
R18
R20
R22
T12
T16
T19
T23
U13
U15
U18
U20
U22
V13
V15
C
19A
Part 7 of 7
5
V17
V20
V22
W12
W16
W19
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
+GPU_CORE
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
r
o
F
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
NC
NC
NC
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
L
L
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
E
D
NC
NC
NC
NC
NC
NC
NC
NC
N17P-GT_BGA908
A
VDD_56
VDD_58
VDD_59
VDD_60
VDD_62
VDD_63
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDDS_SENSE
GNDS_SENSE
+GPU_CORE
AA12
AA16
AA19
AA23
AC14
AC21
M14
M21
P12
P16
P19
P23
T14
T21
U17
V18
W14
W21
B
VDD_1
VDD_4
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_14
VDD_15
VDD_17
VDD_18
VDD_20
VDD_21
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_31
VDD_34
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_44
VDD_45
VDD_47
VDD_48
VDD_49
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
@
POWER
47A +GPU_CORE
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
w
e
i
v
e
r
GND
D
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
D
C
B
A
N17P-GT_BGA908
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
2017/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
N17P-G1(4/9)VGA CORE/GND
Size
3
2
R ev
0.3
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
51
of
78
5
4
3
2
1
Main Func = GPU
2 60.4_0402_1%
2 60.4_0402_1%
@
@
+1.35VS_VGA
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
FB_REFPLL_AVDD
FB_A_WCK0
FB_A_WCK#0
FB_A_WCK1
FB_A_WCK#1
FB_A_WCK2
FB_A_WCK#2
FB_A_WCK3
FB_A_WCK#3
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
FB_VREF
U27
H31
2
53
53
53
53
53
53
53
53
CV938
1
@
0.1U_0402_10V7K
2
CV152
1
N17P@
0.1U_0402_10V7K
2
50mA
12/21 follow NV spec.
+FB_PLLAVDD
Place close to ball
N17P@
1
N17P@
2
1
2
+1V8_MAIN
LV13
1
N17P@
1
120mA
2
BLM15AX300SN1D
N17P_M@
FB_B_EDC0
FB_B_EDC1
FB_B_EDC2
FB_B_EDC3
FB_B_EDC4
FB_B_EDC5
FB_B_EDC6
FB_B_EDC7
E11
E3
A3
C9
F23
F27
C30
A24
FB_B_EDC0
FB_B_EDC1
FB_B_EDC2
FB_B_EDC3
FB_B_EDC4
FB_B_EDC5
FB_B_EDC6
FB_B_EDC7
D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23
300mA
2
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_PLL_AVDD
FB_B_CMD15
FB_B_CMD16
FB_B_CMD17
FB_B_CMD18
FB_B_CMD19
FB_B_CMD20
FB_B_CMD21
FB_B_CMD22
FB_B_CMD23
FB_B_CMD24
FB_B_CMD25
FB_B_CMD26
FB_B_CMD27
FB_B_CMD28
FB_B_CMD29
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
FB_B_CMD31
54
+1.35VS_VGA
1
54
54
54
54
54
54
54
54
FB_B_DBI0#
FB_B_DBI1#
FB_B_DBI2#
FB_B_DBI3#
FB_B_DBI4#
FB_B_DBI5#
FB_B_DBI6#
FB_B_DBI7#
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
54
54
54
54
54
54
54
54
54
54
54
54
54
54
RV96
10K_0402_5%
N17P@
2
FB_B_DBI0
FB_B_DBI1
FB_B_DBI2
FB_B_DBI3
FB_B_DBI4
FB_B_DBI5
FB_B_DBI6
FB_B_DBI7
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FB_B_CMD0
FB_B_CMD1
FB_B_CMD2
FB_B_CMD3
FB_B_CMD4
FB_B_CMD5
FB_B_CMD6
FB_B_CMD7
FB_B_CMD8
FB_B_CMD9
FB_B_CMD10
FB_B_CMD11
FB_B_CMD12
FB_B_CMD13
FB_B_CMD14
+1.35VS_VGA
RV99
10K_0402_5%
N17P@
FB_B_CMD30
RV604
RV605
1
1
@
@
54
1
54
54
54
54
54
54
54
54
L
L
RV108
10K_0402_5%
N17P@
E
D
+FB_PLLAVDD
K27
RV107
10K_0402_5%
N17P@
FB_A_CLK0 53
FB_A_CLK0# 53
FB_A_CLK1 53
FB_A_CLK1# 53
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
1
1
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
R30
R31
AB31
AC31
2
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
e
r
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
G14
G20
C12
C20
2 60.4_0402_1%
2 60.4_0402_1%
54
C
+1.35VS_VGA
FB_B_CMD13
FB_B_CMD29
D12
E12
E20
F20
RV110
10K_0402_5%
N17P@
FB_B_CLK0 54
FB_B_CLK0# 54
FB_B_CLK1 54
FB_B_CLK1# 54
F8
E8
A5
A6
D24
D25
B27
C27
FB_B_WCK0
FB_B_WCK#0
FB_B_WCK1
FB_B_WCK#1
FB_B_WCK2
FB_B_WCK#2
FB_B_WCK3
FB_B_WCK#3
1
1
1
RV602
RV603
53
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
RV111
10K_0402_5%
N17P@
2
FB_A_CMD30
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
D
2
2
RV98
10K_0402_5%
N17P@
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
1
1
+1.35VS_VGA
FB_B_D0
FB_B_D1
FB_B_D2
FB_B_D3
FB_B_D4
FB_B_D5
FB_B_D6
FB_B_D7
FB_B_D8
FB_B_D9
FB_B_D10
FB_B_D11
FB_B_D12
FB_B_D13
FB_B_D14
FB_B_D15
FB_B_D16
FB_B_D17
FB_B_D18
FB_B_D19
FB_B_D20
FB_B_D21
FB_B_D22
FB_B_D23
FB_B_D24
FB_B_D25
FB_B_D26
FB_B_D27
FB_B_D28
FB_B_D29
FB_B_D30
FB_B_D31
FB_B_D32
FB_B_D33
FB_B_D34
FB_B_D35
FB_B_D36
FB_B_D37
FB_B_D38
FB_B_D39
FB_B_D40
FB_B_D41
FB_B_D42
FB_B_D43
FB_B_D44
FB_B_D45
FB_B_D46
FB_B_D47
FB_B_D48
FB_B_D49
FB_B_D50
FB_B_D51
FB_B_D52
FB_B_D53
FB_B_D54
FB_B_D55
FB_B_D56
FB_B_D57
FB_B_D58
FB_B_D59
FB_B_D60
FB_B_D61
FB_B_D62
FB_B_D63
2
1
2
53
53
FB_A_CMD13
FB_A_CMD29
FBA_PLL_AVDD
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FB_A_CMD31
FB_A_CMD14
r
o
F
M30
H30
E34
M34
AF30
AK31
AM34
AF32
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
RV95
10K_0402_5%
N17P@
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
D6
D7
C6
B6
F26
E26
A26
A27
B
H17
+FB_PLLAVDD
N17P@
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
1
CV153
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FB_A_CMD15
FB_A_CMD16
FB_A_CMD17
FB_A_CMD18
FB_A_CMD19
FB_A_CMD20
FB_A_CMD21
FB_A_CMD22
FB_A_CMD23
FB_A_CMD24
FB_A_CMD25
FB_A_CMD26
FB_A_CMD27
FB_A_CMD28
FB_A_CMD29
+1.35VS_VGA
CV156
M31
G31
E33
M33
AE31
AK30
AN33
AF33
53
53
53
53
53
53
53
53
53
53
53
53
53
53
22U_0603_6.3V6M
FB_A_EDC0
FB_A_EDC1
FB_A_EDC2
FB_A_EDC3
FB_A_EDC4
FB_A_EDC5
FB_A_EDC6
FB_A_EDC7
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FB_A_CMD0
FB_A_CMD1
FB_A_CMD2
FB_A_CMD3
FB_A_CMD4
FB_A_CMD5
FB_A_CMD6
FB_A_CMD7
FB_A_CMD8
FB_A_CMD9
FB_A_CMD10
FB_A_CMD11
FB_A_CMD12
FB_A_CMD13
CV154
FB_A_EDC0
FB_A_EDC1
FB_A_EDC2
FB_A_EDC3
FB_A_EDC4
FB_A_EDC5
FB_A_EDC6
FB_A_EDC7
P30
F31
F34
M32
AD31
AL29
AM32
AF34
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
R28
AC28
R32
AC32
0.1U_0402_10V7K
53
53
53
53
53
53
53
53
FB_A_DBI0#
FB_A_DBI1#
FB_A_DBI2#
FB_A_DBI3#
FB_A_DBI4#
FB_A_DBI5#
FB_A_DBI6#
FB_A_DBI7#
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35
CV937
FB_A_DBI0
FB_A_DBI1
FB_A_DBI2
FB_A_DBI3
FB_A_DBI4
FB_A_DBI5
FB_A_DBI6
FB_A_DBI7
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
0.1U_0402_10V7K
B
53
53
53
53
53
53
53
53
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
MEMORY INTERFACE
A
C
FB_A_D0
FB_A_D1
FB_A_D2
FB_A_D3
FB_A_D4
FB_A_D5
FB_A_D6
FB_A_D7
FB_A_D8
FB_A_D9
FB_A_D10
FB_A_D11
FB_A_D12
FB_A_D13
FB_A_D14
FB_A_D15
FB_A_D16
FB_A_D17
FB_A_D18
FB_A_D19
FB_A_D20
FB_A_D21
FB_A_D22
FB_A_D23
FB_A_D24
FB_A_D25
FB_A_D26
FB_A_D27
FB_A_D28
FB_A_D29
FB_A_D30
FB_A_D31
FB_A_D32
FB_A_D33
FB_A_D34
FB_A_D35
FB_A_D36
FB_A_D37
FB_A_D38
FB_A_D39
FB_A_D40
FB_A_D41
FB_A_D42
FB_A_D43
FB_A_D44
FB_A_D45
FB_A_D46
FB_A_D47
FB_A_D48
FB_A_D49
FB_A_D50
FB_A_D51
FB_A_D52
FB_A_D53
FB_A_D54
FB_A_D55
FB_A_D56
FB_A_D57
FB_A_D58
FB_A_D59
FB_A_D60
FB_A_D61
FB_A_D62
FB_A_D63
Part 3 of 7
0.1U_0402_10V7K
UV1C
Part 2 of 7
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
w
e
i
v
PU for X32 mode
PU for X32 mode
UV1B
MEMORY INTERFACE B
D
120mA
2
Place close to ball
Place close to ball Place close to BGA
@
A
5
N17P-GT_BGA908
@
N17P-GT_BGA908
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
N17P-G1(5/9)MEM Interface
Size
4
3
2
Document Number
R ev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
52
of
78
5
4
3
2
1
Main Func = GDDR5
MF=0
UV6
SGRAM GDDR5
r
o
F
@
N17P@
N17P@
N17P@
+1.35VS_VGA
N17P@
N17P@
N17P@
N17P@
N17P@
Under DRAM
N17P@
N17P@
N17P@
2
N17P@
1
2
N17P@
CV166
1U_0402_6.3V6K
2
1
CV165
1U_0402_6.3V6K
2
1
CV164
1U_0402_6.3V6K
2
1
CV163
10U_0603_6.3V6M
2
1
CV162
10U_0603_6.3V6M
2
1
CV161
10U_0603_6.3V6M
2
1
10U_0603_6.3V6M
2
Close to DRAM
1
CV160
1
CV373
10U_0603_6.3V6M
2
CV862
10U_0603_6.3V6M
2
1
CV861
22U_0603_6.3V6M
2
1
CV860
22U_0603_6.3V6M
2
Around DRAM
1
CV859
22U_0603_6.3V6M
1
CV863
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.35VS_VGA
N17P@
1
2
FB_A_CLK1#
E
D
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
N17P@
1
2
1
N17P@
RV596
40.2_0402_1%
+1.35VS_VGA
N17P@
RV597
40.2_0402_1%
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
1
2
N17P@
CV904
0.01U_0402_16V7K
+1.35VS_VGA
1
2
N17P@
WCK01#
WCK01
WCK23#
WCK23
WCK23#
WCK23
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GC4H24MFR-T2C
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Under DRAM
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
170-BALL
1
SGRAM GDDR5
2
N17P@
@
+1.35VS_VGA
2
N17P@
N17P@
1
2
N17P@
Around DRAM
1
2
1
2
N17P@
N17P@
1
2
N17P@
1
2
N17P@
D
BYTE6
BYTE5
BYTE4
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
C
B
VDDQ
Under GPU
1uF x 18
10uF x 4
Near GPU
10uF x 2
22uF x 5
Close to DRAM
1
2
1
2
N17P@
N17P@
1
2
N17P@
1
2
1
2
N17P@
N17P@
1
2
1
2
N17P@
1
2
N17P@
N17P@
1
2
N17P@
1
2
1
2
N17P@
1
2
N17P@
1
2
N17P@
N17P@
1
2
N17P@
1
2
1
CV388
170-BALL
J2
FB_A_CMD29
CAS#
WE#
RAS#
CS#
CV385
1U_0402_6.3V6K
QV20
BSS138W 1N SOT-323-3
N17P_M@
A10
U10
J14
BYTE7
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CV386
1U_0402_6.3V6K
S
G
P5
P4
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
+1.35VS_VGA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CV387
1U_0402_6.3V6K
D
2
MEM_VREF
L
L
D5
D4
FB_A_D56
FB_A_D57
FB_A_D58
FB_A_D59
FB_A_D60
FB_A_D61
FB_A_D62
FB_A_D63
FB_A_D48
FB_A_D49
FB_A_D50
FB_A_D51
FB_A_D52
FB_A_D53
FB_A_D54
FB_A_D55
FB_A_D40
FB_A_D41
FB_A_D42
FB_A_D43
FB_A_D44
FB_A_D45
FB_A_D46
FB_A_D47
FB_A_D32
FB_A_D33
FB_A_D34
FB_A_D35
FB_A_D36
FB_A_D37
FB_A_D38
FB_A_D39
CV382
1U_0402_6.3V6K
1
48,54
3
B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
FB_A_WCK#2
FB_A_WCK2
ABI#
RAS#
CS#
CAS#
WE#
FB_A_D56
FB_A_D57
FB_A_D58
FB_A_D59
FB_A_D60
FB_A_D61
FB_A_D62
FB_A_D63
FB_A_D48
FB_A_D49
FB_A_D50
FB_A_D51
FB_A_D52
FB_A_D53
FB_A_D54
FB_A_D55
FB_A_D40
FB_A_D41
FB_A_D42
FB_A_D43
FB_A_D44
FB_A_D45
FB_A_D46
FB_A_D47
FB_A_D32
FB_A_D33
FB_A_D34
FB_A_D35
FB_A_D36
FB_A_D37
FB_A_D38
FB_A_D39
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV383
1U_0402_6.3V6K
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
A10/A0
A11/A6
A8/A7
A9/A1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV384
1U_0402_6.3V6K
+1.35VS_VGA
FB_A_WCK#3
FB_A_WCK3
52
52
FB_A_CLK1
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
VPP/NC
VPP/NC
MF
SEN
ZQ
MF=0
CV175
1U_0402_6.3V6K
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GC4H24MFR-T2C
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
CV174
1U_0402_6.3V6K
N17P@
BA2/A4
BA3/A3
BA0/A2
BA1/A5
CV173
1U_0402_6.3V6K
W=16mils
BA0/A2
BA1/A5
BA2/A4
BA3/A3
e
r
J1
J10
J13
J4
G3
G12
L3
L12
52
52
52
CK
CK#
CKE#
CV172
1U_0402_6.3V6K
2
N17P@
RV127
1.33K_0402_1%
CV158
1
820P_0402_25V7
+FB_A_VREFC0
1
CV374
1U_0402_6.3V6K
2
RV126
1
2
931_0402_1%
N17P@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CV375
1U_0402_6.3V6K
1
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
CV167
1U_0402_6.3V6K
MEM_VREF levels
70% of rail
Terminat i on Enabl e
N17P@
RV125
50% of rail
Terminat i on Disabl e 549_0402_1%
2 N17P@ 1
121_0402_1%
FB_A_CMD24
FB_A_CMD31
FB_A_CMD21
FB_A_CMD28
FB_A_CMD16
N17P@
2
RV121
52
52
52
52
52
+FB_A_VREFC0
1
2 N17P@ 1
1K_0402_1%
DBI3#
DBI2#
DBI1#
DBI0#
CV171
10U_0603_6.3V6M
RESET#
+1.35VS_VGA
RV117
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
EDC3
EDC2
EDC1
EDC0
DBI0#
DBI1#
DBI2#
DBI3#
CV858
VREFD
VREFD
VREFC
A5
U5
MF=1
w
e
i
v
EDC0
EDC1
EDC2
EDC3
CV169
10U_0603_6.3V6M
WCK01#
WCK01
K4
H5
H4
K5
J5
CV857
1U_0402_6.3V6K
WCK23#
WCK23
WCK23#
WCK23
J12
J11
J3
10U_0603_6.3V6M
J2
FB_A_CMD13
WCK01#
WCK01
FB_A_CLK1
FB_A_CLK1#
FB_A_CMD30
CV856
1U_0402_6.3V6K
52
CAS#
WE#
RAS#
CS#
D2
D13
P13
P2
CV168
A10
U10
J14
+FB_A_VREFC0
N17P@
CV903
0.01U_0402_16V7K
ABI#
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
FB_A_DBI7
FB_A_DBI6
FB_A_DBI5
FB_A_DBI4
CV381
10U_0603_6.3V6M
P5
P4
FB_A_CMD26
FB_A_CMD23
FB_A_CMD22
FB_A_CMD27
FB_A_CMD25
C2
C13
R13
R2
H11
K10
K11
H10
CV855
1U_0402_6.3V6K
D5
D4
52
52
52
52
52
CV854
1U_0402_6.3V6K
FB_A_WCK#1
FB_A_WCK1
FB_A_CMD19
FB_A_CMD17
FB_A_CMD18
FB_A_CMD20
CV866
10U_0603_6.3V6M
2
FB_A_WCK#0
FB_A_WCK0
52
52
52
52
52
52
CV867
22U_0603_6.3V6M
1
52
52
FB_A_CLK1
FB_A_CLK1#
FB_A_CMD30
CV853
1U_0402_6.3V6K
2
2
N17P@
RV595
40.2_0402_1%
J4
G3
G12
L3
L12
52
52
52
+1.35VS_VGA
MF
SEN
ZQ
CV852
1U_0402_6.3V6K
N17P@
RV594
40.2_0402_1%
C
FB_A_CMD8
FB_A_CMD12
FB_A_CMD0
FB_A_CMD15
FB_A_CMD5
FB_A_DBI7
FB_A_DBI6
FB_A_DBI5
FB_A_DBI4
CV864
22U_0603_6.3V6M
1
1
FB_A_CLK0#
52
52
52
52
52
52
52
52
52
FB_A_EDC7
FB_A_EDC6
FB_A_EDC5
FB_A_EDC4
+1.35VS_VGA
CV865
22U_0603_6.3V6M
FB_A_CLK0
J1
J10
J13
BYTE3
FB_A_EDC7
FB_A_EDC6
FB_A_EDC5
FB_A_EDC4
CV200
2 N17P@ 1
RV120
121_0402_1%
BYTE2
1
2 N17P@ 1
1K_0402_1%
VPP/NC
VPP/NC
BYTE1
52
52
52
52
2
RV116
A10/A0
A11/A6
A8/A7
A9/A1
BYTE0
820P_0402_25V7
A5
U5
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
CV851
1U_0402_6.3V6K
K4
H5
H4
K5
J5
BA2/A4
BA3/A3
BA0/A2
BA1/A5
FB_A_D0
FB_A_D1
FB_A_D2
FB_A_D3
FB_A_D4
FB_A_D5
FB_A_D6
FB_A_D7
FB_A_D8
FB_A_D9
FB_A_D10
FB_A_D11
FB_A_D12
FB_A_D13
FB_A_D14
FB_A_D15
FB_A_D16
FB_A_D17
FB_A_D18
FB_A_D19
FB_A_D20
FB_A_D21
FB_A_D22
FB_A_D23
FB_A_D24
FB_A_D25
FB_A_D26
FB_A_D27
FB_A_D28
FB_A_D29
FB_A_D30
FB_A_D31
CV868
22U_0603_6.3V6M
FB_A_CMD6
FB_A_CMD11
FB_A_CMD10
FB_A_CMD7
FB_A_CMD9
BA0/A2
BA1/A5
BA2/A4
BA3/A3
FB_A_D0
FB_A_D1
FB_A_D2
FB_A_D3
FB_A_D4
FB_A_D5
FB_A_D6
FB_A_D7
FB_A_D8
FB_A_D9
FB_A_D10
FB_A_D11
FB_A_D12
FB_A_D13
FB_A_D14
FB_A_D15
FB_A_D16
FB_A_D17
FB_A_D18
FB_A_D19
FB_A_D20
FB_A_D21
FB_A_D22
FB_A_D23
FB_A_D24
FB_A_D25
FB_A_D26
FB_A_D27
FB_A_D28
FB_A_D29
FB_A_D30
FB_A_D31
1
52
52
52
52
52
H11
K10
K11
H10
CK
CK#
CKE#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
2
FB_A_CMD2
FB_A_CMD4
FB_A_CMD3
FB_A_CMD1
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1U_0402_6.3V6K
52
52
52
52
FB_A_CLK0
FB_A_CLK0#
FB_A_CMD14
DBI0#
DBI1#
DBI2#
DBI3#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
22U_0603_6.3V6M
FB_A_CLK0
FB_A_CLK0#
FB_A_CMD14
D2
D13
P13
P2
EDC3
EDC2
EDC1
EDC0
CV380
52
52
52
FB_A_DBI0
FB_A_DBI1
FB_A_DBI2
FB_A_DBI3
EDC0
EDC1
EDC2
EDC3
MF=0
CV379
1U_0402_6.3V6K
FB_A_DBI0
FB_A_DBI1
FB_A_DBI2
FB_A_DBI3
C2
C13
R13
R2
MF=0
CV377
1U_0402_6.3V6K
52
52
52
52
FB_A_EDC0
FB_A_EDC1
FB_A_EDC2
FB_A_EDC3
MF=1
CV378
1U_0402_6.3V6K
FB_A_EDC0
FB_A_EDC1
FB_A_EDC2
FB_A_EDC3
MF=1
CV376
1U_0402_6.3V6K
D
52
52
52
52
MF=1
UV7
MF=0
CV170
10U_0603_6.3V6M
Memory Part i t i on A- L ower 32 bi t
2
N17P@
VDDQ
N17P@
N17P@
5
N17P@
N17P@
N17P@
2
N17P@
2
N17P@
1
2
CV876
1
CV875
1U_0402_6.3V6K
2
1
CV874
1U_0402_6.3V6K
2
1
CV873
1U_0402_6.3V6K
2
1
CV872
1U_0402_6.3V6K
2
N17P@
1
CV871
1U_0402_6.3V6K
2
1
CV870
1U_0402_6.3V6K
1
CV869
1U_0402_6.3V6K
1U_0402_6.3V6K
Under GPU
A
A
1uF x 18
10uF x 4
Near GPU
10uF x 2
22uF x 5
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
N17P-G1(6/9)GDDR5_A
Thursday, March 22, 2018
1
Sheet
53
of
78
5
4
3
2
1
Main Func = GDDR5
MF=0
N17P@
+1.35VS_VGA
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
N17P@
5
N17P@
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
1
N17P@
2
N17P@
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
1
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
N17P@
CV906
0.01U_0402_16V7K
+1.35VS_VGA
WCK01#
WCK01
VREFD
VREFD
VREFC
RESET#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GC4H24MFR-T2C
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Under DRAM
170-BALL
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
SGRAM GDDR5
1
2
N17P@
@
+1.35VS_VGA
2
N17P@
N17P@
1
2
N17P@
Around DRAM
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
D
BYTE7
BYTE6
BYTE5
BYTE4
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
C
B
VDDQ
Under GPU
1uF x 18
10uF x 4
Near GPU
10uF x 2
22uF x 5
Close to DRAM
N17P@
1
2
1
2
N17P@
N17P@
1
2
1
2
N17P@
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
N17P@
1
2
1
2
N17P@
N17P@
1
2
N17P@
1
2
N17P@
1
2
1
CV404
1
+1.35VS_VGA
N17P@
RV601
40.2_0402_1%
WCK23#
WCK23
CV401
1U_0402_6.3V6K
1
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
WCK23#
WCK23
CAS#
WE#
RAS#
CS#
CV403
1U_0402_6.3V6K
2
N17P@
2
N17P@
VDDQ
A
Under GPU
1uF x 18
10uF x 4
CV902
1
CV901
1U_0402_6.3V6K
2
CV900
1U_0402_6.3V6K
1
CV899
1U_0402_6.3V6K
2
CV898
1U_0402_6.3V6K
1
1
J2
FB_B_CMD29
WCK01#
WCK01
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CV402
1U_0402_6.3V6K
2
A10
U10
J14
ABI#
RAS#
CS#
CAS#
WE#
FB_B_D56
FB_B_D57
FB_B_D58
FB_B_D59
FB_B_D60
FB_B_D61
FB_B_D62
FB_B_D63
FB_B_D48
FB_B_D49
FB_B_D50
FB_B_D51
FB_B_D52
FB_B_D53
FB_B_D54
FB_B_D55
FB_B_D40
FB_B_D41
FB_B_D42
FB_B_D43
FB_B_D44
FB_B_D45
FB_B_D46
FB_B_D47
FB_B_D32
FB_B_D33
FB_B_D34
FB_B_D35
FB_B_D36
FB_B_D37
FB_B_D38
FB_B_D39
+1.35VS_VGA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CV398
1U_0402_6.3V6K
1
FB_B_WCK#2
FB_B_WCK2
MF
SEN
ZQ
CV400
1U_0402_6.3V6K
2
2
VPP/NC
VPP/NC
A10/A0
A11/A6
A8/A7
A9/A1
FB_B_D56
FB_B_D57
FB_B_D58
FB_B_D59
FB_B_D60
FB_B_D61
FB_B_D62
FB_B_D63
FB_B_D48
FB_B_D49
FB_B_D50
FB_B_D51
FB_B_D52
FB_B_D53
FB_B_D54
FB_B_D55
FB_B_D40
FB_B_D41
FB_B_D42
FB_B_D43
FB_B_D44
FB_B_D45
FB_B_D46
FB_B_D47
FB_B_D32
FB_B_D33
FB_B_D34
FB_B_D35
FB_B_D36
FB_B_D37
FB_B_D38
FB_B_D39
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV399
1U_0402_6.3V6K
1
P5
P4
FB_B_CLK1#
1
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV194
1U_0402_6.3V6K
2
D5
D4
FB_B_CLK1
N17P@
RV600
40.2_0402_1%
BA2/A4
BA3/A3
BA0/A2
BA1/A5
CV193
1U_0402_6.3V6K
1
FB_B_WCK#3
FB_B_WCK3
52
BA0/A2
BA1/A5
BA2/A4
BA3/A3
CV192
1U_0402_6.3V6K
2
N17P@
CK
CK#
CKE#
CV191
1U_0402_6.3V6K
1
52
52
L
L
2
DBI3#
DBI2#
DBI1#
DBI0#
CV190
10U_0603_6.3V6M
2
CV391
1U_0402_6.3V6K
1
CV390
1U_0402_6.3V6K
2
CV184
1U_0402_6.3V6K
1
CV181
1U_0402_6.3V6K
2
CV180
10U_0603_6.3V6M
1
CV179
10U_0603_6.3V6M
2
CV183
1
CV389
10U_0603_6.3V6M
2
10U_0603_6.3V6M
1
CV182
10U_0603_6.3V6M
CV887
10U_0603_6.3V6M
2
CV888
22U_0603_6.3V6M
1
Under DRAM
CV896
1U_0402_6.3V6K
CV895
1U_0402_6.3V6K
1U_0402_6.3V6K
N17P@
2
2
N17P@
A
1
1
CV885
22U_0603_6.3V6M
2
CV886
22U_0603_6.3V6M
1
@
Close to DRAM
CV185
1U_0402_6.3V6K
1
3
r
o
F
S
Around DRAM
CV897
1U_0402_6.3V6K
N17P@
CV889
22U_0603_6.3V6M
22U_0603_6.3V6M
2
SGRAM GDDR5
FB_B_CMD24
FB_B_CMD31
FB_B_CMD21
FB_B_CMD28
FB_B_CMD16
+FB_B_VREFC1
1
J4
G3
G12
L3
L12
52
52
52
52
52
52
52
J1
J10
J13
2 N17P@ 1
121_0402_1%
MF=0
w
e
i
v
DBI0#
DBI1#
DBI2#
DBI3#
e
r
RV135
E
D
170-BALL
QV21
BSS138W 1N SOT-323-3
N17P_M@
G
+1.35VS_VGA
1
D
2
MEM_VREF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
A5
U5
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
EDC3
EDC2
EDC1
EDC0
CV884
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GC4H24MFR-T2C
K4
H5
H4
K5
J5
MF=1
EDC0
EDC1
EDC2
EDC3
CV188
10U_0603_6.3V6M
N17P@
B
48,53
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H11
K10
K11
H10
CV883
1U_0402_6.3V6K
+1.35VS_VGA
WCK01#
WCK01
J12
J11
J3
10U_0603_6.3V6M
2
WCK23#
WCK23
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
FB_B_CLK1
FB_B_CLK1#
FB_B_CMD30
CV882
1U_0402_6.3V6K
W=16mils
1
CV177
1
2
+FB_B_VREFC1
820P_0402_25V7
N17P@
RV142
1.33K_0402_1%
FB_B_CMD26
FB_B_CMD23
FB_B_CMD22
FB_B_CMD27
FB_B_CMD25
D2
D13
P13
P2
CV397
1
2
RV141
1
2
931_0402_1%
N17P@
WCK01#
WCK01
RESET#
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
N17P@
RV140
549_0402_1%
CAS#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFD
VREFD
VREFC
J2
+1.35VS_VGA
MEM_VREF levels
70% of rail
Terminat i on Enabl e
50% of rail
Terminat i on Disabl e
ABI#
RAS#
CS#
CAS#
WE#
WCK23#
WCK23
A10
U10
J14
FB_B_CMD13
52
52
52
52
52
CV880
1U_0402_6.3V6K
52
FB_B_CMD19
FB_B_CMD17
FB_B_CMD18
FB_B_CMD20
CV879
1U_0402_6.3V6K
P5
P4
+FB_B_VREFC1
52
52
52
52
CV893
22U_0603_6.3V6M
D5
D4
FB_B_WCK#1
FB_B_WCK1
FB_B_CLK1
FB_B_CLK1#
FB_B_CMD30
CV890
22U_0603_6.3V6M
FB_B_WCK#0
FB_B_WCK0
52
52
52
FB_B_DBI7
FB_B_DBI6
FB_B_DBI5
FB_B_DBI4
2 N17P@ 1
RV131
1K_0402_1%
CV199
52
52
C
FB_B_DBI7
FB_B_DBI6
FB_B_DBI5
FB_B_DBI4
C2
C13
R13
R2
+1.35VS_VGA
1
FB_B_CMD8
FB_B_CMD12
FB_B_CMD0
FB_B_CMD15
FB_B_CMD5
52
52
MF
SEN
ZQ
J4
G3
G12
L3
L12
52
52
52
52
52
52
52
52
52
FB_B_EDC7
FB_B_EDC6
FB_B_EDC5
FB_B_EDC4
2
N17P@
CV905
0.01U_0402_16V7K
FB_B_EDC7
FB_B_EDC6
FB_B_EDC5
FB_B_EDC4
+1.35VS_VGA
J1
J10
J13
2 N17P@ 1
121_0402_1%
BYTE3
CV878
1U_0402_6.3V6K
RV136
CV392
1U_0402_6.3V6K
2
VPP/NC
VPP/NC
2 N17P@ 1
RV132
1K_0402_1%
CV186
1U_0402_6.3V6K
1
A10/A0
A11/A6
A8/A7
A9/A1
BYTE2
52
52
52
52
CV881
1U_0402_6.3V6K
A5
U5
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
BYTE1
CV891
22U_0603_6.3V6M
N17P@
RV599
40.2_0402_1%
2
2
N17P@
RV598
40.2_0402_1%
1
1
FB_B_CLK0#
K4
H5
H4
K5
J5
BA2/A4
BA3/A3
BA0/A2
BA1/A5
BYTE0
820P_0402_25V7
FB_B_CLK0
BA0/A2
BA1/A5
BA2/A4
BA3/A3
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
CV877
1U_0402_6.3V6K
FB_B_CMD6
FB_B_CMD11
FB_B_CMD10
FB_B_CMD7
FB_B_CMD9
H11
K10
K11
H10
FB_B_D0
FB_B_D1
FB_B_D2
FB_B_D3
FB_B_D4
FB_B_D5
FB_B_D6
FB_B_D7
FB_B_D8
FB_B_D9
FB_B_D10
FB_B_D11
FB_B_D12
FB_B_D13
FB_B_D14
FB_B_D15
FB_B_D16
FB_B_D17
FB_B_D18
FB_B_D19
FB_B_D20
FB_B_D21
FB_B_D22
FB_B_D23
FB_B_D24
FB_B_D25
FB_B_D26
FB_B_D27
FB_B_D28
FB_B_D29
FB_B_D30
FB_B_D31
CV894
22U_0603_6.3V6M
52
52
52
52
52
CK
CK#
CKE#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
1
FB_B_CMD2
FB_B_CMD4
FB_B_CMD3
FB_B_CMD1
J12
J11
J3
DBI3#
DBI2#
DBI1#
DBI0#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
2
52
52
52
52
FB_B_CLK0
FB_B_CLK0#
FB_B_CMD14
DBI0#
DBI1#
DBI2#
DBI3#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1U_0402_6.3V6K
FB_B_CLK0
FB_B_CLK0#
FB_B_CMD14
D2
D13
P13
P2
EDC3
EDC2
EDC1
EDC0
22U_0603_6.3V6M
52
52
52
FB_B_DBI0
FB_B_DBI1
FB_B_DBI2
FB_B_DBI3
EDC0
EDC1
EDC2
EDC3
FB_B_D0
FB_B_D1
FB_B_D2
FB_B_D3
FB_B_D4
FB_B_D5
FB_B_D6
FB_B_D7
FB_B_D8
FB_B_D9
FB_B_D10
FB_B_D11
FB_B_D12
FB_B_D13
FB_B_D14
FB_B_D15
FB_B_D16
FB_B_D17
FB_B_D18
FB_B_D19
FB_B_D20
FB_B_D21
FB_B_D22
FB_B_D23
FB_B_D24
FB_B_D25
FB_B_D26
FB_B_D27
FB_B_D28
FB_B_D29
FB_B_D30
FB_B_D31
CV396
FB_B_DBI0
FB_B_DBI1
FB_B_DBI2
FB_B_DBI3
C2
C13
R13
R2
MF=0
CV394
1U_0402_6.3V6K
52
52
52
52
FB_B_EDC0
FB_B_EDC1
FB_B_EDC2
FB_B_EDC3
MF=0
CV393
1U_0402_6.3V6K
FB_B_EDC0
FB_B_EDC1
FB_B_EDC2
FB_B_EDC3
MF=1
CV395
1U_0402_6.3V6K
D
52
52
52
52
MF=1
UV9
MF=1
CV187
10U_0603_6.3V6M
MF=0
CV892
10U_0603_6.3V6M
UV8
CV189
10U_0603_6.3V6M
Memory Part i t i on A- L ower 32 bi t
Near GPU
10uF x 2
22uF x 5
2
N17P@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
3
2
Document Number
Rev
0.3
LA-F611P
Date:
4
N17P-G1(7/9)GDDR5_B
Thursday, March 22, 2018
1
Sheet
54
of
78
5
4
3
2
1
+1V8_AON
1
ROM_SI
ROM_SO
ROM_SCLK
2
2
2
2
RV153
100K_0402_5%
@
RV154
100K_0402_5%
@
RV155
100K_0402_5%
RV156
100K_0402_5%
1
1
1
1
1
C
B
SMB_ALT_ADDR
Low
High
Single GPU
Dual GPU
DEVID_SEL
Low
High
Original Device ID
Re-brand Device ID
VGA_DEVICE
Low
High
3D Device
VGA Device
PCIE_CFG
Low
High
A
5
w
e
i
v
RV160
RV161
RV162
@ 100K_0402_5% @ 100K_0402_5% @ 100K_0402_5%
RV66
100K_0402_5%
1
2
RV152
100K_0402_5%
@
RV159
100K_0402_5%
ROM_SI
ROM_SO
ROM_SCLK
2
STRAP5
2
1
STRAP4
1
1
STRAP3
RV158
100K_0402_5%
2
1
49
49
49
STRAP2
RV157
100K_0402_5%
r
o
F
L
L
1
1
STRAP1
2
2
1
STRAP0
1
D
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5
2
49
49
49
49
49
49
RV593
100K_0402_5%
@
1
2
RV150
100K_0402_5%
@
2
2
RV149
100K_0402_5%
@
1
2
RV148
100K_0402_5%
@
2
2
RV147
100K_0402_5%
@
1
2
+1V8_AON
RV146
100K_0402_5%
@
D
e
r
C
B
E
D
Normal signal swing
Reduce the signal amplitude
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
N17P-G1(8/9)MISC
Size
Document Number
3
2
Rev
0.3
LA-F611P
Date:
4
Thursday, March 22, 2018
1
Sheet
55
of
78
A
B
C
D
E
F
G
H
Main Func = DC/DC
+1.8V_PRIM
+1V8_AON / +1V8_MAIN
1
+3VS
1
CG438
0.1U_0201_6.3V6K
@
RG70
10K_0402_5%
Enable 1.2V
Disable 0.5V
1
2
5
2
1
Y
A
1V8_AON_ON
4
3
1V8_MAIN_EN
UG25
74LVC1G32GW_TSSOP5
MAIN@
+1V8_AON
1
1
@
RG505
10K_0201_5%
2
RB751S40T1G_SOD523-2
DG7
MAIN@
2
2
1
6
RG580
Vgs(th):0.8V~1.5V
1
2 0_0402_5%
1
5
QG23A
DMN63D8LDW-7 2N SOT363-6
N17P_M@
SB000013K00
4
3
CMP_VOUT0
1V8_MAIN_EN
2
2
DG3
RB751S40T1G_SOD523-2
MAIN@
26,62
NVVDD1_EN
1
NVVDD1_EN
72
RG549
100K_0402_5%
1
2
QG23B
1
DMN63D8LDW-7 2N SOT363-6
N17P_M@
SB000013K00
+1V8_AON
2
CG442
2200P_0402_25V7K
1
1
DG10
1
PEX_VDD_EN_U
2
2
1
2
RG550
39K_0402_1%
DGPU_PEX_RST#
CG482
0.047U_0402_16V4Z
2
+1V8_AON
IN A
6
GPU_GC6_FB_EN_H
1
GPU_GC6_FB_EN_H
RG553
0_0201_5%
2
RG554
0_0201_5%
2
5
UG22
NL17SZ08DFT2G_SC70-5
MAIN@
RG506
10K_0201_5%
RB751S40T1G_SOD523-2
DG4
2
1
NVVDD1_PGOOD
48,72
MAIN@
3
+1V8_AON
CG440
0.1U_0201_6.3V6K
5
2
VCC
4
Y
FBVDD/Q_EN
76
G
UG27
74LVC1G32GW_TSSOP5
MAIN@
RG557
10K_0402_5%
2
3
1
A
A
2
DMN53D0LDW-7_SOT363-6
SB000018X00
QG504A
MAIN@
1V8_MAIN_EN
2
DMN53D0LDW-7_SOT363-6
SB000018X00
B
1
2
6
7
VBIAS
GND
ON2
CT2
VIN2
VIN2
11
10
1
9
8
VOUT2
VOUT2
2
CG320
10U_0603_6.3V6M
+1V8_MAIN
1
2
CG65
220P_0402_50V8J
GPAD
1
1
15
AOZ1331_SON14_2X3
2
CG290
10U_0603_6.3V6M
SA00006U300
MAIN@
2
GPU Power Down Sequence
3
GPU GC6 Entry/Exit Sequence
Optimus Sequence
1
RG514
+5VALW
51_0402_5%
2
@
RG513
@
10K_0402_5%
5
6
5
QG504B
MAIN@
CT1
1
2
CG64
220P_0402_50V8J
+1.35VS_VGA
2
3
RG511
10K_0402_5%
E
D
12
1
2
10_0402_1%
1
2
QG503A
MAIN@
1V8_AON_ON
DMN53D0LDW-7 2N SOT363-6
SB000018X00
QG503B
MAIN@
4
4
DMN53D0LDW-7 2N SOT363-6
SB000018X00
2
1
1
r
o
F
2
2
5
6
QG505A
MAIN@
PEX_VDD_EN
RG509
10K_0402_5%
RG512
+5VALW
10_0402_1%
6
QG505B
MAIN@
1
RG543
10K_0402_5%
3
4
+5VALW
1
1
2
10_0402_1%
+1V8_MAIN
RG510
DMN53D0LDW-7_SOT363-6
SB000018X00
2
1
+5VALW
+1V8_AON
3
RG544
4
1
+1VS_GFX
1
Discharge
UG31
NL17SZ08DFT2G_SC70-5
77
ON1
14
13
VOUT1
VOUT1
DMN53D0LDW-7_SOT363-6
SB000018X00
FBVDD/Q_EN
4
3
B
QG506B
@
5
QG506A
@
4
1
2
+1.0VS_VGA_PGOOD
6
GPU_GC6_FB_EN_H
77
DMN53D0LDW-7_SOT363-6
SB000018X00
2
1
1
e
r
PEX_VDD_EN
GPU Power Up Sequence
MAIN@
QG502A
DMN53D0LDW-7 2N SOT363-6
MAIN@
2
+3VS
1
3
1
1
20,48
4
OUT Y
4
IN B
3
2
QG502B
DMN53D0LDW-7 2N SOT363-6
5
1
GND VCC
2
DGPU_PEX_RST#
L
L
CG246
0.1U_0201_6.3V6K
2
2
1
1
4
CG527
0.1U_0201_6.3V6K
SA00003R000
MAIN@
1
+1V8_AON
RG516
10K_0201_5%
OUT Y
IN A
3
RB751S40T1G_SOD523-2
MAIN@
48,49
IN B
GND VCC
5
2
2
2
CG289
10U_0603_6.3V6M
RG546
10K_0402_5%
1
CG386
0.1U_0402_10V7K
2 100K_0402_5%
CG288
22U_0603_6.3V6M
RG5761
OVERT#
CG487
0.1U_0402_10V7K
2
1V8_MAIN_EN
+3VS
DGPU_PEX_RST#
48,49
4
5
1
48
VIN1
VIN1
w
e
i
v
+5VS
G
1
GPU_PWR_EN
VCC
B
2
1
DGPU_PWROK
@
DGPU_PWR_EN
18,48,76
3
20
RG551
0_0201_5%
1
2
+1V8_AON
UG12
2
2
+1.8V_PRIM
DMN53D0LDW-7_SOT363-6
SB000018X00
Compal Secret Data
Security Classification
Issued Date
2015/09/18
Deciphered Date
2016/09/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
D
E
F
G
Document Number
Rev
0.3
LA-F611P
Date:
C
Compal Electronics, Inc.
GPU power control
Size
Thursday, March 22, 2018
Sheet
H
56
of
78
5
4
MODEL NAME : CALXX/CALXX
PCB NO : LA-F611P
D
X76 : S4G@ X76XXXXXLXX
X76 : M4G@ X76XXXXXLXX
Samsung 4G
Micron 4G
S4G@
UV7
R3
GPU
N17P_G0_R1@ UV1
N17P_G0_R3@
2
S4G@
R3
UV8
S4G@
R3
UV9
S4G@
UV6
R3
M4G@
R3
X76 : H4G@ X76XXXXXLXX
M4G@
UV8
R3
M4G@
R3
R3
K4G80325FB-HC28
MT51J256M32HF-70:A MT51J256M32HF-70:A MT51J256M32HF-70:A MT51J256M32HF-70:A
SA000092D1L
SA000092D1L
SA000092D1L
SA000092D1L
SA00009TV1L
SA00009TV1L
SA00009TV1L
RV152
RV153
RV154
RV146
RV153
RV154
S4G@
S4G@
M4G@
M4G@
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
SA0000A050L
SA0000A051L
SD028100380
SD028100380
SD028100380
SD028100380
SD028100380
SD028100380
L
L
L
H
L
L
R1
R3
N17P-G1-A1
SA0000A060L
SA0000A061L
Samsung 4G
Micron 4G
C
L
L
UV7
H4G@
UV8
R3
H4G@
UV9
R3
D
H4G@
R3
H5GC8H24MJR-R0C
H5GC8H24MJR-R0C
H5GC8H24MJR-R0C
H5GC8H24MJR-R0C
SA00009U11L
SA00009U11L
SA00009U11L
SA00009U11L
RV152
RV147
RV154
H4G@
H4G@
H
H4G@
L
100K_0402_5%
100K_0402_5%
100K_0402_5%
SD028100380
SD028100380
SD028100380
e
r
Hynix 4G
C
E
D
B
r
o
F
H4G@
L
N17P_G1_R3@
N17P-G1-A1
5
SA00009TV1L
M4G@
R3
UV6
R3
K4G80325FB-HC28
N17P-G0-A1
A
M4G@
K4G80325FB-HC28
R1
N17P_G1_R1@ UV1
UV9
K4G80325FB-HC28
S4G@
w
e
i
v
Hynix 4G
UV7
N17P-G0-A1
UV1
1
Bom
Structure
UV6
UV1
3
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Reserved
Size
4
3
2
Document Number
R ev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
57
of
78
5
4
3
2
Version Change List ( P. I. R. List )
1
Page 2
w
e
i
v
D
C
L
L
A
5
e
r
C
E
D
B
r
o
F
D
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
NOTE
Size
4
3
2
Document Number
Rev
0.3
LA-F611P
Date:
Thursday, March 22, 2018
1
Sheet
58
of
78
A
B
Main Func = DCIN/BATT CONN
+DC_IN
PSID@ PQ1
FDV301N-G_SOT23-3
ACES_50458-01001-P01_10P-T
ACES_50458-01001-P01_10P-T
A
PBAT_CHG_SMBDAT
26,61
1
1
1
2
2
1
1
1
3
1
3
1
PQ19
AO3409_SOT23-3
2
1
PC6
0.022U_0603_50V7K
2
1
2
3
AC_B2B_S2_SW
S
2
3
4
5
PRS29
100K_0402_1%
PQS10B
2N7002KDW_SOT363-6
2
1
PRS27
1M_0402_1%
2
@ PRS30
100K_0402_1%
PCS19
.1U_0402_16V7K
USBC_SW_PROCHOT
1
2
1
1
6
2
@ PQS11
2N7002KW_SOT323-3
G
H_PROCHOT#
+3VALW
3
2
2
1
S
2
1
D
2
1
2
3
1
1
USBC_SW_PROCHOT
PRS26
1M_0402_1%
PRS28
10K_0402_1%
2
@ PCS20
.1U_0402_16V7K
Issued Date
Deciphered Date
@ PR45
1M_0402_1%
1
@ PR32
3.3K_1206_5%
1
3 2
2
4
@ PR38
1M_0402_1%
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_DCIN/BATT CONN
Size
Document Number
Rev
0.1
LA-F611P
Date:
C
5
1
6
2
PQ20
2N7002KW_SOT323-3
G
Compal Secret Data
2016/01/06
26,62,66
@ PQ13B
2N7002KDW_SOT363-6
S
POK
2
D
@ PQ13A
2N7002KDW_SOT363-6
3
1
4
PC24
.1U_0402_16V7K
1
2 2
PR40
100K_0402_1%
1
PR44
1M_0402_1%
5
EC_AC_BAT#
@ PR34
1M_0402_1%
@ PR35
0_0402_5%
1
2
1
PQ11
2N7002KW_SOT323-3
G
48
@ PR31
HW_ACAV_IN 0_0402_5%
1
2
2
2
S
2
2
2
2
1
1
D
AC_SW_PROCHOT
1
2
1
2
1
PR36
1M_0402_1%
PC14
.1U_0402_16V7K
PC13
.1U_0402_16V7K
2
H_PROCHOT#
H_PROCHOT#
18,26,60,61
+3VALW
3
10,26,61,67
1
+DC_IN
+DC_IN
Erp lot6 Circuit
PQ12B
2N7002KDW_SOT363-6
asserts H_PROCHOT# when adaptor is
unplugged, keep low for 10ms
till SW PROCHOT# is issued by EC
PR33
10K_0402_1%
Bat t er y pr ot ec t i on
:
Security Classification
B
@ PC23
0.1U_0402_10V7K
PQS10A
2N7002KDW_SOT363-6
1
2
G
PQ18
2N7002KW_SOT323-3
2
2
1
2
1
1
3
1
2
3
2
3
PR9
1M_0402_5%
2
1
4
1
1
1
AC_B2B_S2_G
4
PR8
1M_0402_5%
1
PR100
1M_0402_5%
2
1
1
3
26,61
2
D
AC_B2B_S1
6
2
PBAT_CHG_SMBCLK
PR48
100K_0402_5%
+TBTA_VBUS
1
1
1
3
PR42
100_0402_5%
AC_B2B_S2
PQ17
2N7002KW_SOT323-3
asserts H_PROCHOT# when TypeC is
unplugged, keep low for 10ms
till SW PROCHOT# is issued by EC
26,61
+3VALW
AC_B2B_S2_A
2
HW_ACAVIN_NB
@ PR51
0_0402_5%
2
1
G
S
if battery removed, adaptor only,
then trigger the H_PROCHOT#,
keep @ in BOM since battery can not
be removed by end user
PBAT_PRES#
PR41
10K_0402_1%
1
2
D
PR52
0_0402_5%
2
1
(37.1)
1
PR39
200_0402_5%
1
2
PC10
0.1U_0402_50V7K
3
PR37
100_0402_5%
1
2
1
2
PR50
100K_0402_5%
AC_B2B_S2_B
PQ6
2N7002KW_SOT323-3
ESD@ PD6
TVNST52302AB0_SOT523-3
PBAT_PRES#
+SDC_IN
LM393_P
PR47
300K_0402_5%
Adapter protect i on:
1
1
ESD@ PD5
TVNST52302AB0_SOT523-3
component
+5VALW
+5VALW
61
PR43
100K_0402_1%
DAT_SMB
CLK_SMB
9538@
PC22
0.1U_0402_10V7K
1
r
o
F
SYS_PRES
AC_DIS1
2
1
2
3
4
5
6
7
8
9
10
11
12
S
2
G
PQ21
2N7002KW_SOT323-3
S
2
1
@ PD2
BAV99W_SC70-3
@ PD3
BAV99W_SC70-3
3
4
4
PIN1 GND
PIN2 GND
PIN3 GND
@ PBATT1
PIN4 SYS_PRES
1
2
PIN5 BATT_PRS
3
4
PIN6 DAT_SMB
5
PIN7 CLK_SMB
6
7
PIN8
Bat t +
4
8
PIN9 Bat t +
9
10
PIN10 Bat t +
GND
SP021412220
GND
2
Bat t er y Bot Si de
BATT++
3
EMI@ PL7
5A_Z120_25M_0805_2P
1
2
D
S
PR17
56K_0402_5%
S
PC7
0.1U_0402_50V7K
Other
2
EMI@ PC11
0.01U_0402_25V7K
2
1
BATT+
EMI@ PL4
5A_Z120_25M_0805_2P
1
2
L
L
PQ5
2N7002KW_SOT323-3
E
D
2
2
1
2
EMI@ PC12
1000P_0402_50V7K
1
D
2
G
BATT++
@ PJP3
JUMP_43X79
PQ16
2N7002KW_SOT323-3
1
HW_ACAVIN_NB
PQ15
2N7002KW_SOT323-3
1
S
AC_B2B_S1 2
G
9538@ PR46
0_0402_5%
1
2
3
BATT+
D
D
2
3
1
2
e
r
3
60,61
ACAV_IN1
2
PR22
100K_0402_5%
PR12
1M_0402_5%
G
D
G
1
2
2
2
PR2
0_0402_5%
1
2AC_B2B_S1_A2
w
e
i
v
+5VALW
@ PD7
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
AON7409_DFN8-5
1
2
3
PR11
510K_0402_5%
AC_B2B_S2
AC_B2B_ACOK
1
1
PR16
100K_0402_5%
+3.3V_ADP_DCIN
61
PQ4
5
PR10
1M_0402_5%
9538@ PR15
12K_0402_1%
95522@ PR65
0_0402_5%
1
2
2
PD10
LRB715FT1G_SOT323-3
2
1
3
AC_OK
PR63
15K_0402_5%
PC5
0.022U_0603_50V7K
2
1
1
@ PD12
DFLS160-7_POWERDI123-2
PR14
10K_0402_5%
2
2
60,61
2
9538@ PR13
100K_0402_5%
PC9
2.2U_0402_10V6M
PR62
100K_0402_5%
1
2
1
1
4
+DC_IN_SS
5
1
EN
2
NC
1
PC8
1000P_0603_50V7K
2
1
2
3
+3.3V_ADP_DCIN
26
+3VALW
@ PD4
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
AON7409_DFN8-5
1
2
3
5
AON7409_DFN8-5
1
2
3
GND
PS_ID
PR5 PSID@
2.2K_0402_5%
@ PR7
100K_0402_1%
1
2
S2
PQ3
2
G
3
E
PSID@ PR4
10K_0402_1%
2
1
2
PQ8
5
S1
PU01
RT9069-33GB_SOT23-5
1
5
VCC
OUT
PSID-3
PSID@ PQ2
LMBT3904WT1G_SC70-3
1
PSID@ PR3
100K_0402_1%
2
1
3
B
+DC_IN
+3.3V_ADP_DCIN
C
2
PSID-1
AON7409_DFN8-5
1
2
3
+DC_IN
PSID@ PR1
33_0402_5%
1
2
S
D
PQ7
2
2
EMI@ PL3
BLM15AG102SN1D_2P
1
2
PSID
3
PR6 PSID@
15K_0402_1%
2
1
ACES_51202-00901-001
1
@ESD@ PD1
TVNST52302AB0_SOT523-3
2
1
EMI@ PC4
330P_0402_50V7K
1
2
EMI@ PC3
1000P_0402_50V7K
1
2
EMI@ PC2
330P_0402_50V7K
1
2
EMI@ PC1
1000P_0402_50V7K
JUMP_43X118
EMI@ PL1
5A_Z120_25M_0805_2P
1
2
EMI@ PL5
5A_Z120_25M_0805_2P
1
2
EMI@ PL6
5A_Z120_25M_0805_2P
1
2
D
ADPIN
1
PR64
100K_0402_1%
2
1
2
PQ12A
2N7002KDW_SOT363-6
2
S
11
10
9
8
7
6
5
4
3
2
1
1
JUMP_43X118
@ PJP1
1
2
1
2
G
1
D
@ PJP4
1
@ PJPDC1
11
10
9
8
7
6
5
4
3
2
1
C
Thursday, March 22, 2018
D
Sheet
59
of
78
A
B
Main Func = Type-C PD Selector
1
TypeC@
PCS16
2.2U_0402_10V6M
2
A
r
o
F
S
3
E
D
2
1
1
1
2
2
1
2
USBC_B2B_S3
G
S
3
TypeC@ PQS07
2N7002KW_SOT323-3
TypeC@
PRS34
10K_0402_1%
3
1
EN_PD_HV_1
40
2
HW_ACAV_IN
18,26,59,61
3
4
5
1
2
3
TypeC@ PQS06
AO3409_SOT23-3
P
G
5
TypeC@ PCS13
0.1U_0402_10V7K
2
1
1
TypeC@ PCS12
0.1U_0402_10V7K
1
5
P
1
A
A
G
2
TypeC@ PRS09
499K_0402_1%
1
4
USBC_B2B_S2_G
2
2
G
S
TypeC@ PCS10
1500P_0402_50V7K
1
D
2
TypeC@ PQS03
2N7002KW_SOT323-3
GND
1
OVP_TRIP_P1
2
1
40
3
2
TypeC@ PCS15
1000P_0603_50V7K
2
1
2
VCC
TypeC@ PCS11
0.47U_0402_25V6K
1
G
TypeC@
PRS14
1M_0402_5%
TypeC@
PQS04
2N7002KW_SOT323-3
D
+3.3V_VBUS_IN
TypeC@
PRS25
1M_0402_1%
D
2
B
B
Y
3
+3.3V_VBUS_IN
VOUT
1
USBC_B2B_S1_A
TypeC@ PUS04
RT9058-33GX SOT-89 3P
6
2
TypeC@
PRS12
100K_0402_5%
2
S
+3.3V_ADP_DCIN
TypeC@
PRS15
100K_0402_5%
TypeC@
PUS02
TC7SH08FU_SSOP5
Y
TypeC@ PCS14
0.1U_0402_10V7K
2
1
G
PDS06
TypeC@
RB751V-40_SOD323-2
TypeC@
PQS08
2N7002KW_SOT323-3
4
3
D
2
1
1
TypeC@ PQS05A
2N7002KDW_SOT363-6
3
L
L
+3.3V_VBUS_IN
USBC_B2B_S1
2
4
1
USBC_B2B_S2
TypeC@
PRS10
300K_0402_1%
+3.3V_VBUS_IN
2
2
2
TypeC@ PQS05B
2N7002KDW_SOT363-6
2
TypeC@ PRS23
0_0402_5%
1
PCS23
4.7U_0603_25V6K
2
1
4
TypeC@ PRS08
499K_0402_1%
2
1
1
S
TypeC@ PRS11
49.9K_0402_1%
2
1
G
TypeC@
PQS12
2N7002KW_SOT323-3
TypeC@ PRS33
TypeC@
PDS05
0_0402_5%
RB751V-40_SOD323-2
1
2
2
1
1
TypeC@ PQS13
AO3409_SOT23-3
1
2
1
D
2
TypeC@
PRS48
1M_0402_5%
4
+SDC_IN
e
r
2
1
TypeC@
PRS38
0_0402_5%
1
2
2
TypeC@
PRS37
100K_0402_5%
3
HW_ACAVIN_NB
TypeC@ PCS09
0.47U_0603_25V7K
2
1
2
1
1
3
G
2N7002KW_SOT323-3
TypeC@ PQS21
S
2
TypeC@
PRS36
300K_0402_1%
3
59,61
@
1
AC_OK
PDS04
TypeC@ PRS32
TypeC@
RB751V-40_SOD323-2
0_0402_5%
1
2
2
1
D
1
59,61
1
2
3
5
TypeC@
PRS16
49.9K_0402_1%
2
2
+3.3V_ADP_DCIN
TypeC@
PRS46
100K_0402_5%
3
VBUS_P_CTRL_P1
1
1
4
40,60
PRS51
100K_0402_5%
+TBTA_VBUS
4
4
1
2
PQS22A
2N7002KDW_SOT363-6
TypeC@ PQS02
AON7409_DFN8-5
5
2
1
2
3
1
TypeC@ PQS20
AO3409_SOT23-3
TypeC@
PRS47
0_0402_5%
2
1
@ PCS22
0.1U_0402_10V7K
2
1
6
5
1
PQS22B
2N7002KDW_SOT363-6
2
S4
1
S
2
3
2
1
D
2
TypeC@ PQS19
2N7002KW_SOT323-3
2
USBC_B2B_S2
TypeC@ PCS21
1500P_0402_50V7K
TypeC@ PRS42
499K_0402_1%
2
1
4
1
1
1
2
3
ACAVIN_EC
3
TypeC@
PRS45
10K_0402_1%
w
e
i
v
1
2
3
5
+VBUS_DC_SS
PQS01
AON7409_DFN8-5
1
2
3
TypeC@
PRS44
300K_0402_1%
+3.3V_ADP_DCIN
TypeC@ PRS43
49.9K_0402_1%
PRS49
100K_0402_5%
HW_ACAVIN_NB_EC
TypeC_EMI@
PCS08
100P_0402_50V8J
2
1
1
2
3
5
G
26
5
4
HW_ACAVIN_NB
+3VALW_EC
PRS50
100K_0402_5%
TypeC@
PRS07
100K_0402_5%
2
1
TypeC_EMI@
PCS07
0.1U_0402_25V6
2
1
TypeC_EMI@
PCS06
1000P_0402_50V7K
2
1
1
2
G
4
PCS04
1200P_0402_50V7K
2
1
1
2
PCS03
220P_0402_50V8J~D
PCS02
100P_0402_50V8J~D
2
1
P
8
PRS03
240K_0402_1%
2
1
PRS04
102K_0402_1%
2
1
PRS06
84.5K_0402_1%
2
1
59,60,61
+TBTA_VBUS_1
TypeC@ PQS16
AON7409_DFN8-5
S3
TypeC@
+VBUS_DC_TRIP
TypeC@ PQS18
AON7409_DFN8-5
G
PRS05
23.2K_0402_1%
2
1
PRS39
0_0402_5%
1
2
1
O
-
5
1
2
3
D
+
2
PQS15
AON7409_DFN8-5
1
2
3
S
LM393_P
3
(>17.6V)
TypeC@
TypeC@ PQS17
AON7409_DFN8-5
PRS02
1K_0402_1%
PUS01A
LM393DGKR_VSSOP8
@TypeC@ PDS02
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
D
PRS01
1.8M_0402_1%
1
2
1
3
S
4
TypeC_EMI@
PCS05
100P_0402_50V8J
2
1
LM393_P
PDS01
BAT54CW_SOT323-3
2
G
1
3
+3.3V_VBUS_IN
@TypeC@ PDS07
S SCH DIO 5A 100V 15UA 0.88V TO227-3
D
+3.3V_ADP_DCIN
2
+TBTA_VBUS_1
1
2
TypeC_EMI@ PLS12
5A_Z120_25M_0805_2P
S
@ PCS01
0.01U_0402_25V7K~D
1
2
+3.3V_ADP_DCIN
TypeC_EMI@ PLS11
5A_Z120_25M_0805_2P
1
2
+TBTA_VBUS
+3.3V_ADP_DCIN
D
G
DCIN_AC_Detector
+DC_IN
C
EMI Part
TypeC@
TypeC@ PDS03
PRS40
LRB715FT1G_SOT323-3
0_0402_5%
2
2
1
HW_ACAVIN_NB
1
3
2
1
AC_OK 59,61
2
TypeC@ PRS41
0_0402_5%
1
VBUS_P_CTRL_P1
40,60
59,60,61
TypeC@ PUS03
TC7SH32FU_SSOP5
2
1
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_Type-C PD Selector
Size
Date:
B
C
Document Number
LA-F611P
Thursday, March 22, 2018
D
Sheet
60
of
Re v
0.1
78
A
B
C
D
EMI@ PLB13
5A_Z120_25M_0805_2P
1
2
+PWR_SRC
EMI@ PLB12
5A_Z120_25M_0805_2P
1
2
A
UG1_CHG
2
1
2
2
3
G1
PCB17
10U_0805_25V6K~D
2
1
PCB16
10U_0805_25V6K~D
2
1
@ PCB13
10U_0805_25V6K~D
2
1
9538@ PCB15
10U_0805_25V6K~D
2
1
2
+VCHGR
9538@ PQB03
AON7409_DFN8-5
1
2
3
5
BATT+
BGATE_CHG
@ PCB33
4700P_0402_25V7K
2
1
9538@ PCB32
10U_0805_25V6K~D
2
1
9538@ PCB31
10U_0805_25V6K~D
2
1
S2
S2
3
S2
4
6
9538@ PRB46
0_0603_5%
LG2_CHG
LX2_CHG
2
1
G2
4
4
2
3
PCB32
PQB11
LMUN5113T1G_SOT323-3
1
95522@
PCB31
3
95522@
22U_0805_25V6M
2
PRB32
2
26,62
PRB36
1
LM393_P
@ PRB37
0_0402_5%
2
0.22U_0402_25V6K
BATT+
BA_PWR 59,60
HW_ACAVIN_NB
PRB38
0_0402_5%
2
1
2
PDB04
BAT54CW_SOT323-3
3
2
1
ACAV_IN1 1
PRB40
0_0402_5%
AC_OK
1
2
5
1
PRB68
100_0402_5%
59,60
PCB44
0.1U_0402_10V7K
1
2
2
1
PRB41
0_0402_5%
2
2
B
1
BA
PUB02
TC7SH08FU_SSOP5
Y
A
BA_PWR
1
P
+3.3V_VBUS_IN
G
1
PRB66
0_0603_5%
2
1
95522@
1
2
ALWON
9538@ PRB36 1_0402_1%
1
2
@ PCB43
1
2
4
1
@
1
2_0402_5%
3
9538@
PCB41
1U_0402_25V6K
2
1
9538@ PRB32 1_0402_1%
1
2
PRB65
0_0603_5%
95522@
2
HW_ACAV_IN
4
18,26,59,60
PRB42
0_0402_5%
9538@ PRB44
0_0402_5%
PDB05 9538@
RB751V-40_SOD323-2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_CHARGER
Size
C
Document Number
Rev
0.1
LA-F611P
Date:
B
@ PCB14
10U_0805_25V6K~D
2
1
PCB12
10U_0805_25V6K~D
2
1
EMI@ PCB24
1000P_0402_50V7K
2
1
1
2
1
1
2
2
D1
1
1
JUMP_43X118
PQB10
LTC015EUBFS8TL_UMT3F
26
1
PRB12
0.01_1206_1%
@ PJPB07
1
@ PCB38
1U_0402_25V6K
1
2
0_0402_5%
2
9538@
PQB02
AON6962_DFN5X6D-8-7
22U_0805_25V6M
PCB41
2
for 95522@
0_0603_5%
0.1U_0402_25V6
9538@
UG2_CHG
1
1
G2
PRB15
@ PCB35
0.1U_0402_25V6
@EMI@ PCB37
@EMI@ PRB18
680P_0603_50V7K
4.7_1206_5%
2
1SNUB2_CHG 2
1
95522@
2
4
G2
UG1_CHG
1
G1
S2
S2
6
5
+PWR_SRC
2
TSENSE_PSYS
@ PCB45
0.1U_0402_25V6
7
2
95522@ PQB06
AON7380_DFN3X3-8-5
1
2
3
5
9538@ PLB01
2.2UH_TMPA1005S-2R2MN-D_17.5A_20%
LX1_CHG
LX2P_CHG
1
2
7
D2/S1
@EMI@ PCB36
@EMI@ PRB17
680P_0603_50V7K
4.7_1206_5%
9538@ PRB21
1
2
0_0402_5%
1
4.7UH +-20% MMD-10DZ-4R7M-X2 9.5A
1SNUB1_CHG 2
CSON_CHG
for 95522@
@ PJPB06
JUMP_43X118
2
1
PLB01
1
JUMP_43X118
BGATE_CHG
G1
S2
S2
6
5
LG1_CHG
2
D1
CSOP_CHG
32
1
PRB31
0_0402_5%
1
S2
9538@ PRB15
4.7_0603_1%
95522@ PRB57
0_0402_5%
1
2
0.22U_0603_25V7K
2
95522@
PCB40
2
1
2
4
1
95522@
LG1_CHG
BGATE
PCB30
1
2
2
@ PJPB05
1
ESD@ PD14
AZ4024-02S_SOT23
D2/S1
3
3
BGATE_CHG
31
VBAT_CHG
0_0402_5%
30
VBAT
PSYS
AMON/BMON
COMP
e
r
3
2
D1
BOOT2_CHG
95522@ PRB39
100_0402_5%
I_ADP_R
LX1_CHG
7
2
4
S2
4
2
67
I_BATT_R
4
3
PHASE1
LGATE1
9
33
95522@ PCB57 1000P_0402_25V8J
UG2_CHG
1
2 LG2_CHG
0.015U_0402_25V7K
26
1
1
2
PRB06
3.3_0603_1%
UGATE1
10
11
95522@ PRB50
2
1
100K_0402_5%
1
13
12
BOOT1
14
15
CSIN
ASGATE
PAD
LX2_CHG
5
2
3
PCB42
PQB07
AON6962_DFN5X6D-8-7
L
L
PCB29
1U_0402_6.3V6K
1
2
6
PRB33
10.5K_0402_1%
9538@ PCB42
0.01UF_0402_25V7K
95522@
CSON
2
AC_DIS
2
0_0402_5%
0.1U_0402_25V6
2
26
LG2_CHG
COMP_CHG
95522@ PCB39
560P_0402_50V7K
2
1
100_0402_5%
9538@ PRB30
499_0402_1%
2
1
r
o
F
PRB30
1
3
S
G
95522@
1
95522@ PRB59
2
1
D
16
100K_0402_1%
2
I_BATT_R
@ PQB05
2N7002KW_SOT323-3
1
2
2
VDDP_CHG
7
PRB28
95522@ PRB29
1
8
E
D
BATGONE_CHG
2
200K_0402_1% 9538@ PRB27 100K_0402_1%
1
2
VDD_CHG 1
95522@ PRB60
ACOK
29
PCB34
10P_0402_50V8J
1
2
CSOP
1
@ PRB24
100K_0402_1%
1
2
VSYS
PROCHOT#
2
PBAT_PRES#
PRB25
100K_0402_1%
2
1
1 ACOK_CHG
0_0402_5%
SCL
PROG
24
2
PRB22
BOOT2
27
23
UGATE2
SDA
1
22
2 0_0402_5%
CMIN
2
2 0_0402_5%
1 PRB19
ZTB02
CSIP
ADP
1 PRB16
+3VALW
@ PRB45
1M_0402_1%
PCB25
0.22U_0603_25V7K
2 1
2
1
21
PHASE2
CMOUT
H_PROCHOT#
2 0_0402_5%
ACIN
BATGONE
PBAT_CHG_SMBCLK
1 PRB14
LGATE2
26
2
26,59
26,59
20
VDDP
1
1
JUMP_43X118
PQB01
AON6962_DFN5X6D-8-7
VDD
25
PRB23
1M_0402_1%
1
2
3
PRB43
100K_0402_1%
2
1
AC_DIS1
PBAT_CHG_SMBDAT
19
DCIN
PRB35
0_0402_5%
2
1
2
1
PRB20
768K_0402_1%
1
3
S
G
59
26,59
10,26,59,67
ACIN_CHG
95522@ PRB13
200K_0402_1%
2
1
PRB11
499K_0402_1%
18
PRB09
4.7_0402_5%
1
2 VDD_CHG
I_ADP_R
1
PCB28
1U_0402_6.3V6K
D
17
VDD_CHG
1
PRB26
95522@ PRB10
95.3K_0402_1%
2
1 OTGEN/CMIN_CHG
2
59 ACAV_IN1
PQB04
2N7002KW_SOT323-3
2
2
1
DCIN_CHG
28
1
2
1
2
9538@ PUB01
ISL9538HRTZ-T_TQFN32_4X4
PUB01
ISL95522
LG1_CHG
PCB27
1U_0603_25V6
2
1
LX1_CHG
PRB08 150K_0402_5%
1_0805_5%
9538@ PRB07
100K_0402_5%
BYPSRC
RB751V-40_SOD323-2
9538@
PCB20
1U_0402_25V6K
95522@
UG1_CHG
1
@ PJPB04
1
D2/S1
BOOT1_CHG
95522@ PRB07
2
+DC_IN 95522@ PDB03
9538@ PCB26
0.1U_0402_25V6
2
1
ACIN_CHG
9538@ 316K_0402_1%
2
PDB02
RB751V-40_SOD323-2
47K_0402_1%
1
+SDC_IN 9538@
2
9538@ PRB34
0_0402_5%
I_BATT_R 2
1
2
95522@ PRB70
374K_0402_1%
2
1 ADP_CHG
ADP_CHG
1
95522@
2
9538@ PRB04
0_0402_5%
9538@ PRB05
442K_0402_1%
2
1
95522@ PCB56
0.1U_0402_25V6
2
1
2
+PWR_SRC
1
9538@ PRB67
0_0603_5%
2
1
9538@
PCB19
1U_0402_25V6K
+SDC_IN
PDB01
RB751V-40_SOD323-2
PRB51
95522@ PRB69
0_0603_5%
BA_PWR 2
1
CSIN_CHG
CSIP_CHG
9538@
PCB18
4.7U_0402_6.3V6M
1
2
0.1U_0402_25V6
for 9538@
2
2
PRB03
2.2_0402_1%
5
9538@
PRB02
2.2_0402_1%
PCB18
EMI@ PCB23
2200P_0402_50V7K
2
1
1
1
1
0_0402_5%
9538@ PCB11
10U_0805_25V6K~D
2
1
w
e
i
v
2
2
ESD@ PD13
AZ4024-02S_SOT23
95522@
EMI@ PCB22
2200P_0402_50V7K
2
1
1
JUMP_43X118
2
9538@ PCB10
10U_0805_25V6K~D
2
1
1
EMI@ PCB21
0.1U_0402_25V6
2
1
PRB02
2
95522@
@ PJPB03
+
3
JUMP_43X118
2
2
95522@ PRB61
0_0402_5%
2
1
JUMP_43X118
1
9538@ PCB54
10U_0805_25V6K~D
2
1
1
JUMP_43X118
@ PJPB08
2
1
2
1
PCB07
33U_D2_25VM_R40M
1
1
2
PCB05
22U_0805_25V6M
2
1
1
@ PJPB02
+CHARGER_SRC
@ PJPB01
PCB04
22U_0805_25V6M
2
1
3
PCB03
22U_0805_25V6M
2
1
4
2
@EMI@ PCB02
2200P_0402_50V7K
2
1
1
@EMI@ PCB01
0.1U_0402_25V6
2
1
+SDC_IN
95522@
EMI@ PLB11
5A_Z120_25M_0805_2P
+PWR_SRC_AC 1
2
PCB06
22U_0805_25V6M
2
1
PRB01
0.005_1206_1%
9538@ PCB53
10U_0805_25V6K~D
2
1
Main Func = CHARGER
Thursday, March 22, 2018
D
Sheet
61
of
78
A
B
C
D
E
Main Func = 3.3VALW/5VALW
w
e
i
v
1
A
PR508
1M_0402_5%
VL
2
2
+5VALW
1
2
2
1
2
3
@ PC314
22U_0805_6.3V6M
PC313
22U_0805_6.3V6M
2
1
1
5VALW
TDC=7.56 A
Peak Current 10.8 A
OCP current 13 A
@ PR510
150K_0402_1%
2
1
PC515
4.7U_0603_6.3V6M
1
5V LDO 150mA~300mA
PC514
22U_0805_6.3V6M
4.7U_0603_6.3V6M
1
+5VALWP
PC513
22U_0805_6.3V6M
2
1
21
+3VALW
JUMP_43X118
PC512
22U_0805_6.3V6M
2
1
16
PC508
1
2
2
@ PJP503
PC511
22U_0805_6.3V6M
2
1
17
2
@ PJP502
1
1
PC510
22U_0805_6.3V6M
2
1
OUT
FF
LDO
15
14
12
NC
GND
18
1
JUMP_43X118
JUMP_43X118
1
BS
IN
IN
VCC
NC
@ PJP302
1
+3VALWP
PL501
1.5UH_9A_20%_7X7X3_M
1
2
LX_5V
19
2
JUMP_43X118
+5VALWP
2
1
2
3
PG
20
1
2
@ PR511
150K_0402_1%
2
1
2
4
1
PD501
RB751V-40_SOD323-2
1
2
1
CMP_VOUT0
GND
2
r
o
F
POK
PC507
2
PC517
PR509
1000P_0402_25V8J 1K_0402_5%
5V_FB 1
2
1
2
2
ALWON
GND
11
@ PR504
10K_0402_1%
1
2
PR506
2.2K_0402_5%
1
2
PR507
0_0402_5%
1
2
26,56
+3VALWP
PC516
4.7U_0402_6.3V6M
26,61
LX
EN_5V
PR503
0_0402_5%
1
2
LX
GND
ENLDO_3V5V
EN_5V
LX
EN2
10
PR502
0_0402_5%
1
2
4
5
8
IN
IN
7
9
EN_3V
1
2
@ PJP303
1
PU501
SY8180CRAC_QFN20_3X3
E
D
LX_5V 6
13
3
PR501
0_0603_5%
1
2
0.1U_0402_10V7K
EN1
@EMI@ PC506
1000P_0402_25V8J
2
1
EMI@ PC505
0.1U_0402_25V6
2
1
PC504
10U_0805_25V6K
2
1
@EMI@ PC501
1000P_0402_25V8J
2
1
JUMP_43X79
BST_5V
PC503
10U_0805_25V6K
2
1
2
EMI@ PC502
2200P_0402_50V7K
2
1
1
5V_VIN
2
@EMI@
@EMI@
PC509
PR505
680P_0603_50V7K
4.7_1206_5%
2
15V_SN
2
1
@ PJP501
1
3VALW
TDC 6.8 A
Peak Current 9.7 A
OCP Current 11.64 A
@ PC518
22U_0805_6.3V6M
EMI@ PL511
5A_Z120_25M_0805_2P
1
2
+PWR_SRC
@ PR307
150K_0402_1%
2
1
L
L
PC315
PR306
1000P_0402_25V8J 1K_0402_5%
3V_FB
1
2
1
2
EN_3V
e
r
PC311
22U_0805_6.3V6M
2
1
2
15
PC308
4.7U_0603_6.3V6M
@ PR308
150K_0402_1%
2
1
NC
21
PC310
22U_0805_6.3V6M
2
1
16
+PWR_SRC
+3VALWP
2
+3VLP
17
@EMI@ PR305
4.7_1206_5%
1
18
GND
14
12
11
LX_3V
19
@EMI@ PC309
680P_0603_50V7K
2
1 3V_SN 2
NC
POK
PR303
150K_0402_1%
2
1
1
2
BS
3
LDO
NC
OUT
PG
PL301
1.5UH_9A_20%_7X7X3_M
1
2
ENLDO_3V5V
26,59,66
IN
4
GND
EN2
LX
GND
PR304
10K_0402_1%
1
2
+3VALWP
2
20
LX
GND
FF
9
10
PC307
0.1U_0402_10V7K
1
2
PU301
SY8288BRAC_QFN20_3X3
LX
13
8
IN
5
7
IN
IN
LX_3V 6
EN1
@EMI@ PC306
1000P_0402_25V8J
2
1
EMI@ PC305
0.1U_0402_25V6
2
1
@EMI@ PC301
1000P_0402_25V8J
2
1
PC304
4.7U_0805_25V6K
2
1
3V_VIN
2
JUMP_43X39
EMI@ PC302
2200P_0402_50V7K
2
1
1
PR301
0_0603_5%
BST_3V1
2
1
@ PJP301
PC303
4.7U_0805_25V6K
2
1
+PWR_SRC
PR302
499K_0402_1%
1
2
ENLDO_3V5V
PC312
22U_0805_6.3V6M
2
1
EMI@ PL311
5A_Z120_25M_0805_2P
1
2
1
4
2016/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2017/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_3.3VALW/5VALW
Size
C
D
R ev
0.1
LA-F611P
Date:
B
Document Number
Thursday, March 22, 2018
Sheet
E
62
of
78
A
B
C
D
Main Func = 1.2V_DDR/+0.6V_DDR_VTT
PRM02
2.2_0603_5%
2
1
@ PJPM01
1.2V_VIN
2
1
@EMI@ PRM01
4.7_1206_5%
SM_PG_CTRL
FB
6
S3
2
1
PCM21
10U_0603_6.3V6M
1
+1.2VP
PCM19
0.033U_0402_16V7K
+1.2VP
1
PRM11
100K_0402_1%
+1.2V_DDR
TDC 8.3 A
Peak Current 11.9 A
OCP Current 14.3 A
@ PCM18
.1U_0402_16V7K
2
PRM08
0_0402_5%
1
2
2
@ PCM17
220P_0402_25V8J
1
2
1
453K_0402_1%
2
VTTREF_1.2V
2
VTT
VLDOIN
2
20
19
18
BOOT
S5
5
FB_1.2V
TON_1.2V
4
PRM10
60.4K_0402_1%
1
2
PRM07
2
@ PCM15
0.1U_0402_10V7K
E
D
10
3
2
1.2V_VDDQ_EN
1.2V_VIN 1
2
PRM09
0_0402_5%
1
2
@ PJPM04
1
@ PCM16
0.1U_0402_10V7K
1
2
2
3
JUMP_43X118
@ PJPM02
2
37
+1.2VP
1
1
2
2
+1.2V_DDR
JUMP_43X118
4
r
o
F
A
@EMI@ PCM11
680P_0402_50V7K
2
1
2
PCM10
22U_0603_6.3V6M
1
2
1
PCM09
22U_0603_6.3V6M
2
1
PCM08
22U_0603_6.3V6M
2
PCM07
22U_0603_6.3V6M
1
2
1
PCM06
22U_0603_6.3V6M
2
1
2
PCM05
22U_0603_6.3V6M
+1.2VP
@
1
1
@ PRM06
10K_0402_1%
1
2
+3VALW
PLM01
1UH_11A_20%_7X7X3_M
1
2
17
10
2
L
L
+5VALW
1
1
1
2
PCM14
1U_0603_10V6K
PRM05
2.2_0603_5%
VDDQ
7
VDD
21
e
r
VTTREF
1
+5VALW
2
UGATE
VDDP
8
11
GND
RT8207PGQW _W QFN20_3X3
EN_0.6VSP
VDD_1.2V
CS
TON
12
VTTSNS
9
PRM04
5.1_0603_5%
1
2
13
PCM13
1U_0603_10V6K
2
1
PAD
VTTGND
PGND
EN_1.2V
9
CS_1.2V
LGATE
PGOOD
1
2
D1
G1
3
14
PRM03
15.4K_0402_1%
2
1
G2
S2
7
15
8
D1
5
D2/S1
S2
D1
S2
10
6
PQM01
AONH36334_DFN3X3A8-10
D1
4
LG_1.2V
PHASE
PUM01
16
1
LX_1.2V
PCM20
10U_0603_6.3V6M
PCM04
4.7U_0805_25V6K
PCM03
4.7U_0805_25V6K
2
1
EMI@ PCM02
2200P_0402_50V7K
2
1
EMI@ PCM01
0.1U_0402_25V6
2
1
2
1
@EMI@ PCM22
1000P_0402_50V7K
2
1
+PWR_SRC JUMP_43X39
3
w
e
i
v
UG_1.2V
+0.6VSP
@EMI@ PCM23
1000P_0402_50V7K
2
1
1
0.6Volt +/- 5%
TDC 1.2A
Peak Current 1.5A
+1.2VP
PCM12
0.1U_0402_10V7K
2
EMI@ PLM11
5A_Z120_25M_0805_2P
1
2
1
BST_1.2V
1
BST_1.2V_R
@ PJPM03
+0.6VSP
1
2
+0.6V_DDR_VTT
JUMP_43X39
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_+1.2V_DDR/+0.6V_DDR_VTT
Size
C
Rev
0.1
LA-F611P
Date:
B
Document Number
Sheet
Thursday, March 22, 2018
D
63
of
78
5
4
3
2
1
Main Func = VCCIO
+VCCIO (0.95V)
TDC 4.5 A
Peak Current 6.4 A
OCP Current 9 A Fix by IC
EMI@ PL911
5A_Z120_25M_0805_2P
1
2
1
2
ILMT
NC
BYP
NC
PAD
10
12
16
21
Rup
SY8286RAC_QFN20_3X3
2
1
2
1
L
L
B
5
r
o
F
4
2
+VCCIO
D
Rdown
FB_VCCIO_SENSE
1
2
PC916
22U_0603_6.3V6M
1
2
1
e
r
PR909
21K_0402_1%
2
1
PR910
35.7K_0402_1%
ILMT_VCCIO
@ PR906
0_0402_5%
A
1
@EMI@ PC911
680P_0603_50V7K
PC915
22U_0603_6.3V6M
VCC_VCCIO
2
NC
17
PC914
22U_0603_6.3V6M
EN
FB_VCCIO
14
@ PR905
0_0402_5%
C
2
+VCCIOP
@EMI@ PR907
4.7_1206_5%
2
VCC
20
PL901
1UH_PCMB042T-1R0MS_4.5A_20%
1
2
PR908
10_0402_1%
2
1
GND
LX_VCCIO
19
1
FB
PC907
0.1U_0603_25V7K
1
2
2
LX
GND
BST_VCCIO
PC912
330P_0402_50V7K
GND
PR902
0_0603_5%
2
1
LX
1
2
IN
BS_VCCIO
6
1
PC909
1U_0603_6.3V6M
LX
1
2
+3VALW
IN
9
1
1
15
+3VALW
BS
2
11
13
PR904
1M_0402_1%
2
@ PR913
0_0402_5%
2
1
EN_VCCSTG_VCCPLL_OC
@ PC908
0.22U_0402_10V6K
2
EN_VCCIO
PG
IN
SNB_VCCIO
1
36
18
IN
1
4
2
3
PC910
2.2U_0402_16V6K
2
8
VCCIO_EN
1
JUMP_43X118
7
37
1
PU901
5
PR903
0_0402_5%
1
2
w
e
i
v
@ PJP902
+VCCIOP
PC906
10U_0805_25V6K
PC905
10U_0805_25V6K
2
1
1
2
EMI@ PC904
0.1U_0402_25V6
2
1
2
EMI@ PC903
2200P_0402_50V7K
2
1
2
JUMP_43X39
@EMI@ PC902
1000P_0402_50V7K
2
1
1
+3VS
VIN_VCCIO
@EMI@ PC901
1000P_0402_50V7K
2
1
1
@ PR901
10K_0402_5%
2
1
+VCCIO_PG
PC913
22U_0603_6.3V6M
@ PJP901
+PWR_SRC
D
18
PR911
0_0402_5%
1
2
VCCIO_SENSE
12
PR912
0_0402_5%
1
2
VSSIO_SENSE
12
E
D
C
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_+VCCIO
Size
2
Rev
0.1
LA-F611P
Date:
3
Document Number
Thursday, March 22, 2018
Sheet
1
64
of
78
5
4
3
2
1
Main Func = 1.05VALW
@ PJPH01
2
1
JUMP_43X39
w
e
i
v
2
E
D
B
5
r
o
F
@EMI@ PCH07
1000P_0402_50V7K
2
1
@EMI@ PCH06
1000P_0402_50V7K
2
1
1
PLH01
1UH_11A_20%_7X7X3_M
1
2
+1.05VP
+
SNUB_+1.05V
2
@EMI@ PCH12
680P_0402_50V7K
1
+
2
C
PCH14
220U_D2 SX_2VY_R9M
1
@EMI@ PRH06
4.7_1206_5%
PCH13
220U_D2 SX_2VY_R9M
1
L
L
1
PRH13
10K_0402_1%
A
G1
PCH10
1U_0603_6.3V6M
PRH10
4.99K_0402_1%
1
2
e
r
1
TPS51212DSCR_SON10_3X3
2
11
2
+5VALW
LG_+1.05V
1
6
G2
7
7
D
+PWR_SRC
+1.05VP
TDC=7.6A
Ipeak=10.8A
OCP=13A
2
TP
PRH05
470K_0402_1%
D2/S1
S2
DRVL
LX_+1.05V
PQH01
AON6962_DFN5X6D-8-7
6
V5IN
TST
UG_+1.05V
8
5
VFB
9
D1
5
SW
S2
4
RF_+1.30V
DRVH
EN
S2
FB_+1.05V
TRIP
PRH02
PCH08
2.2_0603_5%
0.1U_0603_25V7K
1
2BST_+1.05V 1
2
4
3
2
VBST
VBST_+1.05V
3
EN_+1.05V
PGOOD
10
2
2
C
1
1
2
@ PRH04
0_0402_5%
1
2
PUH01
PRH03
22.1K_0402_1%
1
2 TRIP_+1.05V
1
PRIM_PW RGD_R
1
26,66
PCH_PRIM_EN
PRH01
100K_0402_1%
2
21,26,37,66
PRH14
10K_0402_1%
1
2
1V05PRIM_PG
PCH09
0.1U_0402_16V7K
26
2
1
PCH03
10U_0805_25V6K~D
2
1
2
1
2
+3VALW
EMI@ PCH02
2200P_0402_50V7K
1
EMI@ PCH01
0.1U_0402_25V6
VIN_+1.05V
PCH04
10U_0805_25V6K~D
EMI@ PLH11
5A_Z120_25M_0805_2P
2
1
D
@ PJPH02
1
+1.05VP
1
2
2
+1.05VALW
JUMP_43X118
B
@ PJPH03
1
1
2
2
JUMP_43X118
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR-1.05VALW
Size
3
2
Rev
0.1
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
65
of
78
A
B
C
D
Main Func = +1.8V_PRIM/+2.5V_MEM
w
e
i
v
@ PL1811
5A_Z120_25M_0805_2P
1
2
1
POK
1
2
2
@ PR1802
1M_0402_5%
2
+3VALW
@EMI@ PC1806
680P_0402_50V7K
1
PR1807
20K_0402_1%
PR1805
10K_0402_1%
FB_1.8VALW
2
+2.5VP
SIO_SLP_S4#
A
PGOOD
GND
7
ADJ_2.5V
1
1
E
D
8
PR2502
21.5K_0402_1%
2
PU2501
RT9059GSP_SO8
r
o
F
1
+1.8V_PRIM
TDC 1.4 A
Peak Current 2 A
OCP Current 3.5A f i x by I C
e
r
2
@ PJP2502
1
2
JUMP_43X39
+2.5V_MEM
+2.5VP
6
PR2503
10K_0402_1%
@ PC2505
0.01U_0402_25V7K
1
ADJ
2
EN
5
PC2502
10U_0805_10V6K
VOUT
2
1
EN_2.5V
2
4
2
NC
VIN
1
PR2501
0_0402_5%
1
2
1
18,37
VDD
3
2
1
2
3
PC2501
10U_0805_10V6K
JUMP_43X39
2.5V_VIN
2
@ PC2503
0.1U_0402_10V6K
1
GND
9
2
PC2504
1U_0402_6.3V6K
4
@ PJP2501
+3VALW
L
L
2
PR2504
2.2_0402_1%
1
1
+5VALW
PC1804
22U_0603_6.3V6M
1
22P_0402_50V8J
PC1803
22U_0603_6.3V6M
2
1
@EMI@ PR1804
4.7_1206_5%
PC1807
2
PR1803
100K_0402_5%
@ PR1801
0_0402_5%
1
2
1
26,59,62
5
+1.8V_PRIM
+1.8VALWP
26,65
PC1802
22U_0603_6.3V6M
2
1
EN
PRIM_PWRGD_R
1
FB
RT8061AZQW_WDFN10_3X3
PR1806
0_0402_5%
PCH_PRIM_EN
1
2
4
2
PGOOD
3
1
NC
LX_1.8VALW
2
1
21,26,37,65
LX
2
6
LX
SVIN
1
PC1801
22U_0603_6.3V6M
2
1
7
PVIN
2
8
2
9
PL1801
1UH_6.6A_20%_5X5X3_M
1
2
2
2
JUMP_43X39
1
PC1805
0.1U_0402_10V7K
1
NC
1
@ PJP1801
+3VALW
TP
PVIN
EN_1.8VALW
11
10
@ PJP1802
JUMP_43X79
1
2
1
2
+1.8VALWP
PU1801
+2.5V
TDC 0.5 A
Peak Current 0.62 A
3
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_+1.8V_PRIM/+2.5V_MEM
Size
B
C
Document Number
Rev
0.1
LA-F611P
Date:
Thursday, March 22, 2018
D
Sheet
66
of
78
5
4
3
2
1
Main Func = VCORE
2
PRZ10
0_0402_5%
1
118
2
1
1
2
1
2
VR_ON
18
PRZ40
0_0402_5%
1
2
PCZ20
PRZ41
1000P_0402_50V7K
1.37K_0402_1%
1
2
1
2
2
PCZ05
2200P_0402_50V7K
@ PRZ74
100K_0402_1%
CSP3_4PH
@ PRZ75
100K_0402_1%
1
CSREF_4PH
5
PWM3_4PH/VBOOT
69
PWM4_4PH/ROSCM
PCZ31
0.1U_0402_25V6
1
2
1
2
1
PRZ23
45.3_0402_1%
2
1
PRZ45
PCZ23
49.9_0402_1% 470P_0402_50V8J
1
2
1
2
2
1
PCZ24
15P_0402_50V8J
1
2
1
PRZ46
1K_0402_1%
PCZ28
680P_0402_50V7K
2
1
PCZ27
100P_0402_50V8J
2
1
1
2
PCZ26
0.22U_0402_25V6K
TSENSE_PSYS
11
2
PRZ47
3.65K_0402_1%
1
2
PCZ25
2200P_0402_50V7K
C
CSCOMP_2PH
PHZ02
220K_0402_5%_ERTJ0EV224J
PRZ51
88.7K_0603_1%
1
2
SW1_2PH
67,70
61
PRZ58
24.9K_0402_1%
1
2
PWM2_2PH/ROSC1
CSREF_2PH
CSREF_2PH
70
2
PRZ59
25.5K_0402_1%
70
PRZ60
1.62K_0402_1%
1
2
CSP1_2PH
SW1_2PH
67,70
2
PWM1_2PH/ICCMAX2
PCZ33
0.1U_0402_25V6
CSREF_2PH
B
TSENSE_2PH
1
1
1
PRZ67
61.9K_0402_1%
PHZ04
PRZ69
61.9K_0402_1%
220K_0402_5%_ERTJ0EV224J
2
2
PHZ03
220K_0402_5%_ERTJ0EV224J
+5VALW
VSSGT_SENSE
PRZ68
0_0402_5%
2
1
2
1
@ PRZ76
100K_0402_1%
1
A
69
1
@ PRZ77
1K_0402_1%
TSENSE_4PH
CSP4_4PH
r
o
F
PCZ37
0.1U_0402_25V6
CSREF_4PH
PWM2_4PH/ADDR
+5VALW
CSP4_4PH
PRZ66
0_0402_5%
2
1
PRZ64
1.62K_0402_1%
1
2
SW4_4PH
2
67,69
PWM1_4PH/ICCMAX4
1
11
10
10
1
1
PCZ36
0.1U_0402_25V6
2
SW3_4PH
CSP1_2PH
2
2
12.1K_0402_1%
VCCGT_SENSE
D
2
PRZ63
1.62K_0402_1%
1
2
2
67,69
1
CSREF_4PH
1
PRZ48
CSSUM_2PH
1
68
DIFFOUT_2PH
FB_2PH
COMP_2PH
ILIM_2PH
PRZ72
97.6K_0402_1%
2
1
1
CSP2_4PH
1
PCZ35
0.1U_0402_25V6
B
68
2
SW2_4PH
2
67,68
DRVON
E
D
CSREF_4PH
PRZ62
1.62K_0402_1%
1
2
68,69,70
2
@ PRZ73
100K_0402_1%
1
PCZ34
0.1U_0402_25V6
2
PRZ53
2.2_0603_5%
2
SW1_4PH
2
67,68
CSP1_4PH
VSP_2PH
VSN_2PH
2
PRZ57
97.6K_0402_1%
2
1
1
+5VALW
PRZ61
1.62K_0402_1%
1
2
PRZ44
31.6K_0402_1%
1
2
PCZ22
470P_0402_50V8J
1
2
81215_VR_HOT
PRZ71
1K_0402_1%
TSENSE_2PH
e
r
PRZ42
0_0402_5%
2
PCZ21
2200P_0402_50V7K
L
L
PCZ29
0.1U_0402_25V6
2
1 TSENSE_4PH
PCZ30
0.01U_0402_50V7K
1
2
PRZ56
24.9K_0402_1%
2
1
2
1
1
2
1
1 2
2
1
CPU_B+
CSREF_4PH
39
38
37
36
35
34
33
32
31
30
29
28
27
VRHOT#
VSP_2PH
VSN_2PH
IMON_2PH
DIFFOUT_2PH
FB_2PH
COMP_2PH
ILIM_2PH
CSCOMP_2PH
CSSUM_2PH
CSREF_2PH
CSP1_2PH
CSP2_2PH
14
15
16
17
18
19
20
21
22
23
24
25
26
CSREF_4PH
PRZ54
100K_0402_1%
2
1
SW4_4PH
68,69
PCZ32
1U_0603_10V6K
67,69
PRZ52
1K_0402_1%
1
2
2
SW3_4PH
CSP1_4PH
CSP2_4PH
CSP3_4PH
PCZ19
0.22U_0402_25V6K
1
67,69
PCZ18
680P_0402_50V7K
SW2_4PH
PCZ17
100P_0402_50V8J
67,68
ILIM_4PH
2
27.4K_0402_1%
VSP_4PH
VSN_4PH
IMON_4PH
DIFFOUT_4PH
FB_4PH
COMP_4PH
ILIM_4PH
CSCOMP_4PH
CSSUM_4PH
CSREF_4PH
CSP1_4PH
CSP2_4PH
CSP3_4PH
2
SW1_4PH
PRZ34
158K_0402_1%
67,68
PRZ35
115K_0603_1%
1
2
PRZ36
115K_0603_1%
1
2
PRZ37
115K_0603_1%
1
2
PRZ38
115K_0603_1%
1
2
PRZ33
75K_0402_1%
1
2
PHZ01
220K_0402_5%_ERTJ0EV224J
1
PRZ32
1
2
3
4
5
6
7
8
9
10
11
12
13
DIFFOUT_4PH
FB_4PH
COMP_4PH
C
CSCOMP_4PH
CSSUM_4PH
52
51
50
49
48
47
46
45
44
43
42
41
40
53
VSP_4PH
VSN_4PH
PCZ16
470P_0402_50V8J
2
1
1
PUZ01
NCP81215MNTXG_QFN52_6X6
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH
VR_RDY
PWM_1PH/ICCMAX_1PH
EN
SCLK
ALERT#
SDIO
2
PCZ15
2200P_0402_50V7K
PRZ55
4.32K_0402_1%
2
1
1
PRZ31
25.5K_0402_1%
2
1
PRZ30
1K_0402_1%
1
2
TAB
PRZ29
3.65K_0402_1%
1
2
PRZ28
PCZ14
49.9_0402_1% 470P_0402_50V8J
1
2 1
2
TSENSE_4PH
VRMP
VCC
DRON
PWM1_4PH/ICCMAX_4PH
PWM2_4PH/ADDR
PWM3_4PH/VBOOT
PWM4_4PH/ROSC_MPH
PWM2_2PH/ROSC_1PH
PWM1_2PH/ICCMAX_2PH
TTSENSE_1PH/PSYS
TTSENSE_2PH
CSP4_4PH
PCZ13
15P_0402_50V8J
1
2
PRZ22
45.3_0402_1%
2
1
VR_SVID_DATA
PRZ19
0_0402_5%
VSP_1PH
PRZ21
100_0402_1%
1
2
PRZ20
499_0402_1%
2
1
VR_SVID_ALERT#
2
10_0402_1%
1
PRZ27
VSN_1PH
2
w
e
i
v
1
0_0402_5%
81215_SDIO
1
1
VSS_SENSE
IMVP_VR_PG
PCZ11
100P_0402_50V8J
PRZ11
1.69K_0402_1%
1
2 VSN_4PH
10
81215_ALERT 2
PRZ26
1
11
1
PCZ04
1000P_0402_50V7K
10,26,59,61
VR_SVID_CLK
1
PRZ25
70
PRZ18
34.8K_0402_1%
81215_SCLK
81215_ALERT
81215_SDIO
2
H_PROCHOT#
2
49.9_0402_1%
81215_SCLK
PWM1_1PH/ICCMAX1
PCZ12
10U_0402_6.3V6M
2
1
PRZ24
100_0402_1%
81215_VR_HOT
1
2
+3VS
PRZ17
10K_0402_1%
VSP_4PH
@
PRZ50
165K_0402_1%
PRZ08
0_0402_5%
1
2
VCC_SENSE
PRZ15
12.4K_0402_1%
2
1
PRZ16
PCZ10
1.5K_0402_1% 0.01U_0402_25V7K
2
1
2
1
2
11
IMON_1PH
PCZ03
1000P_0402_50V7K
2
2
PRZ14
29.4K_0402_1%
1
PCZ09
1000P_0402_50V7K
1
2
1
@ PCZ07
2200P_0402_50V7K
CSN_1PH_R
CSP_1PH
PCZ38
3300P_0402_25V7K
@
2
PCZ08
470P_0402_50V8J
1
2
1
PRZ06
1.58K_0402_1%
VSP_1PH
1
2
1
2
2
2
PRZ05
0_0402_5%
D
+VCCST
70
COMP_1PH
ILIM_1PH
1
VCC_SA_SENSE
1
PCZ02
1000P_0402_50V7K
12
SW_1PH
PCZ06
0.01UF_0402_25V7K
1
2
PRZ70
10_0402_1%
PRZ03
1.21K_0402_1%
VSN_1PH
1
2
PRZ13
7.5K_0603_1%
1
2
2
VSS_SA_SENSE
PHZ05
PRZ12
100K_0402_1%_TSM0B104F4251RZ
12K_0402_1%
1
2 1
2
CSN_1PH
2
12
PRZ02
0_0402_5%
1
2
70
PRZ49
75K_0402_1%
1 2
1
PCZ01
2200P_0402_50V7K
1
2
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
4
3
2
+VCORE_NCP81215
Document Number
Rev
0.1
LA-F611P
Date:
Thursday, March 22, 2018
1
Sheet
67
of
78
5
4
3
2
1
CPU_B+
D
2
PRI01
2_0603_5%
1
2
1
PCI14
1U_0603_25V7K
PCI16
PUI01
2
PCI15
2.2U_0603_10V7K
+5VALW
4
10
14
13
19
C
VIN
VIN
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
CGND
PGND
PGND
GL
GL
SW
SW
8
9
2
1
PRI02
3.9_0603_1%
NC
AGND
2
e
r
6
18
EMI@
PRI04
1_1206_5%
1
2
1
PCI24
1U_0603_25V7K
17
16
1
2
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
8
9
5
7
r
o
F
+5VALW
4
10
14
13
19
CGND
PGND
PGND
GL
GL
SW
SW
NC
AGND
5
6
18
EMI@
PRI08
1_1206_5%
1
2
@ PCI13
10U_0805_25VAK
4
2
3
+VCC_CORE
PRI03
10_0402_1%
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
2
CSREF_4PH
SW1_4PH
67,68,69
C
67
2
EMI@
PCI17
2200P_0603_50V7K
@EMI@ PCI49
1000P_0402_50V7K
1
2
1
2
@EMI@ PCI48
1000P_0402_50V7K
1
2
@ PCI22
10U_0805_25VAK
1
2
1
PCI21
10U_0805_25VAK
2
1
PCI20
10U_0805_25VAK
2
EMI@ PCI19
0.1U_0402_25V7K
1
CORE_SW2
11
12
2
1
NCP302045MNTXG_PQFN33_5X5
A
2
0.22U_0603_25V7K
1
2
67,68,69,70 DRVON
67 PWM2_4PH/ADDR
VIN
VIN
1
B
PLI02
1
4
2
3
+VCC_CORE
PRI07
10_0402_1%
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
2
CSREF_4PH
67,68,69
2
1
PCI25
2.2U_0603_10V7K
VCC
VCCD
PCI26
1
@ PCI23
10U_0805_25VAK
L
L
E
D
PRI06
3.9_0603_1%
1
2
PUI02
3
15
2
1
2
PRI05
2_0603_5%
1
2
B
EMI@ PCI18
2200P_0402_50V7K
+5VALW
1
PLI01
CORE_SW1
11
12
NCP302045MNTXG_PQFN33_5X5
CPU_B+
D
0.22U_0603_25V7K
5
7
1
1
17
16
1
2
67,68,69,70 DRVON
67 PWM1_4PH/ICCMAX4
1
VCC
VCCD
2
3
15
2
w
e
i
v
+5VALW
+VCC_CORE
TDC PL2 :80A
Peak Current 128A
OCP Current 154A
DCR 0.9mohm +/-5%
Load Line 1.8mV/A
@ PCI12
10U_0805_25VAK
1
PCI11
10U_0805_25VAK
2
1
PCI10
10U_0805_25VAK
2
1
2
2
1
+
EMI@ PCI09
0.1U_0402_25V7K
2
1
2
+
EMI@ PCI08
2200P_0402_50V7K
2
1
PCI07
33U_D2_25VM_R40M
+
PCI06
33U_D2_25VM_R40M
1
PCI05
33U_D2_25VM_R40M
2
2
1
FBMA-L11-453215800LMA90T_2P
1
2
@EMI@ PCI04
1000P_0402_50V7K
EMI@ PLI11
1
+PWR_SRC
@EMI@ PCI03
1000P_0402_50V7K
Main Func = CORE_Phase1&2
SW2_4PH
EMI@
PCI27
2200P_0603_50V7K
67
A
2016/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
+VCC_CORE_Phase1&2
Size
3
2
Rev
0.1
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
68
of
78
5
4
3
2
1
1
PCI34
1U_0603_25V7K
PRI10
3.9_0603_1%
1
2
PUI03
2
PCI35
2.2U_0603_10V7K
67,68,69,70 DRVON
67 PWM3_4PH/VBOOT
+5VALW
4
10
14
13
19
VCC
VCCD
VIN
VIN
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
CGND
PGND
PGND
GL
GL
SW
SW
5
7
PLI03
CORE_SW3
11
12
1
2
NC
AGND
1
C
67,68,69,70 DRVON
67 PWM4_4PH/ROSCM
2
17
16
1
2
4
10
14
13
19
VCC
VCCD
VIN
VIN
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
CGND
PGND
PGND
GL
GL
SW
SW
5
NC
AGND
1
2
@EMI@ PCI53
1000P_0402_50V7K
2
1
@EMI@ PCI52
1000P_0402_50V7K
1
2
2
EMI@
PCI37
2200P_0603_50V7K
1
1
@EMI@ PCI50
1000P_0402_50V7K
1
@EMI@ PCI51
1000P_0402_50V7K
CSREF_4PH
2
2
2
SW3_4PH
67,68,69
67
C
B
PLI04
CORE_SW4
11
12
1
2
6
18
1
2
r
o
F
PCI43
10U_0805_25VAK
1
2
PCI42
10U_0805_25VAK
@ PCI41
10U_0805_25VAK
1
1
2
1
@ PCI40
10U_0805_25VAK
2
1
0.22U_0603_25V7K
5
7
NCP302045MNTXG_PQFN33_5X5
A
PCI46
E
D
8
9
1
1
B
+5VALW
2
PRI14
3.9_0603_1%
1
2
3
PRI11
10_0402_1%
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
2
EMI@
PRI16
1_1206_5%
+VCC_CORE
4
3
PRI15
10_0402_1%
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
2
CSREF_4PH
67,68,69
2
3
15
2.2U_0603_10V7K
L
L
PCI44
1U_0603_25V7K
PUI04
PCI45
EMI@ PCI39
0.1U_0402_25V7K
1
1
2
2
PRI13
2_0603_5%
2
EMI@ PCI38
2200P_0402_50V7K
2
CPU_B+
1
EMI@
PRI12
1_1206_5%
D
+VCC_CORE
4
e
r
6
18
NCP302045MNTXG_PQFN33_5X5
+5VALW
@ PCI33
10U_0805_25VAK
1
2
8
9
1
1
17
16
1
2
PCI36
0.22U_0603_25V7K
1
2
2
3
15
@ PCI32
10U_0805_25VAK
1
2
PCI31
10U_0805_25VAK
1
2
1
2
w
e
i
v
2
PCI30
10U_0805_25VAK
PRI09
2_0603_5%
1
2
D
EMI@ PCI29
0.1U_0402_25V7K
1
2
+5VALW
EMI@ PCI28
2200P_0402_50V7K
CPU_B+
Main Func = CORE_Phase3&4
SW4_4PH
67
EMI@
PCI47
2200P_0603_50V7K
A
2016/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
+VCC_CORE_Phase3&4
Size
4
3
2
Document Number
Rev
0.1
LA-F611P
Date:
Thursday, March 22, 2018
Sheet
1
69
of
78
5
4
3
2
1
+5VALW
4
10
14
13
19
VIN
VIN
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
CGND
PGND
PGND
GL
GL
SW
SW
8
9
NC
AGND
2
PCA08
2.2U_0603_10V7K
4
10
14
13
19
VCC
VCCD
VIN
VIN
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
CGND
PGND
PGND
GL
GL
SW
SW
NC
AGND
2
E
D
PRA02
3.9_0603_1%
5
7
5
2
0.22U_0603_25V7K
SA_SW
11
12
1
2
6
18
1
2
@EMI@ PCA12
1000P_0402_50V7K
1
2
EMI@
PRG04
1_1206_5%
1
@EMI@PCG12
1000P_0402_50V7K
1
@EMI@PCG11
1000P_0402_50V7K
1
@PCG06
10U_0805_25VAK
1
EMI@
PCG10
2200P_0603_50V7K
CSREF_2PH
2
2
2
SW1_2PH
67
67
C
+VCCSA
TDC PL2 :10A
Peak Current 11A
OCP Current 13A
DCR 6.2mohm +/-5%
Load Line 10.3mV/A
B
+VCCSA
4
3
EMI@
PRA04
1_1206_5%
2
1
2
r
o
F
3
PRG03
10_0402_1%
0.15UH_MMD-06CZER15MEX5L__35A_20%
1
2
PLA01
0.47UH_MMD05CZR47M_12A_20%
NCP302035MNTXG_PQFN33_5X5
A
1
+VCCGT
4
e
r
1
67,68,69,70 DRVON
67 PWM1_1PH/ICCMAX1
17
16
1
2
2
1
1
B
1
8
9
@EMI@ PCA11
1000P_0402_50V7K
1
2
PCA09
PUA01
@ PCA06
10U_0805_25VAK
1
2
@ PCA05
10U_0805_25VAK
PCA04
10U_0805_25VAK
1
2
1
2
PCA03
10U_0805_25VAK
1
2
EMI@ PCA02
0.1U_0402_25V7K
1
2
1
PCA07
1U_0603_25V7K
3
15
2
1
2
L
L
2
EMI@ PCA01
2200P_0402_50V7K
2
1
PLG01
6
18
D
0.22U_0603_25V7K
GT_SW1
11
12
CPU_B+
2_0603_5%
2
5
7
C
PRA01
1
PRG02
3.9_0603_1%
NCP302045MNTXG_PQFN33_5X5
+5VALW
2
1
2
2
1
67,68,69,70 DRVON
PWM1_2PH/ICCMAX2
1
VCC
VCCD
2
17
16
1
2
1
2
1
PCG09
PUG01
67
2
PCG07
1U_0603_25V7K
3
15
PCG08
2.2U_0603_10V7K
w
e
i
v
2
2_0603_5%
@PCG05
10U_0805_25VAK
2
PCG04
10U_0805_25VAK
PRG01
1
+VCCGT
TDC PL2 :25A
Peak Current 32A
OCP Current 39A
DCR 0.9mohm +/-5%
Load Line 2.7mV/A
PCG03
10U_0805_25VAK
D
EMI@ PCG02
0.1U_0402_25V7K
2
1
+5VALW
EMI@ PCG01
2200P_0402_50V7K
CPU_B+
Main Func = VCCGT/+VCCSA
1
1
SW_1PH
CSN_1PH
67
67
EMI@
PCA10
2200P_0603_50V7K
A
2016/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
+VCC_GT/+VCC_SA
Size
3
2
Rev
0.1
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
70
of
78
2
4
A
PCG114
10U_0402_6.3V6M
2
1
PCG115
10U_0402_6.3V6M
2
1
PCG116
10U_0402_6.3V6M
2
1
PCG117
10U_0402_6.3V6M
2
1
PCG118
10U_0402_6.3V6M
2
1
PCG124
1U_0201_6.3V6M
2
1
PCG125
1U_0201_6.3V6M
2
1
PCG126
1U_0201_6.3V6M
2
1
PCG127
1U_0201_6.3V6M
2
1
PCG128
1U_0201_6.3V6M
2
1
r
o
F
PCG113
10U_0402_6.3V6M
2
1
3
PCG123
1U_0201_6.3V6M
2
1
B
E
D
PCG132
1U_0201_6.3V6M
PCG131
1U_0201_6.3V6M
2
1
2
PCG110
22U_0603_6.3V6M
1
2
1
C
Issued Date
Security Classification
2016/01/06
PCA113
10U_0402_6.3V6M
+VCCSA
PCA112
10U_0402_6.3V6M
2
1
2
PCA111
10U_0402_6.3V6M
2
1
PCA104
47U_0805_6.3V6M
1
1
PCA110
10U_0402_6.3V6M
2
1
2
2
PCA102
47U_0805_6.3V6M
1
PCA103
47U_0805_6.3V6M
PCA106
22U_0603_6.3V6M
PCA108
10U_0402_6.3V6M
2
1
2
PCA101
47U_0805_6.3V6M
PCA109
10U_0402_6.3V6M
2
1
PCA105
22U_0603_6.3V6M
2
1
PCA107
10U_0402_6.3V6M
2
1
2
+VCCGT
1
+VCCSA
47uF*4
22uF*2
10uF*7
L
L
1
PCI129
22U_0603_6.3V6M
2
1
PCI130
22U_0603_6.3V6M
2
1
PCI131
22U_0603_6.3V6M
2
1
PCI132
22U_0603_6.3V6M
2
1
PCI133
22U_0603_6.3V6M
2
1
@ PCI134
22U_0603_6.3V6M
2
1
@ PCI135
22U_0603_6.3V6M
2
1
@ PCI136
22U_0603_6.3V6M
PCI149
1U_0201_6.3V6M
2
1
PCI150
1U_0201_6.3V6M
2
1
PCI151
1U_0201_6.3V6M
2
1
PCI152
1U_0201_6.3V6M
2
1
PCI153
1U_0201_6.3V6M
2
1
PCI154
1U_0201_6.3V6M
2
1
PCI155
1U_0201_6.3V6M
2
1
PCI156
1U_0201_6.3V6M
2
1
PCI140
47U_0805_6.3V6M
PCI141
47U_0805_6.3V6M
PCI162
1U_0201_6.3V6M
2
1
PCI120
10U_0402_6.3V6M
2
1
PCI165
1U_0201_6.3V6M
PCI121
10U_0402_6.3V6M
PCI119
10U_0402_6.3V6M
2
1
PCI164
1U_0201_6.3V6M
2
1
PCI117
10U_0402_6.3V6M
2
1
PCI116
10U_0402_6.3V6M
2
1
PCI115
10U_0402_6.3V6M
2
1
PCI114
10U_0402_6.3V6M
2
1
PCI113
10U_0402_6.3V6M
2
1
PCI112
10U_0402_6.3V6M
2
1
PCI111
10U_0402_6.3V6M
2
1
PCI110
10U_0402_6.3V6M
2
1
PCI109
10U_0402_6.3V6M
2
1
PCI108
10U_0402_6.3V6M
2
1
PCI107
10U_0402_6.3V6M
2
1
PCI106
10U_0402_6.3V6M
2
1
PCI105
10U_0402_6.3V6M
2
1
PCI104
10U_0402_6.3V6M
2
1
PCI103
10U_0402_6.3V6M
2
1
PCI102
10U_0402_6.3V6M
2
1
PCI118
10U_0402_6.3V6M
2
1
1
1
PCI163
1U_0201_6.3V6M
2
1
2
1
PCI161
1U_0201_6.3V6M
2
1
2
PCI139
47U_0805_6.3V6M
1
PCI160
1U_0201_6.3V6M
2
1
2
1
PCI138
47U_0805_6.3V6M
2
PCI137
47U_0805_6.3V6M
PCI159
1U_0201_6.3V6M
2
1
PCI158
1U_0201_6.3V6M
2
1
2
PCI101
10U_0402_6.3V6M
2
1
B
2
PCI128
22U_0603_6.3V6M
2
1
PCI148
1U_0201_6.3V6M
2
1
1
PCI127
22U_0603_6.3V6M
2
1
PCI147
1U_0201_6.3V6M
2
1
2
PCI126
22U_0603_6.3V6M
2
1
PCI146
1U_0201_6.3V6M
2
1
PCI157
1U_0201_6.3V6M
2
1
PCI125
22U_0603_6.3V6M
2
1
PCI145
1U_0201_6.3V6M
2
1
+
PCI173
330U_X_2VM_R6M
2
PCG120
10U_0402_6.3V6M
PCG103
47U_0805_6.3V6M
PCG108
22U_0603_6.3V6M
2
1
PCI172
330U_X_2VM_R6M
1
PCG109
22U_0603_6.3V6M
2
1
PCG102
47U_0805_6.3V6M
PCG107
22U_0603_6.3V6M
2
1
PCI124
22U_0603_6.3V6M
2
1
PCI144
1U_0201_6.3V6M
2
1
PCI171
330U_X_2VM_R6M
2
1
PCI123
22U_0603_6.3V6M
2
1
1
PCI143
1U_0201_6.3V6M
2
1
2
+
2
PCG101
47U_0805_6.3V6M
2
PCG106
22U_0603_6.3V6M
2
1
+
PCG172
220U_D7_2VM_R6M
2
1
1
PCG105
22U_0603_6.3V6M
2
1
1
PCI122
22U_0603_6.3V6M
2
1
2
PCI142
1U_0201_6.3V6M
2
1
2
1
PCG130
1U_0201_6.3V6M
2
1
PCG171
220U_D7_2VM_R6M
+
PCG119
10U_0402_6.3V6M
2
1
1
1
PCG129
1U_0201_6.3V6M
2
1
2
2
PCG104
22U_0603_6.3V6M
2
1
+
PCG112
10U_0402_6.3V6M
2
1
1
1
PCG122
1U_0201_6.3V6M
2
1
2
+VCCGT
220uF*2
47uF*3
22uF*7
10uF*10
1uF*12
PCG111
10U_0402_6.3V6M
2
1
1
1
+VCC_CORE
330uF*3
47uF*5
22uF*12
10uF*21
1uF*24
PCG121
1U_0201_6.3V6M
2
1
A
C
D
Deciphered Date
D
E
Main Func = PWR_CPU DECOUPLING
+VCC_CORE
e
r
w
e
i
v
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/01/06
Date:
Size
Document Number
Thursday, March 22, 2018
LA-F611P
Sheet
E
71
of
78
1
2
3
4
Title
PWR-CPU DECOUPLING
Compal Electronics, Inc.
R ev
0.1
4
3
PRV01
4.7K_0402_5%
PRV02
4.7K_0402_5%
2
2
5
21
CSP1
20
CSP2
41
GND
PCV14
2
PCV15
2
2
3.3K_0402_1%
41.2K_0402_1%
2
23.2K_0402_1%
2
2
PRV22
1
49.9_0402_1%
1
1K_0402_0.5%
PCV10
1
1000P_0402_25V8J
2
PRV26
1
24.3K_0402_1%
2
2
15K_0402_1%
PCV11
0.1U_0402_25V7K
100K_0402_1%
2
PHV01
220K_0402_5%_B25/50 4700K
PRV36
147K_0402_1%
B
100K_0402_1%
2
0.068U_0402_16V7K
1
100K_0402_1%
2
PRV39
2
200K_0603_1%
1
VGA_SWN1
72,73
PRV41
2
200K_0603_1%
1
VGA_SWN2
72,73
PRV42
2
200K_0603_1%
1
VGA_SWN3
72,74
1
3.24K_0402_1%
1
3.24K_0402_1%
1
3.24K_0402_1%
@ PRV43
1
VGA_CSREF
72,73
72,74
VGA_SWN1
VGA_SWN2
2
PRV44
2
PRV45
2
PRV46
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_GPU Controller
Size
3
2
Document Number
Rev
0.1
LA-F611P
Date:
4
C
0.068U_0402_16V7K
1
@ PRV40
1
PCV16
2
1
0.068U_0402_16V7K
1
@ PRV37
1
PRV20
1
330P_0402_50V8J
PRV21
2
49
2
22
CSREF
VGA_SWN3
A
1
1
PRV27
23
CSSUM
+5VS
r
o
F
2
PCV12
2
32
33
31
VSP
VSN
34
SDA
SCL
VCC
35
36
37
EN
PSI
38
39
40
PW M3/PHTH2
VGA_DRON
24
CSCOMP
E
D
73,74
25
ILIM
PW M4/PHTH1
PRV38
1K_0402_5%
1
L
L
LPC2
PW M2/PHTH3
26
PCV05
1
e
r
PRV24
1
PRV25
1
27
IOUT
NCP81276MNTXG_QFN40_5X5
11
2
1
2
LPC1
PRV35 1K_0402_5%
PRV34 1K_0402_5%
2
1
2
1
PRV33 1K_0402_5%
2
1
PRV32 37.4K_0402_1%
2
1
PRV31 37.4K_0402_1%
1
1
PRV30 26.1K_0402_1%
10
2
9
VGA_PWM2
2
VGA_PWM3
73
PRV29 10K_0402_5%
74
28
LLTH/I2C_ADD
19
8
29
FSW
OCP
CSP3
7
SS
CSP4
6
30
DIFF
18
5
VRMP
17
4
NC
3
VGA_PWM1
47P_0402_50V8J
2200P_0402_25V7K
FB
16
1
B
PCV04
PCV07
2
COMP
NC
2
VREF
NC
C
REFIN
15
2
14
1
VGA_VREF
PGOOD
VGA_REFIN
PWM_VID
0.01U_0402_16V7K
2
NC
PCV08
1
DRON
0.01U_0402_50V7K
13
PCV09
PWM1/PHTH4
+PWR_SRC
4700P_0402_50V7K
VID_BUFF
PUV101
2
PCV06
0_0402_5%
2
PRV17
20.5K_0402_1%
16.5K_0402_1%
1
1K_0402_1%
1
1
1VGA_VREF
2
PRV14
+GPU_CORE
100_0402_5%
VDD_SENSE_VGA
6.19K_0402_1%
12
309_0402_1%
1
1
49
1
PRV19
2
1
PRV11
2
75K_0402_1%
1
PRV18
PRV23
2
GND_SENSE_VGA
PCV02
1000P_0402_50V7K
2
PRV15
1
D
73,74
4700P_0402_50V7K
2
PRV28
2
1
2
1
2
2
2
@ PCV03
2
1
1
1U_0603_16V7
0_0402_5%
100_0402_5%
2
2
0_0402_5%
PRV13 0_0402_5%
1
2
NVVDD_VID
PRV16
4.32K_0402_1%
1
w
e
i
v
2
NVVDD1_PGOOD
48
73
1
2
1
0_0402_5%
PRV07
PCV01
1
PRV09
PRV06
2
@ PRV08
NVVDD_PSI
1
48,56
2
NVVDD1_EN
1
48
56
72,73
PRV10
10K_0402_5%
1
2
D
PRV05
2_0603_5%
680P_0402_50V7K
1
@ PRV03
0_0402_5%
+5VS
1
1
2
PRV04
10K_0402_5%
1
+3VS
2
2
+1V8_AON
1
+3VS
1
+3VS
1
PCV13
2
Main Func = GPU Controller
2
560P_0402_50V7K
1
5
Sheet
Thursday, March 22, 2018
1
72
of
78
2
3
Main Func = +GPU_CORE Phase1&2
4
+5VALW
+GPU_CORE
TDC 59A (46+13)
Peak Current 124A (106+18)
OCP=149A
Fsw=305KHz
DCR:0.98mohm +-5%
CGND
PGND
PGND
GL
GL
BOOT
PHASE
SW
SW
5
7
NC
AGND
6
18
PCV36
1U_0603_25V7K
PUV02
3
15
1
r
o
F
72,73,74
72
PCV38
2.2U_0603_10V7K
VGA_DRON
VGA_PWM2
+5VALW
17
16
1
2
4
10
14
13
19
VIN
VIN
THW N
DISB#
PW M
SMOD#
CGND
PGND
PGND
GL
GL
BOOT
PHASE
SW
SW
NC
AGND
2
PRV52
3.9_0603_1%
6
18
PCV24
10U_0805_25VAK
PCV23
10U_0805_25VAK
1
2
1
1
2
4
2
3
+GPU_CORE
PRV50
10_0402_1%
2
1
VGA_CSREF
VGA_SWN1
72,73,74
B
72
2
PCV35
10U_0805_25VAK
1
2
1
2
1
1
C
2
0.22U_0603_25V7K
PLV02
0.22UH_MMD-06DZER22MEM2L__32A_20%
VGA_SW2
1
4
2
3
+GPU_CORE
2
EMI@ PRV53
4.7_1206_5%
2
NCP302045MNTXG_PQFN33_5X5
PLV01
0.22UH_MMD-06DZER22MEM2L__32A_20%
PCV37
1
5
7
11
12
PCV34
10U_0805_25VAK
2
2
1
PCV32
10U_0805_25VAK
1
2
2
1
VCC
VCCD
EMI@ PCV31
0.1U_0402_25V7K
EMI@ PCV30
2200P_0402_50V7K
1
1
2
E
D
8
9
EMI@ PCV29
680P_0603_50V7K
2
0.22U_0603_25V7K
1
1
2
PRV51
2_0603_5%
1 2
2
@EMI@ PCV55
1000P_0402_50V7K
1
2
C
@EMI@ PCV54
1000P_0402_50V7K
+5VALW
PCV33
10U_0805_25VAK
L
L
2
1
EMI@ PRV49
4.7_1206_5%
NCP302045MNTXG_PQFN33_5X5
NVVDD_B+
e
r
VGA_SW1
11
12
1
4
10
14
13
19
THW N
DISB#
PW M
SMOD#
PCV27
1
2
VGA_DRON
VGA_PWM1
VIN
VIN
A
1
17
16
1
2
1
2
72,73,74
PCV28
72
2.2U_0603_10V7K
VCC
VCCD
8
9
PCV22
10U_0805_25VAK
PCV21
10U_0805_25VAK
2
1
PRV48
3.9_0603_1%
1
2
PUV01
B
2
2
2
1
PCV26
1U_0603_25V7K
+5VALW
1
w
e
i
v
PRV47
2_0603_5%
1
2
3
15
D
EMI@ PCV20
0.1U_0402_25V7K
2
1
+
2
1
1
EMI@ PCV19
2200P_0402_50V7K
2
A
2
1
@EMI@ PCV17
1000P_0402_50V7K
FBMA-L11-453215800LMA90T_2P
@EMI@ PCV18
1000P_0402_50V7K
EMI@ PLIV11
1
2
+PWR_SRC
1
5
NVVDD_B+
PCV50
100U_25V_M
1
1
VGA_CSREF
72,73,74
PRV54
10_0402_1%
EMI@
PCV39
680P_0603_50V7K
VGA_SWN2
72
D
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_+GPU_CORE Phase1&2
Size
3
4
Rev
0.1
LA-F611P
Date:
2
Document Number
Sheet
Thursday, March 22, 2018
5
73
of
78
5
4
3
2
1
Main Func = +GPU_CORE Phase3
NVVDD_B+
72,73
72
17
16
1
2
VGA_DRON
VGA_PWM3
+5VALW
4
10
14
13
19
VCC
VCCD
VIN
VIN
THWN
DISB#
PWM
SMOD#
BOOT
PHASE
CGND
PGND
PGND
GL
GL
SW
SW
NC
AGND
5
r
o
F
E
D
5
7
11
12
2
e
r
1
PCV45
10U_0805_25VAK
PLV03
0.22UH_MMD-06DZER22MEM2L__32A_20%
1
4
2
3
C
+GPU_CORE
2
EMI@ PRV57
4.7_1206_5%
1
VGA_CSREF
72,73
2
PRV58
10_0402_1%
VGA_SWN3
72
1
EMI@ PCV49
680P_0603_50V7K
B
Compal Electronics, Inc.
Compal Secret Data
2016/01/06
Deciphered Date
2017/01/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_+GPU_CORE Phase3
Size
3
2
Document Number
Rev
0.1
LA-F611P
Date:
4
2
1
PCV44
10U_0805_25VAK
PCV47
0.22U_0603_25V7K
VGA_SW3
6
18
2
1
2
1
1
PCV42
10U_0805_25VAK
2
1
A
Security Classification
Issued Date
2
PRV56
3.9_0603_1%
L
L
A
2
1
NCP302045MNTXG_PQFN33_5X5
B
EMI@ PCV41
0.1U_0402_25V7K
2
1
EMI@ PCV40
2200P_0402_50V7K
1
8
9
1
1
2
PCV48
2.2U_0603_10V7K
2
PUV03
D
2
1
PCV46
1U_0603_25V7K
3
15
C
@EMI@ PCV57
1000P_0402_50V7K
1
2
2
PRV55
2_0603_5%
2
1
@EMI@ PCV56
1000P_0402_50V7K
+5VALW
PCV43
10U_0805_25VAK
w
e
i
v
D
Thursday, March 22, 2018
Sheet
1
74
of
78
PCV210
22U_0805_6.3VAM
PCV271
470U_D2_2VM_R4.5M~D
1
PCV217
4.7U_0603_6.3V6K
PCV216
4.7U_0603_6.3V6K
2
PCV209
22U_0805_6.3VAM
PCV208
22U_0805_6.3VAM
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
1
1
PCV215
10U_0603_6.3V6M
2
1
PCV214
10U_0603_6.3V6M
2
1
PCV213
10U_0603_6.3V6M
2
1
PCV212
10U_0603_6.3V6M
PCV133
10U_0603_6.3V6M
PCV132
10U_0603_6.3V6M
PCV131
10U_0603_6.3V6M
PCV130
10U_0603_6.3V6M
PCV129
10U_0603_6.3V6M
PCV128
10U_0603_6.3V6M
PCV127
10U_0603_6.3V6M
2
2
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
1
1
1
PCV205
1U_0402_6.3V6K
2
1
PCV204
1U_0402_6.3V6K
2
1
PCV203
1U_0402_6.3V6K
2
1
PCV202
1U_0402_6.3V6K
PCV123
4.7U_0603_6.3V6K
PCV122
4.7U_0603_6.3V6K
PCV121
4.7U_0603_6.3V6K
PCV120
4.7U_0603_6.3V6K
PCV119
4.7U_0603_6.3V6K
1
2
PCV207
10U_0603_6.3V6M
PCV206
10U_0603_6.3V6M
PCV272
330U_X_2VM_R6M
C
PCV211
10U_0603_6.3V6M
PCV124
4.7U_0603_6.3V6K
2
1
PCV201
1U_0402_6.3V6K
2
1
PCV116
4.7U_0603_6.3V6K
2
1
PCV115
4.7U_0603_6.3V6K
2
1
PCV114
4.7U_0603_6.3V6K
2
1
PCV113
4.7U_0603_6.3V6K
2
1
PCV112
4.7U_0603_6.3V6K
2
1
PCV111
4.7U_0603_6.3V6K
2
2
2
1
1
2
1
PCV108
1U_0402_6.3V6K
2
1
PCV107
1U_0402_6.3V6K
2
1
PCV106
1U_0402_6.3V6K
2
1
PCV105
1U_0402_6.3V6K
2
1
PCV104
1U_0402_6.3V6K
2
1
PCV103
1U_0402_6.3V6K
PCV126
10U_0603_6.3V6M
PCV125
10U_0603_6.3V6M
PCV173
330U_X_2VM_R6M
PCV172
470U_D2_2VM_R4.5M~D
PCV171
470U_D2_2VM_R4.5M~D
PCV140
22U_0805_6.3VAM
PCV139
22U_0805_6.3VAM
PCV138
22U_0805_6.3VAM
PCV137
22U_0805_6.3VAM
PCV136
22U_0805_6.3VAM
PCV135
22U_0805_6.3VAM
PCV134
22U_0805_6.3VAM
5
PCV118
4.7U_0603_6.3V6K
PCV117
4.7U_0603_6.3V6K
A
A
PCV110
4.7U_0603_6.3V6K
PCV109
4.7U_0603_6.3V6K
1
78
of
75
Sheet
Thursday, March 22, 2018
Date:
Rev
0.1
Document Number
Size
VGA DECOUPLING
LA-F611P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
2017/01/06
Deciphered Date
2016/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2
3
4
E
D
r
o
F
1
1
1
+
+
2
2
2
1
1
1
1
1
2
2
C
B
B
2
2
2
2
2
2
2
2
2
2
2
1
PCV102
1U_0402_6.3V6K
2
1
PCV101
1U_0402_6.3V6K
For NV N17P latest spec
e
r
L
L
+
+
+
1
1
1
1
1
For NV N17P latest spec
+GPU_CORE
w
e
i
v
D
1
1
D
+GPU_CORE (NVVDDS)
470uF X 1
330uF X 1
22uF_0805 X 3
10uF_0603 X 7
4.7uF_0603 X 2
1uF_0402 X 5
+GPU_CORE (NVVDD)
470uF X 2
330uF X 1
22uF_0805 X 7
10uF_0603 X 9
4.7uF_0603 X 16
1uF_0402 X 8
+GPU_CORE
1
2
3
4
5
Main Func = VGA DECOUPLING
5
4
3
2
1
Main Func = +1.35VGPUP
w
e
i
v
@ PJPW 01
2
D
1.35VS_VGAP
TDC=11A
Ipeak=20A
OCP=24A
1
JUMP_43X39
1
1
PCW 13
0.1U_0402_25V7K
2
48
0_0402_1%
1
2
S1@ PRW 11
2
PRW13
3.3K_0402_1%
1
PCW 15
2700P_0402_50V7K
4
5
0.1U_0402_25V7K
8
2
1
6
S1@ PRW 12
51K_0402_1%
7
12
VREF
BOOT2
REFADJ
PHASE2
REFIN
LGATE2
5
G1
G2
S2
S2
S2
1 2
1
VSNS
GND
RGND
15
16
L
L
17
PRW 14
100_0402_5%
11
1
2
10
1
PRW 19
0_0402_1%
2
FBVDDQ_SENSE
E
D
PRW 12
31.6K_0402_1%
S2@
GPU type
VRAM memory
VRAM vender
RVL
PRW11
PRW12
S1@ (4G)
N17P-G0/G1
256Mx32
Micron
1.35V & 1.5V
5.62K
51K
S1@ (4G)
N17P-G0/G1
256Mx32
Hynix
1.35V & 1.5V
5.62K
51K
S1@ (4G)
N17P-G0/G1
256Mx32
r
o
F
Samsung
1.35V & 1.5V
5.62K
51K
S2@ (3G/6G) N17E-G1 Max-Q 128M/256M x32
Hynix
1.35V & 1.55V
4.7K
31.6K
S2@ (3G/6G) N17E-G1 Max-Q 128M/256M x32
Samsung
1.35V & 1.55V
4.7K
31.6K
@EMI@ PCW08
1000P_0402_50V7K
2
1
PCW06
10U_0805_25VAK
2
1
PCW05
10U_0805_25VAK
2
1
PCW04
10U_0805_25VAK
2
1
2
e
r
EMI@ PRW 04
4.7_1206_5%
6
2
5
+1.35VGPU_BOOT1_1
4
1
14
PRW 17
66.5K_0402_1%
BOM config
A
+1.35VGPU_LGATE1
PRW 05
2.2_0603_5%
1
OCSET/SS
B
S2@
1
1
UGATE2
50
PRW 11
4.7K_0402_1%
2
D1
2
VID
19
2
1
2
PRW16
1800P_0402_50V7K
2
1
LGATE1
2
1
21
PRW15
25.5K_0402_1%
PSI
+1.35VGPU_PHASE1
100K_0402_1%
5.62K_0402_1%
1
2
PHASE1
+1.35VGPU_BOOT1
20
2
PCW 14
2
EN
1
PCW 11
0.22U_0603_25V7K
EMI@ PCW 12
680P_0402_50V7K
1.35VGPUP
1
+
2
1
+
2
PCW19
220U_D2 SX_2VY_R9M
+1.35VGPU_PSI
PRW 09
1
PRW 10
2
1
BOOT1
+1.35VGPU_UGATE1
+PWR_SRC
PCW18
220U_D2 SX_2VY_R9M
0_0402_1%
3
7
2
PRW 06
+1V8_AON
MEM_VDD_CTL
PGOOD
2
1
FBVDD/Q_EN
2
2
PRW 08
10K_0402_1%
UGATE1
3
13
+1.35VGPU_EN
1
2
C
TON
2.2_0402_1%
PRW 0712.4K_0402_1%
1
+1.35VGPU_TON 9
2
56
+1V8_AON
PRW 02
2
2
10K_0402_1%
1
1
1
PLW 01
0.82UH_MMD-06CZ-R82M-V1L_13A_20%
D2/S1
PCW17
47P_0402_50V8J
@ PRW 18
2
PVCC
1
1
1
+3VS
PRW 03
383K_0402_1%
+1.35VGPU_VIN
DGPU_PWROK
PCW 09
2.2U_0603_10V7K
18
2+1.35VGPU_TON_1
1
18,48,56
PUW 01
RT8816AGQW _W QFN20_3X3
2
PCW03
10U_0805_25VAK
2
1
PQW01
AON6962 2N DFN5X6D
2
+1.35VGPU_PVCC
EMI@ PCW02
0.1U_0402_25V7K
2
1
EMI@ PCW01
2200P_0402_50V7K
2
1
1
PRW 01
2.2_0603_5%
PCW 10
0.1U_0402_25V7K
EMI@ PLW 11
5A_Z120_25M_0805_2P
+1.35VGPU_VIN
@EMI@ PCW07
1000P_0402_50V7K
2
1
+5VALW
D
C
@ PJPW 02
1
1.35VGPUP
1
2
2
+1.35VS_VGA
JUMP_43X118
@ PJPW 03
1
1
2
2
JUMP_43X118
B
MEM_VDD_CTL
L
H
+MVDD
1.35V
1.5V/1.55V
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
4
3
2
+1.35VGPUP
Document Number
Rev
0.1
LA-F611P
Date:
Thursday, March 22, 2018
1
Sheet
76
of
78
5
4
3
2
1
Main Func = 1VS_GFX
+1VS_GFX
TDC 0.88A
Peak Current 1.1A
OCP current 4A
w
e
i
v
D
@ PL1011
5A_Z120_25M_0805_2P
1
2
PU1001
PR1005
0_0402_5%
1
2
@ PR1006
0_0402_5%
L
L
r
o
F
1
PC1008
0.1U_0402_16V7K
2
2
1
@
e
r
@EMI@ PC1004
680P_0402_50V7K
PC1007
22U_0603_6.3V6M
SNB_1.0VS_VGAP
PC1006
22U_0603_6.3V6M
2
1
PR1002
10K_0402_5%
1
+1.0VS_VGA_PGOOD
+3VS
EN_1.0VS_VGAP
+1.0VS_VGAP
@EMI@ PR1003
4.7_0603_5%
2
56
5
2
2
5
EN
1
PR1004
10K_0402_1%
C
@ PJP1002
1
+1.0VS_VGAP
1
2
2
+1VS_GFX
JUMP_43X79
E
D
B
A
PGOOD
FB
4
1
2
PR1007
1M_0402_1%
2
1
+1V8_AON
NC
PL1001
1UH_6.6A_20%_5X5X3_M
1
2
3
FB_1.0VS_VGAP
PC1003
22P_0603_50V8
PEX_VDD_EN
LX
LX_1.0VS_VGAP
2
Rdown
1
C
56
SVIN
1
2
6
LX
2
PC1002
1
2
7
NC
PVIN
RT8061AZQW _W DFN10_3X3
PR1001
6.81K_0402_1%
2
1
+1.0VS_VGAP
1U_0603_6.3V6M
1
2
PC1001
22U_0603_6.3V6M
Rup
8
TP
PVIN
PC1005
22U_0603_6.3V6M
2
1
9
JUMP_43X39
1
+3VALW
11
10
1.0VS_VGAP_VIN
2
1
@ PJP1001
1
1
2
D
B
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
Issued Date
Deciphered Date
2017/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR_+1VS_GFX
Size
3
2
Rev
0.1
LA-F611P
Date:
4
Document Number
Thursday, March 22, 2018
Sheet
1
77
of
78
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Issue
Description
Request
Owner
Solution
Description
w
e
i
v
D
1
2
C
3
L
L
4
5
6
B
8
A
5
D
e
r
C
E
D
7
r
o
F
Rev.
B
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2016/01/06
2017/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Changed-List PWR History
Size
Date:
4
3
2
Document Number
R ev
0.1
Thursday, March 22, 2018
Sheet
1
78
of
78