A B C D E 1 1 VFKTA Rosetta 10FT/10FTG 2 2 LA-9862P REV 1.0 Schematic Intel Processor (Ivy Bridge/Sandy Bridge)+ PCH(Panther Point) 3 3 2013-02-06 Rev 1.0 4 4 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Cover Page Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 1 of 46 A B C D Intel CPU Ivy Bridge 17W Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 Dual Channel page 11,12 BANK 0, 1, 2, 3 1.5V DDRIII 1066/1333/1600 MT/s BGA-1023 1 E 1 31mm*24mm page 5,6,7,8,9,10 eDP 1.1 2x 2.7GT/s FDI X8 DMI X4 2.7GT/s 5GT/s USB30 2x 5V 5GT/s LVDS & eDP Conn. USB20 3x page 13 2 5V 480MHz Intel PCH Panther Point HDMI Conn. USB20 2x USB Right USB20 port 0,1 USB30 port 1,2 page 29 CardReader GL834L 5V 480MHz Int. Camera USB20 port 8 page 28 page 15 2 USB port 11 page 22 FCBGA-989 RJ45 Conn. PCIe Gen1 1x RTL8106E & 8111G PCIe Gen1 1x 1.5V 5GT/s PCIe port 1 1.5V 5GT/s 25mm*25mm page 27 USB20 port 2 PCIe port 2 &USB port 9 page 26 USB20 2x USB20 2x 5V 480MHz 5V 480MHz USB Left PCIeMini Card WLAN and BT page 27 SATA Gen3 1x SATA HDD SATA port 0 page 25 5V 6GHz(600MB/s) To sub-board SATA Gen2 1x page 16,17,18,19,20,21,22,23,24 5V 3GHz(300MB/s) SATA ODD SATA port 2 page 25 3 3 RTC CKT. page 16 SPI ROM (4MB) page LPC BUS HD Audio 3.3V 33 MHz 3.3V 24MHz HDA Codec KB9012 16 ALC259/269 page 32 page 30 DC/DC Interface CKT. page 34 Power Circuit DC/DC Touch Pad page 33 Int.KBD page 33 G-Sensor LED+LID/B page 25 page 33 SPK Conn page 31 page 35,36,37,38,39,40, 41,42,43 JPIO (HP &page MIC) 31 GCLK 4 SLG3NB244VTR 4 page 26 Power/B 2012/04/19 Issued Date To sub-board Compal Electronics, Inc. Compal Secret Data Security Classification page 33 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Block Diagram Document Number Rev 1.0 VFKTA Monday, March 11, 2013 Sheet E 2 of 46 5 4 3 DESIGN CURRENT 0.1A 2 1 +3VL B+ Ipeak=8.5A, Imax=5.95A, Iocp min=10.2 DESIGN CURRENT 5A +5VALW PCH_PWR_EN# +5VALW_PCH P-CHANNEL AO-3413 SUSP# D D DESIGN CURRENT 2A +1.8VS DESIGN CURRENT 6A +5VS SY8032ABC SUSP# TPS22966DPUR KB_LED RT8243AZQW DESIGN CURRENT 400mA +5VS_LED DESIGN CURRENT 300mA +3VS_HDP DESIGN CURRENT 1.6A +5VS_ODD P-CHANNEL AO-3413 +5VS LDO G9191-330T1U ODD_EN# P-CHANNEL AO-3413 Ipeak=5A, Imax=3.5A, Iocp min=6.12A DESIGN CURRENT 5A +3VALW DESIGN CURRENT 330mA +3V_LAN C C WOWL_EN# DESIGN CURRENT 3A P-CHANNEL AO-3413 +3V_WLAN PCH_PWR_EN# +3VALW_PCH P-CHANNEL AO-3413 SUSP# DESIGN CURRENT 6A TPS22966DPUR +3VS LCD_ENVDD DESIGN CURRENT 1.5A APL3512ABI +LCD_VDD VR_ON ISL95833HRTZ DESIGN CURRENT 65A +CPU_CORE DESIGN CURRENT 40A +GFX_CORE B B SUSP# SY8208DQNC Ipeak=14.37A, Imax=10.06A, Iocp min=17.24A +1.05VS_VCCP VCCP_PWRGOOD DESIGN CURRENT 6A +VCCSA G978F11U SYSON Ipeak=16.66A, Imax=11.66A, Iocp min=20A DESIGN CURRENT 2A RT8207MZQW 0.75VR_ON DESIGN CURRENT 1.5A +1.5V +0.75VS SUSP N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU DESIGN CURRENT 2A +1.5VS FDS6676AS A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Power Tree Document Number Rev 1.0 VFKTA Monday, March 11, 2013 1 Sheet 3 of 46 A B ( O MEANS ON Voltage Rails +RTCVCC C X MEANS OFF ) B+ E BTO Option Table +5VL +5VALW +3VL +3VALW +1.5V +5VS +1.5VS description explain +1.5V_CPU BTO +0.75VS 1 CPU Function +3VS +1.8VS +VSB power plane D PCH IVB i5 3337U IVB i3 3227U IVB i3 2375M IVB P 2117U IVB C 847 IVB i5 3337U Panther Point IVB i3 3227U IVB i3 2375M IVB P 2117U IVB C 847 CPUI53337UR1@ CPUI33227UR1@ CPUI32375MR1@ CPUP2117UR1@ CPUC847R1@ HM76R1@ HM76 HM70R1@ HM70 CPUI53337UR3@ CPUI33227UR3@ CPUI32375MR3@ CPUP2117UR3@ CPUC847R3@ HM76R3@ HM70R3@ 1 +CPU_CORE +GFX_CORE +VCCSA +1.05VS_VCCP State +3V_WLAN Function description Camera & Mic LVDS-eDP Camera & Mic 14640 14641 Camera & Mic 14640 14641 14640@ 14641@ explain LVDS eDP BTO LVDS@ IEDP@ +3V_LAN +LCD_VDD 2 O O O O O O description explain S1 O O O O O O S3 O O O O O X O O O O X X O O O X X X X X X S5 S4/AC S5 S4/ Battery only S5 S4/AC & Battery don't exist O X X CAM_EMI@ WOWL Function S0 USB S&C G-SENSOR WOWL@ NOWOWL@ GSENSOR@ w/ ZPODD@ EC w/o CRT KB9012 CRT@ CRT_EMI@ NOCRT@ 9012@ GCLK non-GCLK Touch Screen w/o GCLK non-GCLK Touch Screen NONZP@ GCLK@ NOGCLK@ TOUCH_EMI@ Sleep & Music KB Light EMI/ESD/RF part ISPD description Sleep & Music KB Light EMI/ESD/RF part HDMI Logo KB Light EMI/ESD/RF part Function explain w/ S&M w/o S&M BTO 269@ 259@ KBL@ EMI@ @EMI@ ESD@ @ESD@ NPCE885N 885@ Touch Screen GCLK ZPODD G-SENSOR w/o EC CRT w/ CRT ZPODD G-SENSOR WOWL w/ BTO CRT LVDS-eDP 2 HDMI Logo @RF@ HDMI45@ Red Word: always un-mount PCH SM Bus Address Power Device HEX Address +3VS DDR SO-DIMM 0 A0 H 1010 0000 b +3VS DDR SO-DIMM 1 A4 H 1010 0100 b +3VS Touch Pad 2C H 0010 1100 b 3 3 EC SM Bus1 Address Power Device HEX Address EC SM Bus2 Address Power +3VL Smart Battery 16 H 0001 0110 b +3VS +3VL Smart Charger 12 H 0001 0010 b +3VS +3VL USB S&C 14640 35 H 0011 0101 b Power Device Address HEX Device HEX Address PCH 96 H 1001 0110 b 40 H 0100 0000 b G-Sensor 10/22A Add G-sensor reference Hemen SIGNAL STATE Full ON SLP_S3# SLP_S4# SLP_S5# HIGH HIGH HIGH S1(Power On Suspend) HIGH HIGH HIGH S3 (Suspend to RAM) LOW HIGH HIGH S4 (Suspend to Disk) LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW 10/22A Add Smart Charger SMBus address: 0x12 Hemen we Add already 4 4 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Notes List Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 4 of 46 A B C D E Stuff RC158&RC157 if do not support eDP MISC @ 1 CC62 1 180P_0402_50V8J ESD@ 1 PM_DRAM_PWRGD_R ESD@ 2 CC63 H_PWRGOOD_R 2 H_THERMTRIP# 21 H_SNB_IVB# H_SNB_IVB# T1 PAD TP_SKTOCC# TP@ F49 C57 PROC_SELECT# PROC_DETECT# 11/30 Change CC63 from @ESD@ to ESD@ for ESD request CC20 100P_0402_50V8J T2 PAD H_CATERR# TP@ C49 by ESD requestion and place near CPU H_PECI A48 PECI RC159 +1.05VS_VCCP RC44 H_PECI 2 1 62_0402_5% H_PROCHOT# 1 10K_0402_5% H_PWRGOOD 32 H_PROCHOT# 21 H_THERMTRIP# 1 2 H_PROCHOT#_R 56_0402_5% H_THERMTRIP# C45 D45 DPLL_REF_CLK DPLL_REF_CLK# J3 H2 AG3 AG1 100 MHz CLK_CPU_DMI CLK_CPU_DMI# CLK_CPU_DMI 17 CLK_CPU_DMI#17 +1.05VS_VCCP 120 MHz LVDS@ CLK_CPU_EDP CLK_CPU_EDP# CLK_CPU_EDP 17 CLK_CPU_EDP#17 CLK_CPU_EDP# RC1571 CLK_CPU_EDP RC1581 PROCHOT# SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] AT30 H_DRAMRST# BF44 BE43 BG43 SM_RCOMP_0 RC56 2 SM_RCOMP_1 RC59 2 SM_RCOMP_2 RC61 2 7 H_DRAMRST# H_PECI 18 H_PM_SYNC 21 H_PWRGOOD PM_SYNC @ 1000P_0402_50V7K 2 1 CC67 H_PM_SYNC 1 CC66 BUF_CPU_RST# 1 RC183 2 H_PWRGOOD_R B46 Rshort@ 0_0402_5% UNCOREPWRGOOD @ 1000P_0402_50V7K 2 PM_SYS_PWRGD_BUF 1 RC170 2 PM_DRAM_PWRGD_R BE45 130_0402_5% SM_DRAMPWROK Please place near JCPU 2 BUF_CPU_RST# D44 RESET# +3VALW_PCH by ESD requestion and place near CPU 1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1% DDR3 Compensation Signals Layout Note:Place these resistors near Processor 1 BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_TCK XDP_TMS XDP_TRST# M60 L59 XDP_TDI XDP_TDO K58 T3 T4 1 RC55 T6 T7 PAD TP@ PAD TP@ 2 51_0402_5% Routed as a single daisy chain PAD TP@ PAD TP@ Close to CPU side G58 E55 E59 G55 G59 H60 J59 J61 2 +1.5V_CPU 2 DRAMPWROK 5 B UC3 74AHC1G09GW_TSSOP5 P 10K_0402_5% 2 RC13 1 1 O 4 1 <BOM> RC14 200_0402_5% PM_SYS_PWRGD_BUF 3 A IVY-BRIDGE_BGA1023 CPU@ G +3VS DRAMPWROK DBR# L56 L55 J58 2 ESD@ 100P_0402_50V8J CC35 +3VALW_PCH 1 DRAMPWROK 200_0402_5% 02/20 Delete CC33 0.1U 18 TDI TDO N53 N55 2 2 RC11 TCK TMS TRST# JTAG & BPM 1 CC70 C48 PWR MANAGEMENT 1000P_0402_50V7K 2 H_PM_SYNC 1 THERMTRIP# PRDY# PREQ# @ 2 1K_0402_5% @ESD@ 1 2 CC34 180P_0402_50V8J H_DRAMRST# RC45 2 2 1K_0402_5% LVDS@ H_DRAMRST# THERMAL 32 BCLK BCLK# CATERR# 1 DDR3 MISC 1000P_0402_50V7K 2 CLOCKS UC1B 3 3 Buffered Rest to CPU FAN Control Circuit XDP Connector +3VS For power consumption +5VS +3VS OE# 3 RC38 75_0402_5% 5 2 VCC 2 2 R2 10K_0402_5% IN OUT 4 BUFO_CPU_RST# JFAN 6 5 4 3 2 1 0_0603_5% 2 1 Rshort@ 1 R1 UC2 PLT_RST# 1A +1.05VS_VCCP 20,26,27,32 1 PLT_RST# 1 02/20 Delete CC36 0.1U 32 32 RC35 43_0402_1% 1 2 BUF_CPU_RST# FANPWM FAN_SPEED1 +FAN1 02/20 change R1 to short pad for part count reduce GND Conn@ GND GND 4 3 2 1 ACES_50273-0040N-001 02/20 Delete C4 0.01U 1 74AHC1G125GW_SOT353-5 1 BAS16_SOT23-3 2012/04/19 Issued Date 4 2 10U_0603_6.3V6M Compal Electronics, Inc. Compal Secret Data Security Classification C5 2 D1 4 2015/04/19 Deciphered Date Title Ivy Bridge_JTAG/XDP/FAN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 5 of 46 A B C D 1 +1.05VS_VCCP M2 P6 P1 P10 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 N3 P7 P3 P11 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_N0 18 DMI_CTX_PRX_N1 18 DMI_CTX_PRX_N2 18 DMI_CTX_PRX_N3 18 K1 M8 N4 R2 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 18 DMI_CTX_PRX_P1 18 DMI_CTX_PRX_P2 18 DMI_CTX_PRX_P3 18 K3 M7 P4 T3 DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 18 18 18 18 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 U7 W11 W1 AA6 W6 V4 Y2 AC9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 U6 W10 W3 AA7 W7 T4 AA3 AC8 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 18 18 18 18 18 18 18 18 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 18 18 FDI_FSYNC0 FDI_FSYNC1 18 FDI_INT FDI_INT 18 18 FDI_LSYNC0 FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] 2 RC2 +1.05VS_VCCP 13 13 10/24 SWAP pin H_EDP_AUXN/P 3 02/20 Swap H_EDP_TXN[0\1] to H_EDP_TXP[0\1] 1 2 24.9_0402_1% AA11 AC12 U11 AA10 AG8 AF3 AD2 H_EDP_HPD# AG11 EDP_COMP AG4 AF4 H_EDP_AUXN H_EDP_AUXP 13 13 H_EDP_TXN0 H_EDP_TXN1 AC3 AC4 AE11 AE7 13 13 H_EDP_TXP0 H_EDP_TXP1 AC1 AA4 AE10 AE6 +1.05VS_VCCP FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] G3 G1 G4 PEG_COMP 1 H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 2 G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 3 <BOM> 2 IVY-BRIDGE_BGA1023 CPU@ eDP eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm FDI_FSYNC0 FDI_FSYNC1 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] Intel(R) FDI FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 18 18 18 18 18 18 18 18 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 18 18 18 18 PCI EXPRESS -- GRAPHICS 1 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 m ohm (12 mils) 2 RC1 24.9_0402_1% UC1A E 1 1 D S 2 G CPU_EDP_HPD 2N7002_SOT23-3 QC1 IEDP@ IEDP@ RC9 100K_0402_5% 1 2 13 H_EDP_HPD# 3 RC10 1K_0402_5% 4 4 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Ivy Bridge_DMI/PEG/FDI Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 6 of 46 A B C D E DDR_A_D[0..63] 12 DDR_B_D[0..63] UC1C AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2 11 BD37 BF36 BA28 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE# 11 BE39 BD39 AT41 1 2 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_CK[0] SA_CK#[0] SA_CKE[0] SA_CK[1] SA_CK#[1] SA_CKE[1] SA_CS#[0] SA_CS#[1] SA_ODT[0] SA_ODT[1] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 UC1D SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] AU36 AV36 AY26 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 AT40 AU40 BB26 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 BB40 BC41 DDRA_SCS0# DDRA_SCS1# AY40 BA41 DDRA_ODT0 DDRA_ODT1 AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDRA_CLK0 DDRA_CLK0# DDRA_CKE0 11 11 11 DDRA_CLK1 DDRA_CLK1# DDRA_CKE1 11 11 11 DDRA_SCS0# DDRA_SCS1# 11 11 DDRA_ODT0 DDRA_ODT1 11 11 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2 12 BG39 BD42 AT22 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE# 12 AV43 BF40 BD45 11 DDR_A_DQS#[0..7] DDR_A_DQS[0..7]11 DDR_A_MA[0..15] 11 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_BS[0] SA_BS[1] SA_BS[2] 3 SA_CAS# SA_RAS# SA_WE# IVY-BRIDGE_BGA1023 CPU@ SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CK[0] SB_CK#[0] SB_CKE[0] SB_CS#[0] SB_CS#[1] SB_ODT[0] SB_ODT[1] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 BA36 BB36 BF27 DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 BE41 BE47 DDRB_SCS0# DDRB_SCS1# AT43 BG47 DDRB_ODT0 DDRB_ODT1 DDRB_CLK0 DDRB_CLK0# DDRB_CKE0 12 12 12 DDRB_CLK1 DDRB_CLK1# DDRB_CKE1 12 12 12 DDRB_SCS0# DDRB_SCS1# 12 12 DDRB_ODT0 DDRB_ODT1 12 12 AL3 DDR_B_DQS#0 AV3 DDR_B_DQS#1 BG11 DDR_B_DQS#2 BD17 DDR_B_DQS#3 BG51 DDR_B_DQS#4 BA59 DDR_B_DQS#5 AT60 DDR_B_DQS#6 AK59 DDR_B_DQS#7 12 DDR_B_DQS#[0..7] 2 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# IVY-BRIDGE_BGA1023 CPU@ <BOM> BA34 AY34 AR22 1 SB_CK[1] SB_CK#[1] SB_CKE[1] DDR SYSTEM MEMORY B 11 AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS[0..7]12 DDR_B_MA[0..15] 12 3 <BOM> +1.5V 1 2013/02/06 change QC3 to SB00000PF00 for X1 code QC3 1 DDR3_DRAMRST#_R 3 2 H_DRAMRST# 11/28 Change RC73 to 0 ohm (do not use short pad on this location) 2 4 02/20 Change RC73 to short pad for part count reduce RC73 1 Rshort@ 2 DRAMRST_CNTRL 9,17 DRAMRST_CNTRL_PCH 2013/02/06 Confim with rick_Chu , delete CC22 , because HW timing 0_0402_5% 2013/02/06 PVT Delete RC3. SM_DRAMRST# 11,12 BSS138_NL_SOT23-3 1 4 RC77 1K_0402_5% 2 G RC78 4.99K_0402_1% 1 D H_DRAMRST# S 5 2 RC76 1K_0402_5% 1 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification CC37 0.047U_0402_25V6K 2015/04/19 Deciphered Date Title 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Ivy Bridge_DDR3 Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 7 of 46 A B VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] 2 1 2 ESD@ CC19 100P_0402_50V8J 1 ESD@ CC18 100P_0402_50V8J AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48 1 2 1 For DDR by ESD requestion and place near CPU 11/30 install 3 CAP(100pF)CC17,CC18,CC19 on +1.05Vs_Vccp and must close to CPU AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15 2 For PEG +1.05VS_VCCP VCCIO50 VCCIO51 W16 W17 1mA VCCIO_SEL BC22 3 +1.05VS_VCCP +1.05VS_VCCP VCCPQE[1] VCCPQE[2] AM25 AN22 1 CC71 1U_0402_6.3V6K RC91 130_0402_5% SVID A44 B43 C44 2 2 VIDALERT# VIDSCLK VIDSOUT +1.05VS_VCCP 1 3 VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] H_CPU_SVIDALRT# 1 RC89 75_0402_5% 2 RC90 2 2 E +1.05VS_VCCP 1 1 VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76] D +1.05VS_VCCP 8.5A ESD@ CC17 100P_0402_50V8J A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38 POWER PEG IO AND DDR IO 33A QUIET RAILS UC1F CORE SUPPLY +CPU_CORE C VR_SVID_ALRT# 42 42 VR_SVID_CLK 42 VR_SVID_DAT 43_0402_1% +CPU_CORE 2 Pull high resistor on VR side VCCSENSE VSSSENSE 1 VCCIO_SENSE AN16 AN17 VCCIO_SENSE 40 RC97 100_0402_1% RC98 10_0402_1% 2 <BOM> 1 IVY-BRIDGE_BGA1023 CPU@ 42 42 4 2 VCCIO_SENSE VSS_SENSE_VCCIO 4 F43 G43 1 SENSE LINES VCC_SENSE VSS_SENSE 1 RC93 100_0402_1% RC96 10_0402_1% Close to CPU +1.05VS_VCCP 2012/04/19 Issued Date 2 Close to CPU Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Ivy Bridge_POWER-1 Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 8 of 46 B +VCCSA Decoupling: 2X 47U (MLCC), 3X 10U, 5X 1U 2 2 2 1 1 1 1 @ 1 2 1 @ 47U_0805_6.3V6M 1 1 2 2 2 3 1 +VREF_DQB QC8 BSS138_NL_SOT23-3 CC53 CC50 47U_0805_6.3V6M 2 10U_0603_6.3V6M 2 10U_0603_6.3V6M 2 10U_0603_6.3V6M 2 10U_0603_6.3V6M CC56 10U_0603_6.3V6M CC54 +1.5V_CPU Decoupling: 2X 47U(MLCC), 6X 10U, 8X 1U Place BOT OUT BGA CC85 1 2 2 2 2 2 2 2 2 1U_0402_6.3V6K CC86 1 1U_0402_6.3V6K CC87 1 1U_0402_6.3V6K CC78 1 1U_0402_6.3V6K CC79 1 1U_0402_6.3V6K CC80 1 1U_0402_6.3V6K CC81 1 1U_0402_6.3V6K CC82 1 2 +VCCSA VCCSA_VID1 0 0 0.90 V 0 1 0.80 V 1 0 0.725 V 1 1 0.675 V For Sandy Bridge 2 3 VDDQ_SENSE VSS_SENSE_VDDQ BC43 BA43 +1.5V CC46 1 2@ 0.1U_0402_10V7K CC47 1 2@ 0.1U_0402_10V7K CC48 1 2@ 0.1U_0402_10V7K CC45 1 2@ 0.1U_0402_10V7K +1.5V_CPU VCCSA_SENSE Vgs=10V,Id=14.5A,Rds=6mohm U10 RC203 470_0805_5% VCCSA_VID[0] VCCSA_VID[1] D48 D49 H_VCCSA_VID0 H_VCCSA_VID1 H_VCCSA_VID0 41 H_VCCSA_VID1 41 Please kindly check whether there is pull-down resister in PWR-side or HW-side 2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue QC5B SUSP 1 @ 1 1 +1.5V QC4 1 2 3 4 CC68 10U_0603_6.3V6M S S S G D D D D 8 7 6 5 02/20 Delete FDS6676AS_SO8 RUN_ON_CPU1.5VS3 2 CC69 0.1U_0402_25V6 5 <BOM> 1 2 2012/04/19 Issued Date CC83 RC204 1 2 220K_0402_5% B+ RC205 820K_0402_5% QC5A 2 SUSP 34 SUSP 2N7002DW-T/R7_SOT363-6 4 Compal Electronics, Inc. Compal Secret Data Security Classification 11/28 Change CC44 100u to 0805 size (SE00000PL00), Add CC40 (SE00000PL00) PJ1 JUMP_43X39 2N7002DW-T/R7_SOT363-6 IVY-BRIDGE_BGA1023 CPU@ +1.5VS JP@ 2 2 6 QUIET RAILS CC72 1U_0402_6.3V6K 1 VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16] 1 2 6A VCCDQ[1] VCCDQ[2] AM28 AN26 1 2 CC73 1 1U_0402_6.3V6K 2 CC74 1 1U_0402_6.3V6K CC75 1 1U_0402_6.3V6K 2 1U_0402_6.3V6K 1U_0402_6.3V6K 2 4 CC76 1 CC55 3 1 Place BOT OUT BGA CC77 1 CC52 +1.5V_CPU SENSE LINES 1 @ +VREF_DQB_M3 CC51 4 1 47U_0805_6.3V6M 1 2 Place TOP IN BGA CC57 10U_0603_6.3V6M AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33 1U_0402_6.3V6K - 1.5V RAILS VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26] VCCSA VID lines L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20 CC40 2 2 CC43 10U_0603_6.3V6M 1 CC41 10U_0603_6.3V6M 2 10U_0603_6.3V6M 1 2 47U_0805_6.3V6M @ CC42 VCCPLL[1] VCCPLL[2] VCCPLL[3] 02/20 Delete CC61 Place TOP IN BGA CC44 1.2A BB3 BC1 BC4 1 7,17 DRAMRST_CNTRL_PCH VCCSA_VID0 1.8V RAIL 2 1U_0402_6.3V6K 2 VAXG_SENSE VSSAXG_SENSE +VREF_DQA 1mA SA RAIL 2 1 +1.8VS_VCCPLL CC60 1 +VCCSA 11/28 Change CC53 100u to 47U 0805 (SE00000PL00) Add CC50 (SE00000PL00) +1.5V_CPU SENSE LINES F45 G45 VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U 10U_0603_6.3V6M BSS138_NL_SOT23-3 QC7 3 1 +VREF_DQA_M3 +1.5V_CPU VCC_AXG_SENSE 42 VSS_AXG_SENSE 42 RC106 1 2 100_0402_1% Reserve for power consumption CC59 Remove on PVT phase 2 1K_0402_0.5% 2 1 5A Close to CPU 02/20 change RC119 to short pad 1 Rshort@ 2 +1.8VS RC119 0_0805_5% 1K_0402_0.5% 2 1 RC109 D 3 +VREF_DQA_M3 +VREF_DQB_M3 2 RC105 100_0402_1% VCC_AXG_SENSE VSS_AXG_SENSE CC65 1 D BE7 BG7 RC120 1 +V_SM_VREF S +GFX_CORE SA_DIMM_VREFDQ SB_DIMM_VREFDQ AY43 G 2 SM_VREF Intel DDR Vref M3 +1.5V_CPU +V_SM_VREF should have 20 mil trace width E G 1 VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56] D S AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61 POWER VREF 29A DDR3 UC1G GRAPHICS +GFX_CORE C 0.1U_0402_10V7K A 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Ivy Bridge_POWER-2 Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 9 of 46 A B C D E UC1H UC1I CFG Straps for Processor (CFG[17:0] internal pull high 5~15K to VCCIO) UC1E IVY-BRIDGE_BGA1023 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 H43 K43 H45 K45 F48 TP@ PAD RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_DIE_SENSE T87 H48 K48 BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24 A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61 RSVD6 RSVD7 RC79 1K_0402_1% @ N42 L42 L45 L47 1 M13 M14 U14 W14 P13 PEG Static Lane Reversal - CFG2 is for the 16x 1: Normal Operation; Lane # definition matches socket pin map definition CFG2 AT49 K24 * 0:Lane Reversed CFG4 RSVD41 RSVD42 RSVD43 RSVD44 AH2 AG13 AM14 AM15 RC82 1K_0402_1% IEDP@ N50 TheseRSVD45 pins are for solder joint reliability and non-critical to function. For BGA only. Embedded Display Port Presence Strap DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 N59 N58 1 BCLK_ITP BCLK_ITP# 2 CFG4 CFG5 CFG6 CFG7 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] 1 CFG2 B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 2 T89 PAD A4 C4 D3 DC_TEST_C4_D3 D1 A58 A59 C59 DC_TEST_A59_C59 A61 C61 DC_TEST_A61_C61 D61 BD61 BE61 BE59 DC_TEST_BE61_BE59 BG61 BG59 DC_TEST_BG61_BG59 BG58 BG4 BG3 BE3 DC_TEST_BG3_BE3 BG1 BE1 DC_TEST_BG1_BE1 BD1 * CFG4 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port 2 CFG7 1 VSS CFG2 CFG0 TP@ IVY-BRIDGE_BGA1023 RC85 1K_0402_1% @ <BOM> CPU@ 2 VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] RESERVED VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48 PEG DEFER TRAINING CFG7 <BOM> * 1: (Default) PEG Train immediately following xxRESETB de assertion 3 0: PEG Wait for BIOS for training CPU@ CFG6 1 1 CFG5 RC83 1K_0402_1% @ RC84 1K_0402_1% @ 2 3 VSS VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15 2 2 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13 NCTF 1 A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34 PCIE Port Bifurcation Straps IVY-BRIDGE_BGA1023 <BOM> * CPU@ CFG[6:5] 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled; function 2 disabled 01: Reserved - (Device 1 function 1 disabled; function 2 enabled) 4 4 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title Ivy Bridge_GND/RSVD/CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 10 of 46 5 4 +1.5V JDDR3L 02/20 Delete CD2, CD15 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 7 C DDRA_CKE0 7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 7 7 DDRA_CLK0 DDRA_CLK0# DDR_A_MA10 7 DDR_A_BS0 7 7 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 7 DDRA_SCS1# DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 B DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 +3VS 1 +0.75VS A 205 2 CD26 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_D[0..63] DDR_A_D6 DDR_A_D7 7 DDR_A_MA[0..15] 7 D DDR_A_D12 DDR_A_D13 SM_DRAMRST# 7,12 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 +1.5V DDR_A_D30 DDR_A_D31 RD1 1K_0402_1% 7 DDRA_CKE1 +VREF_DQA DDR_A_MA15 DDR_A_MA14 C DDR_A_MA11 DDR_A_MA7 RD2 1K_0402_1% DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDRA_CLK1 DDRA_CLK1# 7 7 DDR_A_BS1 DDR_A_RAS# 7 7 DDRA_SCS0# DDRA_ODT0 7 7 DDRA_ODT1 7 +1.5V RD6 1K_0402_1% +VREF_CAA DDR_A_D36 DDR_A_D37 CD16 DDR_A_D38 DDR_A_D39 2 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 RD7 1K_0402_1% 1 0.1U_0402_10V7K DDR_A_DQS#4 DDR_A_DQS4 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_A_DQS#[0..7] 7 1 DDR_A_D10 DDR_A_D11 DDR_A_DQS[0..7] 7 DDR_A_DQS#0 DDR_A_DQS0 2 DDR_A_DQS#1 DDR_A_DQS1 DDR3 SO-DIMM A Standard Type 1 Close to JDDRL.1 DDR_A_D4 DDR_A_D5 2 DDR_A_D8 DDR_A_D9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 DDR_A_D2 DDR_A_D3 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 2 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 1 1 0.1U_0402_10V7K D DDR_A_D0 DDR_A_D1 1 CD1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 2 +1.5V +VREF_DQA 3 B 02/20 Delete CD2, CD15 Layout Note: Place near JDDRL close to JDDRL.126 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA Layout Note: Place near JDDRL1.203 and 204 DDR_A_D52 DDR_A_D53 +1.5V DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_SMBDATA PM_SMBCLK +1.5V +0.75VS CD8 1 2 10U_0603_6.3V6M CD20 1 2 0.1U_0402_10V7K CD24 2 1 1U_0402_6.3V6K CD9 1 2 10U_0603_6.3V6M CD17 1 2 0.1U_0402_10V7K CD21 2 1 1U_0402_6.3V6K CD10 1 2 10U_0603_6.3V6M CD18 1 2 0.1U_0402_10V7K CD11 1 2 10U_0603_6.3V6M CD19 1 2 0.1U_0402_10V7K CD12 1 2 10U_0603_6.3V6M CD13 1 2 10U_0603_6.3V6M 12,17,26,33 12,17,26,33 +0.75VS A 206 LCN_DAN06-K4406-0102 Conn@ 0.1U_0402_10V7K 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification SPD setting (SA0, SA1) PU/PD by Channel A/B ->Channel A 00 ->Channel B 01 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DDRIII-SODIMM0 Rev 1.0 VFKTA Date: 5 4 3 2 Monday, March 11, 2013 Sheet 1 11 of 46 B +1.5V C +1.5V DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 7 DDRB_CKE0 2 7 DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 7 7 DDRB_CLK0 DDRB_CLK0# DDR_B_MA10 7 DDR_B_BS0 7 7 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 7 DDRB_SCS1# DDR_B_D32 DDR_B_D33 3 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 +3VS 4 2 1 RD15 10K_0402_5% +0.75VS 1 205 CD49 2 0.1U_0402_10V7K CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G2 DDR_B_DQS[0..7]7 1 DDR_B_D[0..63] 7 DDR_B_MA[0..15] 7 SM_DRAMRST# 7,11 DDR_B_D14 DDR_B_D15 +1.5V DDR_B_D20 DDR_B_D21 RD10 1K_0402_1% DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 RD11 1K_0402_1% DDR_B_D30 DDR_B_D31 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 11/28 Move RD10, RD11 to page 12 +VREF_DQB DDRB_CKE1 7 2 DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 DDRB_CLK1# 7 7 DDR_B_BS1 DDR_B_RAS# 7 7 DDRB_SCS0# DDRB_ODT0 7 7 DDRB_ODT1 7 +1.5V RD12 1K_0402_1% +VREF_CAB DDR_B_D36 DDR_B_D37 02/20 Delete CD28, CD46 CD47 DDR_B_D38 DDR_B_D39 1 2 DDR_B_D44 DDR_B_D45 0.1U_0402_10V7K DDR_B_DQS#4 DDR_B_DQS4 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_B_DQS#[0..7]7 DDR_B_D12 DDR_B_D13 1 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D6 DDR_B_D7 2 Close to JDDRH.1 DDR_B_D8 DDR_B_D9 DDR_B_DQS#0 DDR_B_DQS0 1 2 DDR_B_D4 DDR_B_D5 2 02/20 Delete CD28, CD46 DDR_B_D2 DDR_B_D3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 0.1U_0402_10V7K 1 1 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 CD27 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 1 DDR_B_D0 DDR_B_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 E DDR3 SO-DIMM B Standard Type JDDR3H +VREF_DQB D RD13 1K_0402_1% 2 A 3 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 Layout Note: Place near JDDRH Close to JDDRH.126 Layout Note: Place these 4 Caps near Command and Control signals of DIMMB Layout Note: Place near JDDRH.203 and 204 DDR_B_D52 DDR_B_D53 +1.5V +1.5V CD31 1 DDR_B_D54 DDR_B_D55 CD41 1 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_SMBDATA PM_SMBCLK +0.75VS 2 47U_0805_6.3V6M CD33 1 2 0.1U_0402_10V7K CD45 2 1 1U_0402_6.3V6K CD29 1 2 0.1U_0402_10V7K CD42 2 1 1U_0402_6.3V6K CD30 1 2 0.1U_0402_10V7K CD32 1 2 0.1U_0402_10V7K 2 10U_0603_6.3V6M CD36 1 2 10U_0603_6.3V6M CD37 1 2 10U_0603_6.3V6M CD38 1 2 10U_0603_6.3V6M CD39 1 2 10U_0603_6.3V6M CD40 1 2 10U_0603_6.3V6M 11,17,26,33 11,17,26,33 +0.75VS 4 11/28 Change CD31 47U 1206 to 0805 size (SE00000PL00) 206 LCN_DAN06-K4806-0102 Conn@ 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification SPD setting (SA0, SA1) PU/PD by Channel A/B ->Channel A 00 ->Channel B 01 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DDRIII-SODIMM1 Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 12 of 46 A B C D E LCD POWER CIRCUIT For eDP Panel CAM_EMI@ USB20_N11_R 1 USB20_P11_R 4 1 2 4 3 2 USB20_N11 3 USB20_P11 Reserve for power consumption Remove on PVT phase Need check eDP&LVDS both 3V power rail. 20 +3VS H_EDP_AUXN C891 1 H_EDP_TXP0 C912 H_EDP_TXN0 C913 H_EDP_TXP1 C914 C915 H_EDP_TXN1 LVDS_EDID_CLK 20 LVDS_EDID_DATA 1.5A Reserve for EMI request LVDS_TXOUT0+ LVDS_TXOUT0- @TOUCH_EMI@ 1 2 R267 0_0402_5% LVDS_TXOUT11 USB20_N8_R 4 1 2 4 3 VOUT 2 USB20_P8 3 USB20_N8 1 1 Rshort@ 2 +LCD_VDD_OUT R106 0_0805_5% VIN W=60mils I rush=1.5A 1 GND 4 2 SS 2013/02/06 Add R266 , R267 Co-lay L57 TOUCH_EMI@ USB20_P8_R +LCD_VDD U16 5 +LCD_VDD_SS LVDS_TXOUT1+ 02/20 Change R106 to shortpad W=60mils L55 WCM-2012-900T_0805 EN 3 APL3512ABI-TRG_SOT23-5 C7 0.015u_0402_16V_X7R 20 19 LCD_ENVDD 2 6 IEDP@ 1 20.1U_0402_10V7K IEDP@ 1 20.1U_0402_10V7K IEDP@ 1 20.1U_0402_10V7K 6 IEDP@ 1 20.1U_0402_10V7K 6 IEDP@ 1 20.1U_0402_10V7K 6 IEDP@ 1 20.1U_0402_10V7K 6 20 R112 100K_0402_5% L57 WCM-2012-900T_0805 02/20 Change C7 to SE076153K80 (15nF) for LCD sequence tuning 1 2 R266 0_0402_5% @TOUCH_EMI@ 1 C890 1 H_EDP_AUXP 2 6 Reserve for EMI request For LVDS 1ch Panel LVDS colay eDP cable 1 LVDS@ 2 19 R262 0_0402_5% 1 LVDS@ 2 19 R263 0_0402_5% 1 LVDS@ 2 19 R265 0_0402_5% 1 LVDS@ 2 19 R264 0_0402_5% LCD_TXOUT0+ 2 LCD_TXOUT0LCD_TXOUT1+ LCD_TXOUT1LCD_TXOUT2+ 19 LCD_TXOUT2- 19 LCD_TXCLK+ 19 LCD_TXCLK- 19 19 LCD_EDID_CLK 19 LCD_EDID_DATA 1 LVDS@ 2 R300 0_0402_5% 1 LVDS@ 2 R299 0_0402_5% Pin define will be change after ME ready LVDS_TXOUT0+ 2 LVDS_TXOUT0+5VS LVDS_TXOUT1+ LVDS_TXOUT1- JLVDS pin1-4 Touch function for panel LCD_TXOUT2+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LCD_TXOUT2LCD_TXCLK+ pin5-10 For Webcam with single or dual MIC LCD_TXCLKLVDS_EDID_CLK LVDS_EDID_DATA pin11-30 For LVDS or EDP panel 3 GND GND GND GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 Rshort@ 2 R390 0_0603_5% +5VS_LVDS_TOUCH USB20_N8_R USB20_P8_R BKOFF# INT_MIC_DATA INT_MIC_CLK INT_MIC_DATA 30 INT_MIC_CLK 30 +3VS USB20_P11_R USB20_N11_R +3VS_LVDS_CAM +LCD_VDD 1 Rshort@ 2 R389 0_0603_5% +3VS LVDS_EDID_CLK LVDS_EDID_DATA LVDS_TXOUT0LVDS_TXOUT0+ LVDS_TXOUT1LVDS_TXOUT1+ LCD_TXOUT2LCD_TXOUT2+ LED_PWM BKOFF#_R 3 +LCD_INV Irush=1.5A B+ 60mils +LCD_INV L2 2 1 FBMA-L11-201209-221LMA30T_0805 EMI@ 5 G IN2 1 2 EC_ENBKL 19,32 BKOFF# 32 1 RB751V40_SC76-2 2 D17 PCH_PWM 19 1 P LED_PWM IN1 O LVDS@ R131 47K_0402_5% SN74AHC1G08DCKR_SC70-5 2 2 R113 10K_0402_5% 60mils IEDP@ U17 3 1 2 0_0402_5% 2 4 RB751V40_SC76-2 Irush=1.5A 31 32 33 34 35 +3VS 1 D15 +3VS 60mils CPU_EDP_HPD 6 Reserve for eDP panel potential issue IEDP@1 R103 20mils +LCD_VDD Irush=1.5A LCD_TXCLKLCD_TXCLK+ Conn@ BKOFF#_R 20mils 1 2 R147 0_0402_5% LVDS@ 4 4 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LVDS Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 13 of 46 A B C D E CRT CONNECTOR 1 1 UMA_CRT_R 19 L3 1 CRT_R_L UMA_CRT_G 19 L4 1 2 NBQ100505T-800Y_0402 CRT_EMI@ 2 NBQ100505T-800Y_0402 CRT_EMI@ 1 2 NBQ100505T-800Y_0402 CRT_EMI@ CRT_G_L UMA_CRT_B 19 L5 CRT_B_L T65, T66: for ATE JCRT 2 C240 2 2 1 C241 2 1 C242 2 CRT@ 1 C243 2 T65 PAD CRT_R_L 2.2P_0402_50V8C C239 1 CRT@ 2.2P_0402_50V8C C238 1 CRT@ 2.2P_0402_50V8C 1 CRT@ 2.2P_0402_50V8C 2 1 150_0402_1% 2 1 150_0402_1% 2 1 150_0402_1% R138 R139 R140 CRT@ 2.2P_0402_50V8C CRT@ 2.2P_0402_50V8C CRT@ CRT@ CRT@ CRT_DDC_DAT CRT_G_L HSYNC CRT_B_L +HDMI_5V_OUT VSYNC T66 PAD CRT_DDC_CLK USE HDMI POWER 11/28 change BOM structureC238 C239 C240 C241 C242 C243 to CRT@EMI@ 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 G G 16 17 C-H_13-12201513CP Conn@ 2 2 02/20 Delete C250 0.1u CRT@ +3VS 7 VCC_VIDEO VIDEO1 VCC_DDC VIDEO2 DDC_IN1 VIDEO3 DDC_IN2 DDC_OUT1 8 1 C15 +HDMI_5V_OUT 2 0.22U_0402_16V7K 3 CRT_R_L 4 CRT_G_L 3 UMA_CRT_DATA 10 5 CRT_B_L 19 UMA_CRT_CLK 11 19 UMA_CRT_VSYNC 19 UMA_CRT_HSYNC 13 15 6 SYNC_IN1 DDC_OUT2 SYNC_IN2 SYNC_OUT1 GND SYNC_OUT2 R153 4.7K_0402_5% CRT@ R159 4.7K_0402_5% 1 19 2 2 BYP 2 +3VS VCC_SYNC 1 U49 1 +HDMI_5V_OUT CRT@ 9 CRT_DDC_DAT 12 CRT_DDC_CLK 14 22_0402_5% VSYNC_R 1 CRT@ 2 R62 VSYNC 16 22_0402_5% HSYNC_R 1 CRT@ 2 R63 HSYNC 3 TPD7S019-15DBQR_SSOP16 CRT@ 11/29 add 22-ohm (PN: SD028220A80) on CRT HSYNC/VSYNC trace. 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Issued Date Deciphered Date 2015/04/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title CRT Size B C D Rev 1.0 VFKTA Date: A Document Number Monday, March 11, 2013 Sheet E 14 of 46 A B C D OE# A Y L L L L H H H X Z HDMI POWER CIRCUIT RPY1 1 2 3 4 +3VS +HDMI_5V_OUT 8 7 6 5 UMA_HDMI_CLK UMA_HDMI_DATA HDMI_SCLK HDMI_SDATA 2.2K_0804_8P4R_5% E VIN = 5V, IOUT = 0.5A , RDS(ON) Current Limit: TYP=0.8A ; MAX=1A TYP=95m ; MAX=115m 1 1 +HDMI_5V_OUT +HDMI_5V_OUT UY2 1 RY1 2 HDMI_HPD_U 1 1K_0402_5% 2 HDMI_HPD_C RY2 100K_0402_5% UY1 Y 4 2 CY18 3 CY4 0.1U_0402_16V4Z 0.1U_0402_10V7K 2 IN 5 +5VS GND FLG EN 4 AP2151DWG-7_SOT25-5 1 HDMI_HPD OUT SA00006H000 1 5 P OE# A 74AHCT1G125GW_SOT353-5 3 G 2 1 +3VS 2 1 2 11/28 Update HDMI current limited IC from AP230W-7 to AP2151DDWG-7. G BSS138 1N SOT23-3 1 HDMI_SCLK 2 1 RY3 2.2K_0402_5% D QY1 G 2 UMA_HDMI_CLK S 19 3 UMA_HDMI_CLK 3 UMA_HDMI_DATA HDMI_SDATA HDMI_HPD +3VS HDMI_HPD D UMA_HDMI_DATA S 19 BSS138 1N SOT23-3 1 19,21 QY2 2013/02/06 change QY1 QY2 to SB00000PF00 for X1 code 2 2 LY1 19 19 UMA_HDMI_CLKUMA_HDMI_CLK+ CY2 1 2 0.1U_0402_16V7K HDMI_TXC- 1 CY1 1 2 0.1U_0402_16V7K HDMI_TXC+ 4 EMI@ 1 2 4 3 2 HDMI Connector 3 WCM-2012HS-900T_4P JHDMI HDMI_HPD_C +HDMI_5V_OUT LY2 19 UMA_HDMI_TX0- 19 UMA_HDMI_TX0+ CY5 1 2 0.1U_0402_16V7K HDMI_TXD0- 1 CY3 1 2 0.1U_0402_16V7K HDMI_TXD0+ 4 HDMI_SDATA HDMI_SCLK EMI@ 1 2 4 3 2 HDMI_R_CK3 HDMI_R_CK+ HDMI_R_D0- WCM-2012HS-900T_4P HDMI_R_D0+ HDMI_R_D1LY3 3 19 UMA_HDMI_TX1- 19 UMA_HDMI_TX1+ CY7 CY6 1 1 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K HDMI_TXD1HDMI_TXD1+ 1 4 HDMI_R_D1+ HDMI_R_D2- EMI@ 1 2 4 3 2 HDMI_R_D2+ 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ GND D2GND D2_shield GND D2+ GND 23 22 21 20 3 3 Conn@ WCM-2012HS-900T_4P 11/28 Add @ to JHDMI LY4 19 UMA_HDMI_TX2- CY9 1 2 0.1U_0402_16V7K HDMI_TXD2- 1 CY8 1 2 0.1U_0402_16V7K HDMI_TXD2+ 4 HDMI_R_D0HDMI_R_D0+ HDMI_R_CKHDMI_R_CK+ EMI@ 1 2 4 3 2 680 +-5% 8P4R 5 4 6 3 7 2 8 1 RPY3 19 UMA_HDMI_TX2+ 3 WCM-2012HS-900T_4P 12/04 SWAP RPY4 netname HDMI_R_D1HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+ 680 +-5% 8P4R 5 4 6 3 7 2 8 1 HDMI45@ RO0000003HM 4 +5VS 1 QY4 ZZZ HDMI Royalty D 3 RPY4 S 2N7002KW_SOT323-3 2 G 10/18 Modify the BOM structure @ to HDMI45@ , change Location HDMI to ZZZ. 4 HDMI W/Logo + HDCP HDMI W/O Logo: RO0000001HM HDMI W/Logo: RO0000002HM HDMI W/Logo + HDCP: RO0000003HM 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification please manually load this virtual material to 45@ BOM 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D HDMI Conn. Document Number Rev 1.0 VFKTA Monday, March 11, 2013 Sheet E 15 of 46 5 4 JCMOS SP@ 26 1 2 CH5 1 1U_0402_6.3V6K YH1 32.768KHZ_12.5P_1TJF125DP1A000D 2 2 D CH3 1 NOGCLK@ 15P_0402_50V8J Integrated SUS 1.05V VRM Enable High - Enable Internal VRs (must be always pulled high) PCH_INTVRMEN 30 PCH_SPKR +RTCVCC RH12 1 2 SM_INTRUDER# 1M_0402_5% 2 PCH_INTVRMEN 330K_0402_5% RH33 1 +3VS 30 2 1K_0402_5% PCH_RTCRST# D20 PCH_SRTCRST# G22 SM_INTRUDER# K22 PCH_INTVRMEN C17 AZ_BITCLK N34 AZ_SYNC L34 PCH_SPKR T10 AZ_RST# K34 AZ_SDIN0_HD AZ_SDIN0_HD C34 * PCH_SPKR A34 32 1 Rshort@ 2 AZ_SDOUT RH25 0_0402_5% PWRME_CTRL +RTCBATT 1 C N32 Change Net name due to this function is high active 2 2 3 T70 PAD 1 A36 C36 DH1 BAS40-04_SOT23-3 +RTCVCC E34 G34 T67 PAD +3VL CH8 T68 PAD 0.1U_0402_10V7K T69 PAD RTCX2 INT.PH INT.PH INT.PH INT.PH 20K 20K 20K 20K FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 LPC C20 PCH_SPKR High = Enabled "No Reboot Mode" Low = Disabled (Default) @ 1 RH36 PCH_RTCX2 RTCX1 RTCRST# FWH4 / LFRAME# SRTCRST# INT.PH 20K LDRQ0# INT.PH 20K LDRQ1# / GPIO23 INTRUDER# INTVRMEN SERIRQ HDA_BCLK HDA_SYNC INT.PD 20K SPKR INT.PD 20K SATA 6G JME SP@ 1 2 2 PCH_SRTCRST# A20 HDA_RST# HDA_SDIN0 INT.PD 20K HDA_SDIN1 INT.PD 20K HDA_SDIN2 INT.PD 20K HDA_SDIN3 INT.PD 20K HDA_SDO INT.PD 20K HDA_DOCK_EN# / GPIO33 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA NOGCLK@ PCH_RTCX1 RTC CH2 1 NOGCLK@ 15P_0402_50V8J IHDA RH24 1 20K_0402_5% UH1A 2 Placement near to YH1 iME Setting. SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST# / GPIO13 SATA5RXN SATA5RXP SATA5TXN SATA5TXP PCH_JTAG_TCK J3 JTAG_TCKINT.PD 20K PCH_JTAG_TMS H7 JTAG_TMSINT.PH 20K SATAICOMPO PCH_JTAG_TDI K5 JTAG_TDI INT.PH 20K SATAICOMPI PCH_JTAG_TDO H1 JTAG_TDO SATA3RCOMPO SATA3COMPI AZ_BITCLK_HD AZ_BITCLK_HD AZ_SYNC_HD AZ_RST_HD# AZ_SDOUT_HD 1 2 3 4 8 7 6 5 AZ_BITCLK AZ_SYNC_R AZ_RST# AZ_SDOUT PCH_SPICLK T3 PCH_SPICS0# Y14 PCH_SPICS1# T1 PCH_SPIDI V4 SPI_MOSI INT.PD PCH_SPIDO U3 SPI_MISO INT.PH SPI_CLK SATA3RBIAS HDA_SDO ME debug mode, this signal has a weak internal pull down = Disable (default) *Low High = Enable (flash descriptor security overide) B C38 A38 B37 C37 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 D36 LPC_FRAME# D V5 SERIRQ AM3 AM1 AP7 AP5 SPI_CS1# SATALED# 20K 20K AD7 AD5 AH5 AH4 SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 Y7 Y5 AD3 AD1 D 1 S Y3 Y1 AB3 AB1 8 7 6 5 C 10K_0804_8P4R_5% Y11 Y10 SATAICOMP 1 RH43 2 37.4_0402_1% +1.05VS_PCH SATA3_COMP 1 RH48 2 49.9_0402_1% +1.05VS_PCH 1 RH41 2 750_0402_1% AB12 AB13 AH1 RBIAS_SATA3 SATA0GP / GPIO21 P3 SATA_LED# V14 SATA1GP / GPIO19 INT.PH 20K PCH_GPIO21 P1 PCH_GPIO19 PCH_GPIO19 20(PH) BOOT BIOS Strap Bit 0 B change UH4 2M ROM circuit to "@". SPI ROM for Win8 (2MByte ) SPI ROM for BIOS & ME (4MByte ) UH4 RH269 PCH_SPIDO 1 @ 0_0402_5% PCH_SPICS0# PCH_SPIDO 1 Rshort@ 2 PCH_SPI0_DO RH68 +3VALW_PCH 0_0402_5% AZ_SYNC 02/20 change RH67, RH68 to short pad BSS138_NL_SOT23-3 1 2 3 4 CS# DO WP# GND 2 PCH_SPICS1# PCH_SPI1_DO +3VALW_PCH 10/18B change from +3vs to +3VALW_PCH VCC HOLD# CLK DI 8 7 6 5 1 2 3 4 CS# SO WP# GND @ VCC HOLD# SCLK SI 8 7 6 5 RH267 1 @ 1 RH271 @ PCH_SPI1_CLK PCH_SPI1_DI 0_0402_5% 2 PCH_SPICLK 2 PCH_SPIDI 0_0402_5% MX25L1606EM2I-12G_SO8 PCH_SPI0_CLK PCH_SPI0_DI RH66 0_0402_5% 1 Rshort@ 2 PCH_SPICLK 1 Rshort@ 2 PCH_SPIDI RH67 0_0402_5% 10/19A Change RH267 to short pad 32M EN25Q32B-104HIP SOP 8P change UH3 （2013/02/06 EOL）to SA00004LI00 from SA00003K800 for X1 code 10/19A Remove RH65, CH7 4MB ROM P/N: SA00003K800 SA00004LI00 2MB ROM P/N: SA000041N00 SA00003FO10 10/19A Remove RH69, CH21 1 RH56 1M_0402_5% +3VS RPH1 1 2 3 4 SERIRQ PCH_GPIO21 PCH_GPIO19 SATA_LED# 02/20 Delete CH100 0.1U 2 QH1 1 ODD +3VALW_PCH 10/19A Change RH66 to short pad UH3 2 2 G 3 25 SATA_PRX_C_DTX_N2 25 SATA_PRX_C_DTX_P2 25 SATA_PTX_DRX_N2 25 SATA_PTX_DRX_P2 AB8 AB10 AF3 AF1 02/20 Delete CH6 0.1U AZ_SYNC_R HDD 11/29 change RH267 change from shortpad to 0-ohm +3VALW_PCH RH55 1K_0402_5% 25 SATA_PRX_C_DTX_N0 25 SATA_PRX_C_DTX_P0 25 SATA_PTX_DRX_N0 25 SATA_PTX_DRX_P0 AM10 AM8 AP11 AP10 11/29 +3VALW_PCH +5VS 32 SERIRQ SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 11/28 Change UH3 from socket to IC, modify the footprint signal has a weak internal pull down *This H=>On Die PLL is supplied by 1.5V L=>On Die PLL is supplied by 1.8V Need to pull high for Chief River Mobile platform LPC_FRAME# 32 E36 K36 PANTHER-POINT_FCBGA989 HM76R3@ HDA_SYNC 32 32 32 32 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 SPI_CS0# 33_8P4R_5% SPI RPH2 30 30 30 30 1 2 JTAG CH4 1 1U_0402_6.3V6K 2 RH26 GCLK@ 1 2 PCH_RTCX1 0_0402_5% PCH_RTCX1_R NOGCLK@ PCH_RTCRST# RH2 10M_0402_5% 2 1 2 2 RH23 1 20K_0402_5% 1 CMOS Setting, near DDR Door +RTCVCC 3 Socket: SP07000F500/SP07000H900 Please place UH3 & UH4 close to UH1 PCH, please place RH66, RH67, RH68 near UH3 Please place RH267 near RH66, Please place RH271 near RH67, Please place RH269 near RH68. A A RPH9 32 32 32 32 EC_SDIO EC_CS0# EC_SCK EC_SDI 1 2 3 4 8 7 6 5 PCH_SPI0_DO PCH_SPICS0# PCH_SPI0_CLK PCH_SPI0_DI 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 33_8P4R_5% 885@ 2015/04/19 Deciphered Date Title PCH_HDA/JTAG/SATA/SPI/LPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Reserve for NPCE885N EC Date: 5 Rev 1.0 VFKTA 4 3 2 Sheet Monday, March 11, 2013 1 16 of 46 5 4 3 2 1 UH1B BG36 BJ36 AV34 AU34 D +3VS RH1041 2 10K_0402_5% CLKREQ_WLAN# RH95 1 2 10K_0402_5% CLKREQ_LAN# BF36 BE36 AY34 BB34 BG37 BH37 AY36 BB36 Intel Spec: PCIECLK_RQ0# is suspend well, but we pull high to +3VS for LAN en/disable function BJ38 BG38 AU36 AV36 BG40 BJ40 AY40 BB40 +3VALW_PCH RPH10 8 7 6 5 1 2 3 4 EC_SMI# USB_OC#0 SLP_CHG_CB1 SLP_CHG_CB0 EC_SMI# USB_OC#0 SLP_CHG_CB1 SLP_CHG_CB0 21,32 20,29,32 20,29 20,29 BE38 BC38 AW38 AY38 10K_0804_8P4R_5% J2 CLKREQ_LAN# 27 CLKREQ_LAN# AB49 AB47 CLK_WLAN# 26 CLK_WLAN 26 CLK_WLAN# CLK_WLAN WLAN Y40 Y39 CLK_LAN# 27 CLK_LAN 27 CLK_LAN# CLK_LAN LAN C M1 CLKREQ_WLAN# 26 CLKREQ_WLAN# AA48 AA47 V10 Y37 Y36 A8 +3VALW_PCH SMBDATA SML0ALERT# / GPIO60 SML0CLK SML0DATA 8 7 6 5 Y43 Y45 LVDS_SEL PASSWORD_CLEAR# PCH_SMBALERT# LAN_EN L12 4 3 2 1 L14 3 PCH_SMBDATA PCH_SMBCLK PCH_SMLDATA1 PCH_SMLCLK1 A12 DRAMRST_CNTRL_PCH 4 AB42 AB40 Note: place in DDR area E6 PASSWORD_CLEAR# SML1CLK / GPIO58 SML1DATA / GPIO75 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CL_CLK1 CL_DATA1 CL_RST1# V40 V42 T13 LVDS_SEL 1 IEDP@ 2 RH276 10K_0402_5% PANEL_SEL V38 V37 K12 PANEL_SEL AK14 AK13 C8 PCH_SMLCLK0 G12 PCH_SMLDATA0 QH4B C13 LAN_EN 27 LAN_EN E14 PCH_SMLCLK1 M16 PCH_SMLDATA1 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P PCIECLKRQ1# / GPIO18 CLKOUT_DP_N CLKOUT_DP_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_GND1_N CLKIN_GND1_P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N CLKIN_SATA_P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P REFCLK14IN PCIECLKRQ5# / GPIO44 INT. PH 20K CLKOUT_PEG_B_N CLKOUT_PEG_B_P A Channel 25,32 EC_SMB_DA2 1 25,32 EC_SMB_CK2 2N7002DW-T/R7_SOT363-6 +3VALW_PCH M7 Control Link only for support Intel IAMT. T11 P10 DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5% PCH_SMLCLK0 RH73 2 1 2.2K_0402_5% PCH_SMLDATA0 RH77 2 1 2.2K_0402_5% M10 PCH_GPIO47 AB37 AB38 PCH_GPIO47 CLKIN_PCILOOPBACK XTAL25_IN XTAL25_OUT XCLK_RCOMP AV22 AU22 INT. PD 20K CLKOUT_PCIE7N CLKOUT_PCIE7P CLKOUTFLEX0 / GPIO64 INT. PD 20K INT. PH 20K CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUTFLEX1 / GPIO65 INT. PD 20K CLKOUTFLEX2 / GPIO66 INT. PD 20K CLKOUTFLEX3 / GPIO67 C CLK_CPU_EDP#5 CLK_CPU_EDP 5 BF18 BE18 PCH_CLK_DMI# PCH_CLK_DMI BJ30 BG30 CLKIN_GND1# CLKIN_GND1 G24 E24 CLK_DOT# CLK_DOT AK7 AK5 CLK_SATA# CLK_SATA 1 2 3 4 PCH_CLK_DMI PCH_CLK_DMI# CLKIN_GND1# CLKIN_GND1 120 MHz for eDP 8 7 6 5 10K_0804_8P4R_5% RPH4 1 2 3 4 CLK_DOT# CLK_DOT CLK_SATA CLK_SATA# 8 7 6 5 10K_0804_8P4R_5% From Clock Gen. CLK_14M_PCH H45 CLK_PCILOOP V47 V49 PCH_X1 PCH_X2 Y47 XCLK_RCOMP 1 RH115 K43 CLK_FLEX0 F47 CLK_FLEX1 H47 CLK_FLEX2 K49 PCH_GPIO67 2 10K_0402_5% @EMI@ CLK_PCILOOP K45 RH87 1 CLK_14M_PCH 1 RH70 2 10_0402_5% @EMI@ 1 2 CH9 10P_0402_50V8J CLK_PCILOOP 20 PAD T74 PAD T73 PCH_X1 Placement near to YH2 2 90.9_0402_1% T72 B RH37 1 2 26 0_0402_5% GCLK@ PCH_X1_R +1.05VS_VCCDIFFCLKN +3VS RH117 NOGCLK@ 2 1 1M_0402_5% NOGCLK@YH2 25MHZ_20PF_7V25000016 PAD 1 RH261 2 10K_0402_5% PCH_X1 CH26 PANEL_SEL 1 10K_0402_5% RPH3 CLK_CPU_DMI#5 CLK_CPU_DMI 5 AM12 AM13 CLKOUT_PCIE6N CLKOUT_PCIE6P PCIECLKRQ6# / GPIO45 2 RH89 9/28 Delete CLK_VGA, change CLK_REQ_VGA#to PCH_GPIO47 PEG_B_CLKRQ# / GPIO56 PCIECLKRQ7# / GPIO46 D 4 2N7002DW-T/R7_SOT363-6 6 9/28 Change DGPU_PRSNT# to PCH_GPIO67, then pull high to +3VS LVDS_SEL 11,12,26,33 +3VS 3 HM76R3@ PANTHER-POINT_FCBGA989 LVDS_SEL PM_SMBCLK 1 +3VALW_PCH PEG_A_CLKRQ# / GPIO47 FLEX CLOCKS JPW SP@ 11,12,26,33 2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue 1 PANEL_SEL 2 1 LVDS@ 2 RH119 10K_0402_5% PM_SMBDATA 2N7002DW-T/R7_SOT363-6 B +3VALW_PCH 4.7K_0402_5% 4.7K_0402_5% 2N7002DW-T/R7_SOT363-6 QH3A 7,9 DRAMRST_CNTRL_PCH 10K_0804_8P4R_5% V45 V46 RH102 RH103 5 PCH_SMBDATA 5 6 7 8 2 C9 RPH5 (PH) QH4A SML1ALERT# / PCHHOT# / GPIO74 RPH6 1 2 3 4 PCH_SMBCLK 6 PERN4 PERP4 PETN4 PETP4 PERN6 PERP6 PETN6 PETP6 H14 QH3B 2.2K_0804_8P4R_5% PERN3 PERP3 PETN3 PETP3 PERN5 PERP5 PETN5 PETP5 PCH_SMBALERT# 5 1 0.1U_0402_10V7K 26 1 0.1U_0402_10V7K 26 PERN2 PERP2 PETN2 PETP2 E12 2 CH14 2 CH17 2 BE34 BF34 BB32 AY32 SMBCLK Link WLAN PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2 SMBALERT# / GPIO11 SMBUS 26 PCIE_PRX_WLANTX_N2 26 PCIE_PRX_WLANTX_P2 PCIE_PTX_C_WLANRX_N2 PCIE_PTX_C_WLANRX_P2 1 0.1U_0402_10V7K 27 1 0.1U_0402_10V7K 27 +3VS +3VALW_PCH PERN1 PERP1 PETN1 PETP1 Controller CH13 2 CH11 2 BG34 BJ34 AV32 AU32 CLOCKS LAN PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_LANRX_N1 PCIE_PTX_LANRX_P1 PCI-E* 27 PCIE_PRX_C_LANTX_N1 27 PCIE_PRX_C_LANTX_P1 PCIE_PTX_C_LANRX_N1 PCIE_PTX_C_LANRX_P1 27P_0402_50V8J NOGCLK@ 1 1 1 3 GND GND 2 4 3 PCH_X2 1 CH27 27P_0402_50V8J 2 NOGCLK@ 2 PCH_GPIO67 H L PANEL_SEL H L Single (Default) Dual Channel LVDS EDP PCH_GPIO67 H L M/B SKU UMA DIS/OPT A Compal common design SW request to add DGPU_Present on this GPIO67 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title PCH_PCI-E/SMBUS/CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: 5 4 3 2 Monday, March 11, 2013 Sheet 1 17 of 46 5 4 3 2 1 UH1C 8 7 6 5 PCH_SUSPWRDN#_R RI# PCH_LOW_BAT# EC_SWI# 10K_0804_8P4R_5% 2 RH163 1 PCH_RSMRST# 10K_0402_5% 6 6 6 6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 6 6 6 6 DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 6 6 6 6 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 BC24 BE20 BG18 BG20 BE24 BC20 BJ18 BJ20 AW24 AW20 BB18 AV18 AY24 AY20 AY18 AU18 DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI RPH7 1 2 3 4 D DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI +3VALW_PCH 6 6 6 6 FDI_INT 1 RH126 +1.05VS_PCH 2 DMI_COMP 49.9_0402_1% BG25 RPH17 1 2 3 4 BJ24 8 7 6 5 PM_PWROK PCH_GPIO32 PCH_GPIO37 PCH_GPIO37 1 RH127 21 2 RBIAS_CPY 750_0402_1% BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 FDI_LSYNC1 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 6 FDI_CTX_PRX_N0 6 FDI_CTX_PRX_N1 6 FDI_CTX_PRX_N2 6 FDI_CTX_PRX_N3 6 FDI_CTX_PRX_N4 6 FDI_CTX_PRX_N5 6 FDI_CTX_PRX_N6 6 FDI_CTX_PRX_N7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 D 6 FDI_CTX_PRX_P0 6 FDI_CTX_PRX_P1 6 FDI_CTX_PRX_P2 6 FDI_CTX_PRX_P3 6 FDI_CTX_PRX_P4 6 FDI_CTX_PRX_P5 6 FDI_CTX_PRX_P6 6 FDI_CTX_PRX_P7 AW16 AV12 BC10 AV14 BB10 FDI_INT 6 FDI_FSYNC0 6 FDI_FSYNC1 6 FDI_LSYNC0 6 FDI_LSYNC1 6 RH128 0_0402_5% 1 Rshort@ 2 PCH_DPWROK PCH_RSMRST# Do not support DeepSX state +RTCVCC 10K_0804_8P4R_5% DSWVREN Reserve this signal to EC by SW demand 2011/10/18a 32 PM_PWROK 1 SUSACK# 1 RH47 +3VS XDP_DBRESET# C @ESD@ 2 1 @ESD@ CC26 100P_0402_50V8J 2013/02/06 PVT Reserve CC26 CC27 32,42 2 1 2 @ RH282 K3 P12 32 PM_PWROK PM_PWROK L22 L10 DRAMPWROK 1 PCH_SUSPWRDN#_R 0_0402_5% Stuff R137 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit C12 2 XDP_DBRESET# 1K_0402_5% VGATE CC27 100P_0402_50V8J 5 SUSACK#_R 2 SUSACK#_R @ RH133 0_0402_5% 32 PCH_RSMRST# B13 PCH_RSMRST# C21 PCH_SUSPWRDN#_R (PH) 32 1 PCH_SUSPWRDN# 32 +3VALW_PCH 32,37 DRAMPWROK 2 @ RH132 0_0402_5% PBTN_OUT# 1 RH161 2 330K_0402_5% DH2 1 2 ACIN K16 PBTN_OUT# E20 PCH_ACIN H20 PCH_LOW_BAT# E10 INT.PH SUSACK# System Power Management 10/12 Delete OPTIMUS_EN# pull down DSWVRMEN 20K SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST# DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4# SUSWARN#/SUSPWRDNACK/GPIO30 PWRBTN#INT.PH SLP_S3# 20K SLP_A# INT.PD 20K ACPRESENT / GPIO31 SLP_SUS# BATLOW# / GPIO72 INT.PH 20K PMSYNCH A18 DSWVREN E22 PCH_DPWROK B9 EC_SWI# N3 PCH_GPIO32 G8 SUS_STAT# RH150 2 1 330K_0402_5% DSWVREN must be always pulled high to +RTCVCC EC_SWI#(PH) T76 * 27 C PAD 32.768 KHz N14 ：： DSWVREN - Internal Deep Sleep 1.05V regulator H Enable L Disable CLK_EC 32 PM_SLP_S5# 32 PM_SLP_S4# 32 PM_SLP_S3# 32 D10 PM_SLP_S5# H4 PM_SLP_S4# F4 PM_SLP_S3# G10 PM_SLP_A# T77 PAD G16 PM_SLP_SUS# T78 PAD AP14 H_PM_SYNC H_PM_SYNC Follow EC check list demand, but don't implement CLKRUN# this fuction 5 CH751H-40PT_SOD323-2 RI# A10 (PH) B RI# SLP_LAN# / GPIO29 K14 PANTHER-POINT_FCBGA989 HM76R3@ Reserve this signal to EC by SW demand 2011/10/18a B DH5 2 PM_PWROK 1 PCH_RSMRST# CH751H-40PT_SOD323-2 DH6 1 POK 2 32,38 CH751H-40PT_SOD323-2 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PCH_DMI/FDI/PM Rev 1.0 VFKTA Date: 5 4 3 2 Monday, March 11, 2013 Sheet 1 18 of 46 5 4 3 2 1 UH1D PCH_PW M PCH_PW M 13 13 LCD_EDID_CLK LCD_EDID_DATA D 1 RH143 J47 M45 EC_ENBKL LCD_ENVDD EC_ENBKL LCD_ENVDD 13 P45 LCD_EDID_CLK LCD_EDID_DATA T40 K47 LCTL_CLK LCTL_DATA T45 P39 2 LVDS_IBG 2.37K_0402_1% AF37 AF36 AE48 AE47 +3VS RPH8 1 2 3 4 8 7 6 5 LCTL_CLK LCTL_DATA LCD_EDID_CLK LCD_EDID_DATA 2.2K_0804_8P4R_5% 2 RH142 2 RH144 C AK39 AK40 13 13 LCD_TXCLKLCD_TXCLK+ 13 13 13 LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2- AN48 AM47 AK47 AJ48 13 13 13 LCD_TXOUT0+ LCD_TXOUT1+ LCD_TXOUT2+ AN47 AM49 AK49 AJ47 AF40 AF39 1 UMA_CRT_DATA 2.2K_0402_5% CRT@ 1 UMA_CRT_CLK 2.2K_0402_5% CRT@ AH45 AH47 AF49 AF45 AH43 AH49 AF47 AF43 1 RH154 2 UMA_CRT_B 150_0402_1% CRT@ 1 2 UMA_CRT_G RH156 150_0402_1% CRT@ 1 2 UMA_CRT_R RH152 150_0402_1% CRT@ 14 14 14 14 14 14 14 UMA_CRT_B UMA_CRT_G UMA_CRT_R UMA_CRT_CLK UMA_CRT_DATA UMA_CRT_B UMA_CRT_G UMA_CRT_R N48 P49 T49 UMA_CRT_CLK UMA_CRT_DATA T39 M40 M47 M49 UMA_CRT_HSYNC UMA_CRT_VSYNC 2 RH138 1 CRT_IREF 1K_0402_0.5% CRT@ T43 T42 L_BKLTEN L_VDD_EN INT.PD 50 SDVO_TVCLKINN INT.PD 50 SDVO_TVCLKINP AP43 AP45 INT.PD 50 SDVO_STALLN INT.PD 50 SDVO_STALLP AM42 AM40 L_BKLTCTL L_DDC_CLK L_DDC_DATA INT.PD 50 INT.PD 50 SDVO_INTN SDVO_INTP AP39 AP40 D L_CTRL_CLK L_CTRL_DATA INT.PD 20K LVD_IBG LVD_VBG SDVO_CTRLCLK SDVO_CTRLDATA INT.PD 20K LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P Digital Display Interface 13,32 13 LVDS 2 EC_ENBKL 100K_0402_5% LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 DDPC_CTRLCLK DDPC_CTRLDATA INT.PD 20K LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA INT.PD 20K DDPD_AUXN DDPD_AUXP DDPD_HPD CRT 1 RH125 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN P38 M39 AT49 AT47 AT40 UMA_HDMI_CLK15 15 UMA_HDMI_DATA HDMI_HPD 15,21 HDMI_HPD AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 UMA_HDMI_TX2-15 15 UMA_HDMI_TX2+ UMA_HDMI_TX1-15 15 UMA_HDMI_TX1+ UMA_HDMI_TX0-15 15 UMA_HDMI_TX0+ UMA_HDMI_CLK-15 15 UMA_HDMI_CLK+ 02/20 Delete RH254 100K HDMI P46 P42 AP47 AP49 AT38 RH141 2 1 100K_0402_5% AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 C M43 M36 AT45 AT43 BH41 RH255 2 1 100K_0402_5% BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PANTHER-POINT_FCBGA989 B B HM76R3@ RH138 1K_0402_5% NOCRT@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Issued Date Deciphered Date 2015/04/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PCH_CRT/LVDS/HDMI Size Document Number Custom 5 4 3 2 Rev 1.0 VFKTA Date: Monday, March 11, 2013 Sheet 1 19 of 46 5 4 3 2 1 UH1E RPH12 1 2 3 4 8 7 6 5 PCH_GPIO52 PCH_GPIO2 PCH_GPIO51 ODD_DA# 29 29 8.2K_0804_8P4R_5% 29 29 RPH13 C 1 2 3 4 8 7 6 5 PCI_PIRQD# PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# 8.2K_0804_8P4R_5% 10K_0402_5% 1 RH176 2 U3RXDP1 U3RXDP2 U3RXDP1 U3RXDP2 29 29 U3TXDN1 U3TXDN2 29 29 U3TXDP1 U3TXDP2 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 U3RXDN1 U3RXDN2 U3RXDN1 U3RXDN2 U3TXDN1 U3TXDN2 U3TXDP1 U3TXDP2 PCH_GPIO54 8.2K_0402_5% RH305 1 2 PCH_GPIO4 8.2K_0402_5% RH306 1 2 PCH_GPIO5 8.2K_0402_5% RH307 1 2 PCH_GPIO50 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# K40 K38 H38 G38 PCH_GPIO50 PCH_GPIO52 PCH_GPIO54 C46 C44 E40 PCH_GPIO51 D47 E42 F46 PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5 G42 G40 C42 D44 9/28 change DGPU_RST#/ DGPU_PWR_EN to PCH_GPIO50/54, then PCH_GPIO50 8.2k pull high to +3vs 25 ODD_DA# TP21 TP22 TP23 TP24 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 USB3Rn1 USB3Rn2 USB3Rn3 USB3Rn4 USB3Rp1 USB3Rp2 USB3Rp3 USB3Rp4 USB3Tn1 USB3Tn2 USB3Tn3 USB3Tn4 USB3Tp1 USB3Tp2 USB3Tp3 USB3Tp4 PIRQA# PIRQB# PIRQC# PIRQD# RSVD28 RSVD29 INT.PD 20K USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P EHCI 1 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 EHCI 2 INT.PU 20K INT.PU 20K INT.PU 20K PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 USBRBIAS# B T80 PAD 2013/02/28change RH167 pin2 netname from CLK_EC_R to CLK_PCI_EC_R 2013 back to CLK_EC_R as the same for DIS PLT_RST# C6 PLT_RST# 22_0402_5% 1 EMI@ 2 RH167 CLK_EC_R CLK_PCH 0_0402_5% RH166 CLK_PCI_DDR T81 PAD CH115 CLK_PCI_EC CLK_PCILOOP 1 2 22P_0402_50V8J 32 17 5,26,27,32 K10 PCI_PME# H49 H43 J48 K42 H40 @RF@2012/10/19A Change RH166 to short pad 2013/02/06 PVT change back to 0 ohm again PME# INT.PU USBRBIAS 20K PLTRST# INT.PD CLKOUT_PCI0 INT.PD CLKOUT_PCI1 INT.PD CLKOUT_PCI2 INT.PD CLKOUT_PCI3 INT.PD CLKOUT_PCI4 20K 20K 20K 20K 20K OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 AY7 AV7 AU3 BG4 10/24B PLT_RST# Add RH173 100K Pull Down to GND AT10 BC8 PLT_RST# 9/28 Delete PLTRST_VGA# Circuit D 2 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 RH173 100K_0402_5% 1 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 USB B21 M20 AY16 BG46 +3VS RSVD5 RSVD6 RSVD D RSVD1 RSVD2 RSVD3 RSVD4 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 PCI BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 AV5 AV10 NV_ALE AT8 AY5 BA2 AT12 BF3 Note: HM70 only enable USB port 0, 1, 2, 3, 8, 9, 10, 11 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 C33 USBBIAS USB-Right1 Intel Anti-Theft Techonlogy USB-Right2 High=Endabled NV_ALE USB-Left USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N11 USB20_P11 USB20_N8 USB20_P8 USB20_N9 USB20_P9 13 13 26 26 USB20_N11 USB20_P11 13 13 * +1.8VS 1 @ RH164 2 1K_0402_5% Touch Screen BT 10/18B Add USB port 10 for NFC 11/28 Delete NFC Function NFC 1 RH165 C Low=Disable(floating) CardReader NV_ALE Int. Camera 2 22.6_0402_1% Within 500 mils B33 A14 K20 B17 C16 L16 A16 D14 C14 29 29 29 29 27 27 28 28 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB_OC#0 USB_CHG_OC# USB_OC#2 SLP_CHG_CB1 SLP_CHG_CB0 USB_OC#5_7 B USB-Right 17,29,32 USB_OC#0 USB_CHG_OC# 29,32 USB-Right 27,32 USB-Left USB_OC#2 SLP_CHG_CB1 17,29 SLP_CHG_CB0 17,29 Rear Front OC#1 PH @ page 26 CB0 PH @ page 27 +3VALW_PCH RPH11 21 PCH_GPIO28 PANTHER-POINT_FCBGA989 HM76R3@ PCH_GPIO28 USB_CHG_OC# USB_OC#2 USB_OC#5_7 1 2 3 4 8 7 6 5 10K_0804_8P4R_5% 11/30 Move PLT_RST# ESD capacitor (CH104) to EC side (CB13) and mount 0.1u for ESD request Boot BIOS Strap 180P_0402_50V8J A ESD@ 1 2 CH105 PCH_GPIO51 ODD_DA# 1K_0402_5% 2 @ 1 RH293 PCH_GPIO51 1K_0402_5% 2 @ 1 RH294 PCH_GPIO19 PCH_GPIO19 16 PCH_GPIO19 0 1 0 1 0 0 1 1 10/18 Need confirm PCH_GPIO55, 10/19A remove RH295 Boot BIOS Loaction LPC Reserved PCI SPI * A A16 Swap Override Strap WL_OFF# * Low= A16 swap override Enable High= A16 swap override Disable Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PCH_PCI/USB/NAND Rev 1.0 VFKTA Date: 5 4 3 2 Monday, March 11, 2013 Sheet 1 20 of 46 5 4 3 2 1 UH1F 15,19 T7 A42 H36 1 EC_LID_OUT# 1K_0402_5% 32 EC_SCI# 17,32(PH) EC_SMI# E38 EC_SCI# D C10 +3VS C4 32 2 ODD_DETECT# 200K_0402_5% 1 10K_0402_5% PCH_GPIO17 2 RH180 1 10K_0402_5% PCH_GPIO38 G2 PCH_GPIO16 U2 PCH_GPIO17 D40 T5 E8 PCH_GPIO27 20 PCH_GPIO28 (PH) PCH_GPIO34 PCH_GPIO16 EC_SCI# PCH_GPIO49 25 ODD_DETECT# (PH) V8 18 M5 PCH_GPIO38 N2 M3 269@ V13 SM_DET 9/28 change OPTIMUS_EN# to PCH_GPIO38, 10k pull high to +3vs SM_DET PCH_GPIO49 V3 D6 259@ 2 RH199 @ 1 10K_0402_5% PCH_GPIO27 A44 A46 BIOS setup Speaker Type BOM S&M option Harman/Kardon 269@ A5 A6 1 B3 B47 0 B Non Harman BD1 259@ BD49 BE1 BE49 BF1 BF49 GPIO28 * TACH7 / GPIO71 On-Die PLL Voltage Regulator H: Enable L: Disable B41 CPU_PGA_BGA# 34 ODD_EN# RPH16 for common BIOS on PBA/BGA CPU C41 SPK_DET 31 SPK_DET A40 A20GATE INT.PD 350 PECI SATA4GP / GPIO16 20K SCLOCK / GPIO22 PROCPWRGD THRMTRIP# INT.PH 20K GPIO24 INIT3_3V# INT.PD 20K DF_TVS TS_VSS1 STP_PCI# / GPIO34 TS_VSS2 GPIO35 SATA2GP / GPIO36 SATA3GP / GPIO37 8 7 6 5 INT.PD 20K TS_VSS3 INT.PD 20K TS_VSS4 SLOAD / GPIO38 NC_1 P4 D 10K_0804_8P4R_5% 2 CPU_PGA_BGA# RH181 20K INT.PH TACH0 / GPIO17 1 2 3 4 ODD_EN# GATEA20 KB_RST# 11/28 Change SPK_DET0 to SPK_DET, delete SPK_DET1 GATEA20 GATEA20 32 KB_RST# 32 1 10K_0402_5% AU16 P5 KB_RST# AY11 H_PW RGOOD AY10 PCH_THRMTRIP# 1 RH191 H_PW RGOOD 5 2 390_0402_5% Non-Harman detection H_THERMTRIP#5 T14 AY1 This signal has weak internal pull-up, can't be pulled low SPK_DET (GPIO70) NV_CLE AH8 AK11 0 ONKYO 1 Non-Brand AH10 AK10 P37 C SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48 VSS_NCTF_15 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16 GPIO57 VSS_NCTF_17 VSS_NCTF_18 A4 Follow Compal ORB and Intel Check list 460603 V1.5 A45 SM_DET (GPIO48) GPIO15 INT.PD 20K (PH) 10K_0804_8P4R_5% SM_DET TACH6 / GPIO70 INT.PH 20K ODD_EN# LAN_PHY_PWR_CTRL / GPIO12 GPIO28 INT.PH ODD_DETECT# PCH_GPIO37 C 1 10K_0402_5% TACH5 / GPIO69 INT.PH 20K C40 INT.PH 20K 20K RPH15 2 RH201 20K GPIO8 GPIO27 INT.PH K4 1 10K_0402_5% TACH3 / GPIO7INT.PH P8 10/24DChange BT_ON# to PCH_GPIO34 2 RH200 20K E16 K1 PCH_GPIO34 +3VS 8 7 6 5 TACH2 / GPIO6INT.PH INT.PH 20K RCIN# 9/28 change VGA_PWROK to PCH_GPIO17, 10k pull high to +3vs 1 2 3 4 20K CPU/MISC 2 RH179 EC_LID_OUT# TACH1 / GPIO1INT.PH GPIO 1 RH178 EC_LID_OUT# TACH4 / GPIO68 VSS_NCTF_1 VSS_NCTF_19 VSS_NCTF_2 VSS_NCTF_20 VSS_NCTF_3 VSS_NCTF_21 NCTF 2 RH204 +3VS INT.PH 20K BMBUSY# / GPIO0 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_6 VSS_NCTF_24 VSS_NCTF_7 VSS_NCTF_25 VSS_NCTF_8 VSS_NCTF_26 VSS_NCTF_9 VSS_NCTF_27 VSS_NCTF_10 VSS_NCTF_28 VSS_NCTF_11 VSS_NCTF_29 VSS_NCTF_12 VSS_NCTF_30 VSS_NCTF_13 VSS_NCTF_31 VSS_NCTF_14 VSS_NCTF_32 BG2 BG48 H_THERMTRIP# @ESD@ 1 2 CC21 100P_0402_50V8J BH3 BH47 BJ4 BJ44 BJ45 BJ46 DMI & FDI Termination Voltage BJ5 BJ6 Set to VCC when HIGH NV_CLE C2 Set to VSS when LOW C48 +1.8VS D1 B D49 1 +3VALW _PCH HDMI_HPD E1 RH187 2.2K_0402_5% E49 2 HDMI_HPD F1 NV_CLE F49 2 RH189 1 1K_0402_5% H_SNB_IVB# 5 PANTHER-POINT_FCBGA989 HM76R3@ OPTIMUS_EN# GPIO8 * Integrated Clock Chip Enable (Removed) H: Disable L: Enable OPTIMUS_EN# H L SKU NonOPT Optimus A A Integrated clock enable functionality is achieved by soft-strap The current default is clock enable Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Issued Date Deciphered Date 2015/04/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PCH_CPU/GPIO Size B Date: 5 4 3 2 Document Number Rev 1.0 VFKTA Monday, March 11, 2013 Sheet 1 21 of 46 4 3 UH1G +1.05VS_VCCP JP@ PJ4 1 CH31 CH34 1 10U_0603_6.3V6M 2 2 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K +1.05VS_PCH PAD VCCIO[17] AN26 1 CH46 1 1 CH44 VCCIO[22] AP26 10U_0603_6.3V6M 2 2 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K 2 VCCIO[23] AT24 VCCTX_LVDS[3] VCCIO[24] AM38 +VCCTX_LVDS BH29 1 AP36 AP37 CH38 0.01U_0402_25V7K This pin can be left as NC if On-Die VR is enabled (Default) PAD AP16 VCC3_3[6] VCC3_3[7] V34 VCCVRM[3] 75mA VCCCLKDMI VCCDFTERM VCCDFTERM[1] VCC3_3[3] VCCDFTERM[2] VCCIO[27] AU20 +VCCP_VCCDMI VCCDMI[2] S0 Iccmax Current (A) 1.05 0.001 D V5REF 5 0.001 V5REF_Sus 5 0.001 Vcc3_3 3.3 0.228 VccADAC 3.3 0.063 VccADPLLA 1.05 0.08 VccADPLLB 1.05 0.08 VccCore 1.05 1.7 VccDMI 1.1 0.047 CH42 0.1U_0402_10V7K 2 VCCIO[26] VccAFDIPLL AP17 +1.05VS_PCH Voltage 2 V33 1 VCCDMI[1] VCCVRM[2] BG6 T83 CH39 CH40 22U_0805_6.3V6M +1.5VS AT16 AT20 AB36 PANTHER-POINT_FCBGA989 190mA VCCDFTERM[3] +1.05VS_VCCP RH213 0_0402_5% 1 Rshort@ 2 +VCCP_VCCDMI +1.05VS_VCC_DMI 1 +1.05VS_PCH RH214 0_0402_5% 1 Rshort@ 2 1.05 3.711 1.05 0.903 VccSPI 3.3 0.01 VccDSW 3.3 0.001 VccDFTERM 1.8 0.002 VccRTC 3.3 N/A VccSus3_3 3.3 0.095 C 1 2 CH48 1U_0402_6.3V6K CH49 1U_0402_6.3V6K +1.8VS AG16 AG17 1 AJ16 2 VCCDFTERM[4] VccIO VccASW RH221 0_0402_5% 1 Rshort@ 2 +VCCAFDI_VRM +VCCP_VCCDMI CH50 0.1U_0402_10V7K +VCCAFDI_VRM 0.01U_0402_25V7K +VCCAFDI_VRM VCCIO[25] AN34 2 +1.8VS LH2 2 1 BLM18PG181SN1D_0603 AM37 2 AN33 1 1 Rshort@ 2 RH208 0_0402_5% +VCCA_LVDS Voltage Rail V_PROC_IO AK37 1U_0402_6.3V6K +3VS B VCCTX_LVDS[2] VCCIO[21] AP24 1 VCCTX_LVDS[1] AK36 VCCIO[20] AP23 CH47 VCCALVDS VSSALVDS VCCIO[19] 3709mA AP21 CH45 +3VS 1mA PCH Power Rail Table Refer to PCH EDS R1.0 2 VCCIO[18] AN27 C 1 LH1 2 +VCCA_DAC_R2 1 1_0603_1% BLM18PG181SN1D_0603 1 CH37 10U_0603_6.3V6M 1 +3VS VCCIO[16] AN21 CH43 CH35 0.01U_0402_25V7K 0.1U_0402_10V7K 1 CH36 2 60mA VCCIO[15] AN17 1U_0402_6.3V6K U47 +VCCA_DAC VCCAPLLEXP AN16 +1.05VS_PCH U48 VCCIO[28] BJ22 T82 VSSADAC VCCTX_LVDS[4] AN19 This pin can be left as NC if On-Die VR is enabled (Default) CRT 1 LVDS CH33 VCCADAC HVCMOS 1 +3VS 1mA DMI JUMP_43X79 CH32 D VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] 1 RH309 DFT / SPI 1 2 POWER 1730mA AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 +1.05VS_PCH 1U_0402_6.3V6K VCC CORE 2 1 FDI 2 VCCIO 5 CH51 0.1U_0402_10V7K VccSusHDA 3.3 0.01 VccVRM 1.5 0.167 VccCLKDMI 1.05 0.07 AJ17 +3VALW_PCH 20mA VCCSPI V1 VccSSC 1.05 0.095 VccDIFFCLKN 1.05 0.055 VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.04 10/18B Change VCCSPI from +3VS to +3VALW_PCH 1 2 B CH53 1U_0402_6.3V6K HM76R3@ +3VALW to +3VALW_PCH +3VALW +3VALW_PCH QH2 AO3413_SOT23 CH113 2 0.1U_0402_10V7K 1 47K_0402_5% CH112 2 RH3 0.01U_0402_25V7K CH111 PCH_PWR_EN# PCH_PWR_EN# 0.1U_0402_25V6 23,34 2 G A 1 D 1 S 3 1 2 A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PCH_POWER-1 Rev 1.0 VFKTA Date: 5 4 3 2 Monday, March 11, 2013 Sheet 1 22 of 46 5 4 3 2 1 +5VALW +5VALW_PCH +3VS This pin can be left as NC if On-Die VR is enabled (Default) QH6 VCCIO[29] VCCIO[31] +3VS_VCC_CLKF33 T38 BH23 AL29 +1.05VS_PCH AL24 VCCIO[32] VCCIO[33] VCCSUS3_3[7] VCCAPLLDMI2 119mA VCCSUS3_3[8] VCCIO[14] DCPSUS[3] VCCSUS3_3[9] VCCSUS3_3[10] 1 CH65 AA26 1 AA27 22U_0805_6.3V6M 2 2 22U_0805_6.3V6M AA29 AA31 C CH67 +1.05VS_PCH 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1 CH68 CH69 2 2 AC26 1 AC27 AC29 1U_0402_6.3V6K 2 AC31 LH7 1 2 BLM18PG181SN1D_0603 LH8 1 2 BLM18PG181SN1D_0603 +1.05VS_VCCADPLLA AD29 AD31 +1.05VS_VCCADPLLB W21 CH93 1 CH94 1 CH95 1 1 W23 CH96 1U_0402_6.3V6K W24 1U_0402_6.3V6K 2 2 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M W26 W29 W31 W33 1010mA 1mA VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] V5REF_SUS DCPSUS[4] VCCSUS3_3[1] N16 +VCCRTCEXT 1 1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCCASW[16] Y49 B 1 T24 V23 +3VALW_PCH CH60 0.1U_0402_10V7K 2 Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB 1 V24 P24 2 T26 M26 CH61 0.1U_0402_10V7K +PCH_V5REF_SUS AN24 VCC3_3[4] P34 VCC3_3[2] VCCVRM[4] VCCIO[13] Place CH79 near pin AF17 CH79 1U_0402_6.3V6K +1.05VS_PCH BD47 +1.05VS_VCCADPLLB BF47 +1.05VS_VCCDIFFCLKN AF17 AF33 AF34 AG34 1 2 +1.05VS_VCCDIFFCLKN +1.05VS_PCH VCCADPLLA VCCADPLLB 80mA 80mA VCCAPLLSATA VCCVRM[1] 55mA VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3] VCCIO[2] VCCIO[3] +1.05VS_VCCDIFFCLKN AG33 2 CH84 1U_0402_6.3V6K 1 V16 +VCCSST 1 2 2 VCCSSC VCCIO[4] 95mA 2 T17 V19 CH85 1 N22 P20 CH70 1U_0402_6.3V6K 2 P22 AA16 +3VS W16 T34 1 1 2 CH88 +3VS C CH63 & CH71 are different by Intel CRB. DH4 CH751H-40PT_SOD323-2 CH72 0.1U_0402_10V7K +PCH_V5REF_RUN 1 2 2 CH71 1U_0402_6.3V6K +3VS AJ2 +1.05VS_PCH 1 AF13 CH76 0.1U_0402_10V7K 1 AH13 AH14 CH77 1U_0402_6.3V6K 2 B Place CH77 near pin AF13, AH13, AH14, AF14 AF14 This pin can be left as NC if On-Die VR is enabled (Default) AK1 +VCCAFDI_VRM AF11 +VCCAFDI_VRM +1.05VS_PCH AC16 AC17 1 AD17 CH82 1U_0402_6.3V6K +1.05VS_PCH DCPSUS[1] DCPSUS[2] VCCASW[22] 1 1mA V_PROC_IO +RTCVCC Place CH82 near pin AC16, AC17, AD17 VCCASW[23] VCCASW[21] T21 V21 T19 +3VALW_PCH 0.1U_0402_10V7K 2 0.1U_0402_10V7K A CH90 1 Place CH86, CH87, CH88 near pin BJ8 A22 VCCRTC RTC 2 CH87 +5VS RH237 10_0402_5% +3VS DCPSST CPU BJ8 0.1U_0402_10V7K 1 0.1U_0402_10V7K +3VALW_PCH 0.1U_0402_10V7K +1.05VS_VCCP CH86 4.7U_0603_6.3V6K CH63 2 MISC CH81 1U_0402_6.3V6K HDA RH247 0_0402_5% 1 Rshort@ 2 1 +1.05VS_VCCADPLLA SATA +1.05VS_PCH +PCH_V5REF_SUS 1 2 VCCIO[6] CH751H-40PT_SOD323-2 2 0.1U_0402_10V7K +PCH_V5REF_RUN 2 DCPRTC DH3 N20 VCCASW[18] VCCASW[20] RH232 10_0402_5% +3VALW_PCH 1 2 CH75 0.1U_0402_10V7K VCCASW[19] +3VALW_PCH +1.05VS_PCH AN23 VCCASW[17] VCCIO[12] +VCCAFDI_VRM PCH_PWR_EN# 2 D T23 1 CH66 VCCIO[5] CH78 0.1U_0402_10V7K 22,34 +3VALW_PCH RH328 2 1 47K_0402_5% 1 VCCASW[2] VCCIO[34] PCI/GPIO/LPC AA24 CH64 2 T29 1 +5VALW_PCH VCCASW[1] Clock and Miscellaneous AA21 2 1 CH56 1U_0402_6.3V6K T27 VCC3_3[5] VCCSUS3_3[6] AA19 +1.05VS_PCH P28 2 2 DCPSUSBYP 1 P26 1 V12 CH55 0.1U_0402_10V7K USB 1 VCCIO[30] 3mA VCCDSW3_3 CH59 0.1U_0402_10V7K~D VCCACLK 2 T16 N26 G +3VALW_PCH D AO3413_SOT23 1 3 1 AD49 +1.05VS_PCH 2 POWER UH1J 2 CH74 1U_0402_6.3V6K D 2 1 CH73 10U_0603_6.3V6M S 2 2 +3VS_VCC_CLKF33 1 1 CH80 0.1U_0402_10V7K~D LH5 1 2 10UH_LB2012T100MR_20% 10mA VCCSUSHDA P32 1 PANTHER-POINT_FCBGA989 HM76R3@ 2 A CH92 0.1U_0402_10V7K 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PCH_POWER-2 Rev 1.0 VFKTA Date: 5 4 3 2 Sheet Monday, March 11, 2013 1 23 of 46 5 4 3 2 1 UH1I AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 UH1H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 D C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 PANTHER-POINT_FCBGA989 HM76R3@ VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 D C B PANTHER-POINT_FCBGA989 HM76R3@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Issued Date Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PCH_GND Rev 1.0 VFKTA Date: 5 4 3 2 Monday, March 11, 2013 Sheet 1 24 of 46 A B C SATA HDD Conn. GND A+ AGND BB+ GND 1 23 24 GND GND V33 V33 V33 GND GND GND V5 V5 V5 GND DAS/DSS GND V12 V12 V12 1 2 3 4 5 6 7 SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 C369 1 C367 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C368 1 C370 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS E SATA ODD Conn Close to JHDD JHDD D GND A+ AGND BB+ GND 16 SATA_PRX_C_DTX_N0 16 SATA_PRX_C_DTX_P0 10/24Dchange JHDD pin 10 from +3vs to NC 10/19A Add +3VS on JHDD 15 14 +5VS DP +5V +5V MD GND GND GND GND Power Consumption Close to JODD JODD 16 SATA_PTX_DRX_P0 16 SATA_PTX_DRX_N0 1 2 3 4 5 6 7 SATA_PTX_C_DRX_P2 SATA_PTX_C_DRX_N2 C376 1 C377 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 C378 1 C375 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K 8 9 10 11 12 13 ODD_DETECT# 21 ODD_DA# 20 16 SATA_PRX_C_DTX_N2 16 SATA_PRX_C_DTX_P2 1.2A 1 SUYIN_127043FR022G196ZR Conn@ 2 SANTA_202401-1 Conn@ Place closely JHDD SATA CONN. 1 1 C356 10U_0805_10V4Z C357 0.1U_0402_10V7K 2 1 1800 mA 1100 mA 950 mA 1300 mA 20mA 1 +5VS_ODD +5VS_ODD +5VS Peak Read (CD) Read (DVD) Write Standby 16 SATA_PTX_DRX_P2 16 SATA_PTX_DRX_N2 C358 0.1U_0402_10V7K 2 Place components closely ODD CONN. C355 10U_0805_10V4Z 1 2 1 C360 0.1U_0402_10V7K 2 C380 0.1U_0402_10V7K 2 G-Sensor 2 2 +5VS +3VS_HDP UG1 2 12 +3VS_HDP CG12 1U_0402_6.3V6K GSENSOR@ 1 2 UG3 1 2 3 1 CG13 1U_0402_6.3V6K GSENSOR@ 2 GSENSOR@ VIN VOUT 5 4 6 8 SELF_TEST GSENSOR@ Vdd1 Vdd2 Voutx Vouty Voutz ST PD FS NC1 NC2 NC3 NC4 NC5 GND SHDN# BP 4 9 +3VS_HDP Rev GND1 GND2 G9191-330T1U_SOT23-5 SA000022I00 3 5 7 VOUTX VOUTY VOUTZ CG1 CG2 CG3 1 1 1 2 GSENSOR@ 2 GSENSOR@ 2 GSENSOR@ 0.033U_0402_16V7K 0.033U_0402_16V7K 0.033U_0402_16V7K 10 11 14 15 16 1 13 TSH352TR LGA 16P SA00004GB00 UG2 17,32 1 EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 11 HDPACT 32 3 2 3 SELF_TEST 2 +3VS_HDP_R 3 GXOUT 4 12 RG9 47K_0402_5% GSENSOR@ RPG1 1 2 3 4 8 7 6 5 +3VS_HDP_R GXOUT GXIN +3VS_HDP_M 5 6 GXIN 4.7K_8P4R_5% GSENSOR@ 32 HDPINT HDPINT RG7 +3VS_HDP 7 +3VS_HDP_M 8 2 1 1K_0402_5% GSENSOR@ 1 CG7 0.1U_0402_10V7K GSENSOR@ 2 9 RESET# P1_4/TXD0 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT VSS/AVSS P1_2/KI2#/AN10/CMP0_2 SA00003A600 XIN/P4_6 P4_2/VREF VCC/AVCC P1_1/KI1#/AN9/CMP0_1 MODE P1_0/KI0#/AN8/CMP0_0 P4_5/INT0#/RXD1 10 1 P1_7/CNTR00/INT10# CG8 GSENSOR@ R5F211B4D34SP 0.1U_0402_10V7K 2 P3_3/TCIN/INT3#/SSI00/CMP1_0 P3_4/SCS#/SDA/CMP1_1 13 1 +3VS_HDP 14 15 HDPLOCK VOUTZ 32 RG10 47K_0402_5% 2 1 GSENSOR@ 16 +3VS_HDP 17 VOUTX 18 VOUTY 1 2 CG6 0.1U_0402_10V7K GSENSOR@ 19 20 EC_SMB_DA2 17,32 GSENSOR@ 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D HDD/ODD/G-Sensor Document Number Rev 1.0 VFKTA Sheet Monday, March 11, 2013 E 25 of 46 A B C D E Slot 1 Half PCIe Mini Card-WLAN WLAN&BT Combo module circuits 40 mils +3V_WLAN 0.1U_0402_10V7K 1 1 CM1 CM2 BT on module Enable Disable H L 1 CM3 2 0.1U_0402_10V7K BT on module BT_ON 2 2 4.7U_0603_6.3V6K 1 1 10/24D Delete QM1, change BT_ON design 10/24 Remove +1.5VS on WLAN pin6/28/48, delete CM7, CM8 Delete RM22 (EC will programming H/L) From 32 EC Reserve +1.5 power rail & cap. to supoort unknown keypart. 17 PCIE_PTX_C_WLANRX_N2 17 PCIE_PTX_C_WLANRX_P2 To PCH 2 +3V_WLAN 32 32 E51_TXD E51_RXD E51_TXD E51_RXD 53 Debug card using GND1 GND2 WL_OFF# PLT_RST# 32 5,20,27,32 To PCH +3VALW PM_SMBCLK PM_SMBDATA 11,12,17,33 11,12,17,33 USB20_N9 USB20_P9 WiMax/ 20 BT LED_WIMAX# +3VALW 10/24Dchange RM31 to 10K, Add RM2 20 WOWL@ RM31 10K_0402_5% 1 RM6 33 LED_WIMAX# 2 2 WOWL@ CM9 0.1U_0402_10V7K Vgs=-4.5V,Id=3A,Rds<97mohm 1 2 +3VS 100K_0402_5% To 32 EC 1 WOWL_EN# 54 RM2 100K_0402_5% LOTES_AAA-PCI-049-P06-A 3 To PCH WLAN/ WiFi +3VALW TO +3V_WLAN for WOWL To EC WL_OFF# PLT_RST# 47K_0402_5% RM30 2 2 WOWL@ 1 WOWL@ CM10 0.01U_0402_25V7K AO3413_SOT23 QM2 Need short PJ3 if system don't support WOWL +3V_WLAN WOWL@ RM1 1 2 0_0603_5% NOWOWL@ 2 Conn@ 2 1 17 PCIE_PRX_WLANTX_N2 17 PCIE_PRX_WLANTX_P2 1 CLK_WLAN# CLK_WLAN To PCH 1 RM24 2 BT_CTRL_R @ 0_0402_5% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 17 17 BT_ON 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 1 CLKREQ_WLAN# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 G 17 +3V_WLAN JWLAN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 D WLAN_WAKE# For isolate BT_ON and Compal Debug Card. S 10/24Dchange RM24 pin1 netname from BT_CTRL to BT_ON To EC (Need pull-up +3VL) 32 1 RM27 2 E51_RXD 1K_0402_5% BT_ON BT_ON +3VS 10/24 Change PJ3 to RM1 and add BOM structure "NOWOWL@" 02/20 1 2 Delete CCL2, RCL5 CCL1 GCLK@ 10/24 +3VALW 0.1U_0402_10V7K +1.05VS_VCCP 0.1U_0402_10V7K 3 0.1U_0402_10V7K +3VL 1 2 CCL3 GCLK@ 1 2 CCL8 GCLK@ 3 10/24 Change CCL2 to @ 10/19A GCLK@ UCL1 2 15 +3VALW +3VL 8 3 +1.05VS_VCCP CLK_X1 CLK_X2 1 16 4 7 13 17 CCL14 22U_0805_6.3V6M GCLK@ VDD +V3.3A VBAT NC VDDIO_25M_A VDDIO_25M_B XTAL_IN XTAL_OUT VSS VSS VSS Thermal Pad 32K NC 25M_B 25M_A VDD_RTC_OUT SLG3NB244VTR_TQFN16_2X3 GCLK@ 25MHZ 12PF X3G025000DK1H-X YCL1 CLK_X1 1 1 4 1 2 CCL9 18P_0402_50V8J GCLK@ 3 GND GND 2 4 3 PN: SA000057I00 1 RCL4 120_0603_5% 2 1 GCLK@ 2 10 11 9 12 +RTC PCH_RTCX1_R 16 02/20 Delete RCL2 LAN_X1_R_R, LAN_X1_R PCH_X1_R_R 5 6 Change RCL2 to short pad for safety request PCH_X1_R_R 1 Rshort@ 2 RCL1 0_0402_5% PCH_X1_R 17 14 2 1 CCL13 2.2U_0402_6.3V6M GCLK@ CLK_X2 4 1 2 CCL12 18P_0402_50V8J GCLK@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D WLAN/GCLK Document Number Rev 1.0 VFKTA Monday, March 11, 2013 Sheet E 26 of 46 A B C D E Left USB 2.0 x 1 +5VALW W=80mils 2.0A LR1 EMI@ 20 1 20 2 USB20_P2 USB20_P2 3 USB20_N2 USB20_N2 2 1 3 4 1 USB20_P2_L 32 4 USB_EN#2 USB_EN#2 2 3 4 1 IN IN EN/ENB GND USB20_N2_L OUT OUT OUT OCB For EMI +USB_VCCC UR1 6 7 8 5 2 CR38 @EMI@ 1 1000P_0402_50V7K USB_OC#2 +3V_LAN PLT_RST# 5,20,26,32 18 EC_SWI# 17 17 CLK_LAN# CLK_LAN 20,32 02/20 G547I2P81U_MSOP8 SA00004KB00 SA00003TV00 WCM-2012-900T_0805 JLAN 1 2 1 3 2 4 3 5 4 6 5 7 6 8 7 9 8 10 9 11 10 12 11 13 12 14 13 15 14 16 15 17 16 18 17 19 18 20 19 20 LANCLK_REQ# ISOLATE# Delete net: LAN_X1_R PCIE_PTX_C_LANRX_N1 PCIE_PTX_C_LANRX_P1 PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 2013/02/06 change UR1 UR4 from SA00004KB00 to SA00003TV00 DVT 2nd source X1 code issue 17 17 17 17 USB20_P2_L USB20_N2_L +USB_VCCC 1 8 10 12 14 16 18 20 21 22 23 24 1 1 10K_0402_5% LANCLK_REQ# 10/16 Swap JLAN pin define due to FFC fold 2 RL24 2 LAN_EN CLKREQ_LAN# 1 3 WOL_EN# 1 Rshort@ 2 WOL_EN# RL433 0_0402_5% 32 2 LANCLK_REQ# RL7 15K_0402_5% S D CLKREQ_LAN# 1K_0402_5% RL6 @ ISOLATE# 2 17 G LAN_EN 2 17 6 ACES_50559-02001-001 Conn@ +3VS +3VS 4 G1 G2 G3 G4 W=80mils For LAN function 2 Sx Enable Wake up QL53 2N7002KW_SOT323-3 WOL_EN# Sx Disable Wake up LOW HIGH S0 HIGH 10/24 Add note for WOL_EN# S0 status JP@ 2 +3VALW_PCH PJ29 2 1 1 +3V_LAN JUMP_43X39 +3V_LAN rising time (10%~90%) need > 1ms and <100ms. 3 3 LAN WOL LAN_EN ISOLATEB S0 Sx S0 Sx ---------------------------------------------0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0* * S3: after SUSP# assert low over 100ms S4/S5: after SYSON assert low over 100ms 4 4 Compal Secret Data Security Classification Issued Date 2012/04/19 2015/04/19 Deciphered Date Title Compal Electronics, Inc. LUSB20/LAN conn. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A B C D Monday, March 11, 2013 Sheet E 27 of 46 4 3 2 1 For EMI request (Place close to chip) LW1 2 1 SD_DATA0_R BLM15BD121SN1D_0402 EMI@ LW2 2 1 SD_DATA1_R BLM15BD121SN1D_0402 EMI@ LW3 2 1 SD_DATA2_R BLM15BD121SN1D_0402 EMI@ LW4 2 1 SD_DATA3_R BLM15BD121SN1D_0402 EMI@ SD_DATA0 SD_DATA1 D SD_DATA2 1 SD_DATA3 UW1 20 20 2 3 RSTZ MS_INS SD_D2/MS_D5/SB13 SD_D3/MS_D4/SB12 SD CMD/SD_CMD SD CLK/SD_CLK SD_CDZ SD_D0/MS_D6/SB9 SD_D1/MS_D7/SB8 MS BS/MS_BS SD_WP/MS_D1/SB5 SD_D4/MS_D0/SB4 SD_D5/MS_D2/SB3 SD_D6/MS_D3/SB1 SD_D7/MS_CLK/SB0 DM DP 30mils +3VS 1 Rshort@ 2 RW1 0_0402_5% +3VS_CR +VCC_3IN1 1 CW1 2.2U_0402_6.3V6M 2 please close the pin19 of UW1 30mils 2 19 23 20 +3VS_CR +VDD18 4 18 1 CW5 0.1U_0402_16V4Z 1 C +3VS_CR +3VS_CR 12mils +3VS_CR +3VS_CR 1 24 DVDD PMOS 30mils CW2 0.1U_0402_16V4Z 25 DVDD DVDD GPIO0 AVDD VDD18 5 17 16 15 14 21 13 12 11 10 9 8 7 6 SD_DATA2 SD_DATA3 SDCMD SDCLK SDCD# SD_DATA0 SD_DATA1 2 SDCMD_R 0_0402_5% 2 EMI@ 2 EMI@ 2 EMI@ 2 EMI@ 2 LW5 2 1 BLM15BD121SN1D_0402 EMI@ @EMI@ SDCLK_R 2 CW14 4.7P_0402_50V8J 1 SDWP 1 CW9 EMI@ 10P_0402_50V8J 1 1 1 1 Thermal pad GL834L-OGY01_QFN24_4X4 2 EMI@ 1 LW6 CW10 10P_0402_50V8J 22 USB20_N3 USB20_P3 CW11 10P_0402_50V8J 2 CW12 10P_0402_50V8J CW8 0.1U_0402_16V4Z D CW13 10P_0402_50V8J 5 NC (default) 10K pull down GPIO0 Power saving mode Normal mode C please close the pin4 of UW1 De-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket +3VS_CR +3VS_CR 30mils CW3 2.2U_0402_6.3V6M 1 2 1 CW4 0.1U_0402_16V4Z 2 < 2 in 1 Card Reader > Close to connector Conn@ JCARD 5 3 6 7 4 VDD CMD CLK VSS VSS DAT0 DAT1 DAT2 CD/DAT3 B 12 13 GND_SW GND_SW WP_SW CD_SW 1 10 11 SDWP# SDCD 1 CW7 2.2U_0402_6.3V6M CW6 0.1U_0402_16V4Z 2 SD_DATA0_R SD_DATA1_R SD_DATA2_R SD_DATA3_R 30mil +VCC_3IN1 SDCMD_R SDCLK_R 8 9 1 2 Close to IC 2 B T-SOL_156-2000302604 "Normal Close" type connector Close Open Close SDCD# SDWP RW3 100K_0402_5% RW4 100K_0402_5% Open SDCD 2 6 QW1A Card Insertion D 2 G QW1B SDWP# D 5 G 2N7002KDWH_SOT363-6 1 S 3 Protect Enable Close 1 Protect disable Close +3VS_CR 2 Card Uninsertion +3VS_CR WP_SW 1 CD_SW For normal close type connector invert circuit 2N7002KDWH_SOT363-6 4 S A A Compal Secret Data Security Classification 2012/10/26 Issued Date 2013/10/26 Deciphered Date Title Compal Electronics, Inc. USB-CardReader GL834L THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 1.0 VFKTA Monday, March 11, 2013 Sheet 1 28 of 46 5 4 3 2 1 USB Sleep & Charge State table for MAX14641 CB0 CB1 D 12/05 S&C IC Pin1 was connected to the EC(GPIO49) Pin82. STATUS Mode 0 AM2 2A auto-detection charger mode for Apple device. Resistor dividers are connected to DP/DM. Including DCP 0 1 AP1 Forced 1A charger mode for Apple devices. Resistor dividers are connected to DP/DM. 1 0 PM USB pass-through mode.DP/DM are connected to TDP/TDM 1 1 CM USB pass-through mode with CDP emulation. Auto connects DP/DM to TDP/TDM depending on CDP detection status. 0 UR2 32 CHG_PWR_GATE# USB20_N1_S USB20_P1_S 14641@ RR2 17,20 CHG_CB1 0_0402_5% SLP_CHG_CB1 Right rear USB3.0 Conn. 14641@ 14641@ 8 CHG_CB0 RR1 0_0402_5% CEN CB0 7 DM TDM 6 DP TDP 5 +5VALW CB1 VCC 1 PGND CR9 0.1U_0402_10V7K MAX14641ETA-TGH7_TDFN8 D 1 2 3 4 9 17,20 20 20 2 UR2 Right front USB3.0 Conn. (Support S&C function) SLP_CHG_CB0 USB20_N1 USB20_P1 Address 0x35 +3VALW +3VALW 1 3 4 1 USB20_N0_R 4 USB20_P0_R WCM-2012-900T_0805 USB20_N1_S 2 USB20_P1_S 3 LR7 EMI@ 2 1 3 4 1 USB20_N1_R 4 USB20_P1_R WCM-2012-900T_0805 C QR1A 6 32,36,37 EC_SMB_CK1 LR2 U3RXDP1 20 U3RXDN1 EMI@ LR3 1 2 U3RXDP1_L 4 3 U3RXDN1_L 20 20 LR5 20 1 2U3TXDP1_C CR14 0.1U_0402_10V7K U3TXDP1 1 2U3TXDN1_C CR15 0.1U_0402_10V7K U3TXDN1 1 2 U3RXDP2_L 4 3 U3RXDN2_L LR4 U3TXDP1_C_L 3 02/22 SAWP CR16 pin1 U3TXDN2 to CR17 pin1 U3TXDP2 U3TXDN1_C_L 1 2U3TXDP2_C CR16 0.1U_0402_10V7K 1 2 U3TXDP2_C_L 20 U3TXDN2 1 2U3TXDN2_C CR17 0.1U_0402_10V7K 4 3 U3TXDN2_C_L +USB_VCCB W=80mils USB_EN#0 USB_OC#0 CR12 SA00004KB00 SA00003TV00 1 1000P_0402_50V7K 1 CR13 17,20,32 2 CR39 @EMI@ +USB_VCCA W=100mils 2.5A W=100mils +USB_VCCA UR3 02/20 Delete CR7, CR8 32 2 3 4 1 USB_CHG_EN# 2 IN IN EN/ENB GND 0.1U_0402_10V7K OUT OUT OUT OCB 6 7 8 5 1 1 6 7 8 5 OUT OUT OUT OCB G547I2P81U_MSOP8 D3 +5VALW 0.1U_0402_10V7K 2 32 IN IN EN/ENB GND QR1B 2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue DR4 @ESD@ 1000P_0402_50V7K 1 CR11 2 B CR40 @EMI@ 2 47U_0805_6.3V6M @ESD@ U3TXDP1_C_L 1 9 U3TXDP1_C_L U3TXDP2_C_L 1 9 U3TXDP2_C_L U3TXDN1_C_L 2 8 U3TXDN1_C_L U3TXDN2_C_L 2 8 U3TXDN2_C_L U3RXDP1_L 4 7 U3RXDP1_L U3RXDP2_L 4 7 U3RXDP2_L U3RXDN1_L 5 6 U3RXDN1_L U3RXDN2_L 5 6 U3RXDN2_L 3 1 USB_CHG_OC# 20,32 SY6288DCAC_MSOP8 SA00006DN00 47U_0805_6.3V6M CR10 2 +USB_VCCB UR4 2 3 4 1 3 JUSBF TVWDF1004AD0_DFN9 JUSBR U3TXDP1_C_L U3TXDN1_C_L U3RXDP1_L U3RXDN1_L USB20_P0_R USB20_N0_R +USB_VCCB 9 8 7 6 5 4 3 2 1 StdA-SSTX+ StdA-SSTXGND-DRAIN StdA-SSRX+ StdA-SSRXGND D+ DVBUS Conn@ 13 12 11 10 TVWDF1004AD0_DFN9 U3TXDP2_C_L U3TXDN2_C_L GND GND GND GND U3RXDP2_L U3RXDN2_L USB20_P1_R USB20_N1_R +USB_VCCA 9 8 7 6 5 4 3 2 1 StdA-SSTX+ StdA-SSTXGND-DRAIN StdA-SSRX+ StdA-SSRXGND D+ DVBUS Conn@ 13 12 11 10 GND GND GND GND LOTES_AUSB0015-P001A LOTES_AUSB0015-P001A A A 10/22A ESD request Delete DR1, DR2 10/22A ESD request Delete DR1, DR2 Compal Secret Data Security Classification Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title Compal Electronics, Inc. RUSB30/S&C THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 C CHG_CB0 11/28 Change CR10, CR12 from 47u 1206 to 0805 size (SE00000PL00) W=80mils 2.0A +5VALW CHG_CB1 4 EMI@ U3TXDP2 SW_WCM2012F2S_4P 2013/02/06 change UR1 UR4 from SA00004KB00 to SA00003TV00 DVT 2nd source X1 code issue RR4 4.7K_0402_5% 14640@ 12/04 Update S&C to 14640/14641 co-layout circuit(add RR1~RR4, QR1, modify net-name) 20 SW_WCM2012F2S_4P B 2N7002KDWH_SOT363-6 14640@ SW_WCM2012F2S_4P EMI@ 2 4 U3RXDN2 32,36,37 3 EC_SMB_DA1 EMI@ 1 2013/02/06 change LR2,LR3,LR4,LR5 from SM070001U00 to SM070001R00 DVT 2nd source for X1 code issue SW_WCM2012F2S_4P 20 U3RXDP2 RR3 4.7K_0402_5% 14640@ 1 2N7002KDWH_SOT363-6 14640@ 20 2 2 1 3 1 2 2 20 20 5 USB20_N0 USB20_P0 EMI@ 2 MAX14640ETA+TGH7 14640@ LR6 4 3 2 Rev 1.0 VFKTA Monday, March 11, 2013 Sheet 1 29 of 46 A B C D 35mA for 3.3V level 20 mil E 40 mil UA1 MIC1_LINE1_R_R MIC1_LINE1_R_L 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 22 21 MIC1_LINE1_R_C_R MIC1_LINE1_R_C_L CA58 CA57 MIC1_R MIC1_L DVDD DVDD_IO 17 16 MIC2_R MIC2_L 31 30 MIC1_VREFO_L 29 MIC1_VREFO_R 32 MIC2_VREFO 15 14 LINE2_R LINE2_L +MIC1_VREFO_L +MIC1_VREFO_R EC_MUTE_INT 1 AVDD1 AVDD2 PVDD1 PVDD2 SPK_OUT_R+ SPK_OUT_R- 1 9 +DVDD +DVDD 25 38 +AVDD +AVDD 39 46 +PVDD +PVDD 45 44 SPKR+ SPKR- 20 @ESD@ 0.01U_0402_25V7K 2 CA65 1 16 16 MONO_OUT 12 SYNC 11 close to pin19 2 1 AC_JDREF 1 2 LDO_CAP RA30 20K_0402_1% AC_VREF CA60 10U_0603_6.3V6M 1 2 CPVEE CBN CA54 2.2U_0402_6.3V6M 1 1 2 CBP CA55 CA53 2.2U_0402_6.3V6M 0.1U_0402_10V7K 2 13 INT_MIC_DATA INT_MIC_CLK_R 1 2 2 @ RA34 1 20K_0402_1% 32 SDATA_OUT SDATA_IN 19 28 27 34 35 36 JDREF LDO_CAP VREF CPVEE CBN CBP 2 3 LINE1_L LINE1_R NC SENSE_A SENSE_B 47 4 EC_MUTE# BCLK GPIO0/DMIC_DATA GPIO1/DMIC_CLK 13 18 SENSE_A SENSE_B 40 41 EAPD PD# AVSS1 AVSS2 PVSS1 PVSS2 DVSS Thermal Pad 2 CA45 0.1U_0402_16V4Z 2 CA42 CA3 2.2U_0402_6.3V6M 33 32 HPOUT_R HPOUT_L 2 RA50 4.7K_0402_5% 1 For EMI reserve 75_0402_1% RA19 RA20 75_0402_1% AZ_SDIN0_HD_R 6 AZ_BITCLK_HD 23 24 48 LINE1_R_C_L LINE1_R_C_R HP_R INT_MIC_CLK EC_MUTE# Hight LOW CAM_EMI@ 1 2 10U_0603_6.3V6M 02/20 Change RA22, RA18, RA24 to short pad 60 mil CA33 0.1U_0402_10V7K CA32 0.1U_0402_10V7K AZ_SDOUT_HD 16 16 AZ_SDIN0_HD 2 1 RA23 33_0402_5% 1 1 Rshort@ 2 RA24 0_0603_5% +PVDD 1 2 2 CA35 1 10U_0603_6.3V6M +5VALW close to pin46 For P/N and footprint Please place them to ISPD page 1 2 AZ_BITCLK_HD 16 1 269@ 2 UA1 MIC1_LINE1_R_L 0.1U_0402_10V6K 269@ 1 2 MIC1_LINE1_R_R CA10 0.1U_0402_10V6K CA9 26 37 42 43 7 ALC269Q-VB6-CG 269@ For S&M Sleep and Music AGND 259@ No 269@ Yes 49 1 Rshort@ 2 RA44 0_0603_5% 1 Rshort@ 2 RA43 0_0603_5% 1 Rshort@ 2 RA39 0_0603_5% 1 2 @EMI@ RA38 0_0603_5% 1 2 @EMI@ RA31 0_0603_5% For EMI reserve close to codec EMI@ CA51 1 1 2 EMI@ RA41 10P_0402_50V8J 2 AZ_BITCLK_HD 10_0402_5% Internal AMP RA4213 INT_MIC_CLK_R MBK1005301YZF +5VALW CA50 31 31 HP_L DGND To solve noise issue 2 1 Rshort@ 2 RA18 0_0603_5% 0.1U_0402_10V7K 1 2 CA37 close to pin39 5 8 ALC259-VC2-CG_MQFN48_6X6 259@ 2 269@ CA47 11/28 mount CA32 (modify BOM structure) 2 11/28 Change RA50 to 269@ 0.1U_0402_10V7K 1 10U_0603_6.3V6M 1 close to pin9 SPKL+ SPKL- RESET# 10 mil close to pin 28 CA25 2.2U_0402_6.3V6M HPOUT_R HPOUT_L 2 close to pin1 close to pin 38 close to pin 25 1 PCBEEP 10 AZ_SYNC_HD AZ_RST_HD# SPK_OUT_L+ SPK_OUT_L- +AVDD 1 CA4 0.1U_0402_16V4Z 10/19A Add CA65 for ESD reserved MONO_IN 1 Rshort@ 2 +3VS RA22 0_0402_5% +DVDD 1 650mA for 5V level Enable Disable 2 11/30 Reserve RA31,RA38 for EMI request 2013/02/06 change RA42 from SM01000CY00 to SM01000A900 PVT 2nd for X1 code issue MIC/LINE IN SPK Beep sound 2W 4ohm =40mil 1W 8ohm =20mil 1 Rshort@ 2 RA8 0_0603_5% SPKL- 3 CA31 1000P_0402_50V7K @EMI@ 2 1 1 2 CA27 SENSE A Codec Signals 1 2 2 31 2 31 1 +MIC1_VREFO_L RA46 2.2K_0402_5% 3 CA30 1000P_0402_50V7K @EMI@ MIC_SENSE Rshort@ SPKR+ 1 RA9 2 0_0603_5% SPKR- 1 Rshort@ 2 RA10 0_0603_5% CA34 1000P_0402_50V7K @EMI@ Impedance SPK_L2 1 31 MIC1_L 100P_0402_50V8J For better sound by customer request Sense Pin 2 1 1K_0402_5% RA45 MIC1_LINE1_R_L MONO_IN 0.1U_0402_10V7K RA49 4.7K_0402_5% 31 6 2 47K_0402_5% SPK_L1 1 2 PORT-I (PIN 32, 33) Headphone out 20K PORT-B (PIN 21, 22) Ext. MIC 10K PORT-C (PIN 23, 24) 31 SPK_R2 31 +3VL RA35 RA29 269@ 100K_0402_5% 2 RA37 0_0402_5% 100K_0402_5% 259@ 1 32 CA36 1000P_0402_50V7K 2 @EMI@ SM_SENSE# EC QA1B 2N7002KDWH_SOT363-6 269@ 2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue Function 39.2K SPK_R1 QA1A 2N7002KDWH_SOT363-6 269@ 10/24DChange RA35 to always mount 1 PCH_SPKR CA70 1 2 1 +MIC1_VREFO_R RA48 2.2K_0402_5% MIC1_R 3 16 1 Rshort@ 2 RA7 0_0603_5% SPKL+ 1 RA52 2 RA47 1K_0402_5% 2 1 MIC1_LINE1_R_R 5 JACK_SENSE 31 4 PCI Beep For EMI reserve close to codec place close to chip MIC_SENSE 2 RA32 1 20K_0402_1% SENSE_A 4 4 5.1K (PIN 48) 31 SENSE B 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-H (PIN 20) 2012/04/19 RA33 39.2K_0402_1% Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date NBA_PLUG 2015/04/19 Deciphered Date Title HDA-ALC259-VC/269-VB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev Monday, March 11, 2013 Sheet E 30 of 46 SPK Conn. For common design, pull-high resistor should be placed at connector side. +3VS 2 10/19A Follow the latest connector list to change SPK footprint, The ME drawing with new JSPK will be updated 10/20 RA95 10K_0402_5% BIOS setup Speaker Type BOM S&M option Harman/Kardon 269@ Non Harman 259@ JSPK 1 8 7 1 GND GND 6 5 4 3 2 1 SPK_R1 SPK_R2 SPK_L1 SPK_L2 SPK_DET 6 5 4 3 2 1 0 ACES_50228-0067N-001 Conn@ Non-Harman detection 11/28 Change SPK connector to 6 pin, change SPK_DET0 to SPK_DET, delete SPK_DET1 and RA96 10/22A ESD request Delete DA5, DA8 covered by ME design SPK_DET (GPIO70) 0 ONKYO 1 Non-Brand HeadPhone/LINE Out JACK JLINE Conn@ 2 0_0402_5% 2 0_0402_5% HP_R_L 3 100P_0402_50V8J 1 4 NBA_PLUG 5 1 2 TYCO_2041280-1_3.6D 2 @EMI@ 1 YSDA0502C_SOT23-3 @ESD@ 10/24 30 100P_0402_50V8J DA6 CA12 HP_R_R CA11 1Rshort@ RA54 1Rshort@ RA53 @EMI@ HP_R 6 1 2 2 HP_L 3 Change RA53~56 to short pad..........again......~ MIC/LINE IN JACK JEXMIC Conn@ 3 CA13 30 1 1 2 100P_0402_50V8J @EMI@ YSDA0502C_SOT23-3 @ESD@ 2 4 JACK_SENSE +3VL 100P_0402_50V8J @EMI@ DA7 CA14 MIC1_R_R 2 MIC1_R 6 1 2 MIC1_R_L 3 MIC1_L 1 Rshort@ 2 RA56 0_0402_5% 1 Rshort@ 2 RA55 0_0402_5% 1 30 30 30 30 21 SM_DET (GPIO48) RA40 4.7K_0402_5% 269@ 5 TYCO_2041280-1_3.6D RA36 0_0402_5% 259@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title AUDIO CONN Size Date: Document Number Monday, March 11, 2013 Rev 1.0 Sheet 31 of 46 B C +3VL 0.1U_0402_10V7K 1 CB2 02/20 Delete CB4, CB5 @RF@ 21 21 16 16 16 16 16 16 2 1 1 CB11 10P_0402_50V8J @RF@ 2 20 CLK_PCI_EC 5,20,26,27 PLT_RST# +3VL RB2 47K_0402_5% 1 2 21 26 EC_RST# 11/30 Move PLT_RST# ESD capacitor (CH104) to EC side (CB13) and mount 0.1u for ESD request ESD@ 33 KSI[0..7] 33 KSO[0..15] KSI[0..7] KSO[0..15] 2 29 CHG_PWR_GATE# RPB1 +3VL +3VS 1 2 3 4 8 7 6 5 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 12 13 37 20 38 EC_RST# EC_SCI# WOWL_EN# 1 2 CB12 0.1U_0402_10V7K 1 2 PLT_RST# CB13 100P_0402_50V8J 1 2 3 4 5 7 8 10 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 29,36,37 29,36,37 17,25 17,25 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 CHG_PWR_GATE# 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 77 78 79 80 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0 67 AD Input CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 3 30 18 18,38 EC_MUTE_INT CLK_EC POK RB37 0_0402_5% 1 Rshort@ 2 EC_MUTE_INT_R 2 POK_R 2 0_0402_5% 0_0402_5% 122 123 XCLKI/GPIO5D XCLKO/GPIO5E 1 2012/02/28 Connect RB14 form CLK_EC_R to POK and reserve RB13,RB22,CB16 1 @ 1RB13 RB14 E51_TXD EC_MUTE_INT_R 2 2013/03/04 change CLK_EC_R to POK_R 1 RB22 100K_0402_5%@ 2013/02/06 PVT Add RB12 RB37 2 2 RB27 100K_0402_5% 1 2 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A CB16 20P_0402_50V8 @ 21 23 26 27 SPI Flash ROM GPIO GPIO RB1 1 Rshort@ 2 0_0402_5% H_PROCHOT# D QB1 S 2N7002K_SOT23-3 2 H_PROCHOT#_EC 2 G 33 29 5 BATT_PRES USB_OC#0 ADP_I ADP_V HDPLOCK EC_ENBKL 36 17,20,29 36,37 37 25 13,19 SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 GPI LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R BATT_PRES 10/16 NC EC Pin23 FB_CLAMP /Pin27 CLK_REQ_GC6# BATT_PRES 68 70 71 72 CB8 47P_0402_50V8J 1 CB9 1 2 100P_0402_50V8J 10/18B Change BATT_TEMPA to BATT_PRES 10/22A chang CB10 to mount +3VS 10/16change HDPLOCK from pin 86 H_PROCHOT#_EC 1 RB6 25 HDPINT 885_EC_ON @ 2 10K_0402_5% +3VL PCH_SUSPWRDN# 18 18 SUSACK# 83 84 85 86 87 88 TP_CLK TP_DATA 18 97 98 99 109 PWRME_CTRL 16 36 VCIN0_PH 119 120 126 128 WLAN_WAKE# 100 101 102 103 104 105 106 107 108 H_PROCHOT#_EC VCOUT0_PH_L PCH_RSMRST# 18 21 EC_LID_OUT# 36 PROCHOT_IN BKOFF# PBTN_OUT# PCH_PWR_EN SA_PGOOD 110 112 114 115 116 117 118 ACIN_D EC_ON_R 124 +EC_V18R 1 +3VS VCIN0_PH connect to power portion (9012 only) WLAN_WAKE# 26 27 WOL_EN# 25 HDPACT BATT_FULL_LED#33 33 CAPS_LED# PWR_SUSP_LED#33 33 BATT_CHG_LOW_LED# 39 SYSON 42 VR_ON SYSON VR_ON 1 RB8 2 4.7K_0402_5% TP_DATA 1 RB9 2 4.7K_0402_5% SYSON 1 RB10 2 4.7K_0402_5% SUSP# 1 RB21 2 10K_0402_5% VR_ON 1 RB23 2 10K_0402_5% VCOUT0_PH_L 1 Rshort@ 2 RB34 0_0402_5% PROCHOT_IN connect to power portion (9012 only) 11/30 Change FB_CLAMP from pin23 to pin127 (UMA don’t use FB_CLAMP), SO I NC RB18 330K_0402_5% 2 1 2 RB751V40_SC76-2 1 885@ RB4 1 RB19 2 2 0_0402_5% 43_0402_5% +1.05VS_VCCP H_PECI +3VL 1 DB1 18,37 ACIN 3 5 CB15 4.7U_0603_6.3V6K Close to EC 2 KB9012QF-A3_LQFP128_14X14 9012@ 38 VS_ON VCOUT0_PH connect to power portion (9012 only) 13 18 34 41 33 33 34,39,40 ON/OFFBTN# LID_SW# SUSP# 2 11/30 Change PM_SLP_S4# from pin127 to pin84 To implement fix code design ACIN_D LID_SW# SUSP# +VTT_EC EC_PECI 2 10K_0402_5% 2 10K_0402_5% TP_CLK 16 16 16 16 EC_SDIO EC_SDI EC_SCK EC_CS0# 73 74 89 90 91 92 93 95 121 127 1 RB7 1 CHG_PWR_GATE# RB11 12/05 Add CHG_PWR_GATE# and add RB11 10K pull high to 3VL 18,42 VGATE 2 47K_0402_5% WLAN_WAKE# 11/30 Change USB_EN#0 from pin84 to pin23. To implement fix code design 33 33 TP_CLK TP_DATA 1 RB35 LID_SW# Reserve this signal to EC by SW demand 2011/10/18a 30 EC_MUTE# PM_SLP_S4# 5 1 2 CB10 100P_0402_50V8J ACIN_D 63 64 65 66 75 76 1 @ WL_BT_LED# USB_EN#0 FANPWM SPI Device Interface Bus VR_HOT# 3 CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 ME_EN/GPXIOA02 VCIN0_PH/GPXIOD00 GND/GND GND/GND GND/GND GND/GND GND0 PM_SLP_S3# PM_SLP_S5# EC_SMI# USB_OC#2 USB_CHG_OC# USB_CHG_EN# USB_EN#2 KB_LED FAN_SPEED1 WL_OFF# E51_TXD E51_RXD PM_PWROK BT_ON SM_SENSE# BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F PS2 Interface 11 24 35 94 113 18 18 17,21 20,27 20,29 29 27 33 10/24D Add BT_ON on GPIO19 5 26 E51_TXD 26 26 18 26 10/16Change SM_SENSE# from pin 85 30 10/24D Change GPIO0B netname from USB_OC#1 to USB_CHG_OC#, Also change this netname to P20 P29 GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F DA Output 2.2K_8P4R_5% 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 E 2013/02/06 change QB1 to SB00000EN00 for X1 code PWM Output AGND/AGND 1 UB1 EC_VDD/AVCC CLK_PCI_EC RB3 22_0402_5% 42 2 69 2 CB3 0.1U_0402_10V7K 1 2 9 22 33 96 111 125 For RF 1 EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC CB1 0.1U_0402_10V7K D +3VL 1 A @ESD@ 1 2 SUSP# CB14 180P_0402_50V8J UB1 NPCE885NB0DX LQFP 128P 885@ RB12 1 4.7K_0402_5% 11/28 Change RB36 from 2.2k to 0 ohm and CB50 to @ EC_ON_R 885@ 2 1 RB20 330K_0402_5% 1 9012@ 2 RB36 0_0402_5% EC_ON 2013/02/06 PVT Reserve CC21 CC23 CC24 CC25 CC26 CC27,ADD CC35 CC20 main source SCV00001K00,2nd source SCV2100P010 +3VL PM_PWROK 38 02/20 Delete CB50 @ESD@ 2 S 3 QB2 D 1 885@ 1 10/18B Add RB24 4 FANPWM ON/OFFBTN# @ESD@ CC25 100P_0402_50V8J 2 1 @ESD@ CC24 100P_0402_50V8J 2 1 CC23 100P_0402_50V8J 4 VCIN0 pin109 VCIN1 pin102 >1.2V VCOUT0 pin104 HIGH (default) VCOUT1 pin103 885_EC_ON 2 G 2N7002K_SOT23-3 Voltage Comparator Pins FOR 9012 A3 RB24 885@ 2 1 10K_0402_5% <1.2V LOW LOW (default) HIGH Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D LPC-EC-KB9012&NPCE885N Document Number Rev 1.0 Monday, March 11, 2013 Sheet E 32 of 46 5 4 3 Conn. Power Button 2 Touchpad Connector JPWR 1 3 5 7 +3VL 2 02/20 Delete SW2, SW3 R395 1 3 5 7 16 14 12 10 8 6 4 2 ON/OFFBTN# +5VS ACES_50611-0040N-001 Conn@ 1 ON/OFFBTN# ON/OFFBTN# NFC 10/18B Update NFC pin define 10/19A Add R6, R7 for NFC JTP Conn@ 2 4 6 8 2 4 6 8 100K_0402_5% D 1 16 14 12 10 8 6 4 2 15 13 11 9 7 5 3 1 15 13 11 9 7 5 3 1 +3VS TP_DATA TP_CLK 32 32 PM_SMBDATA 11,12,17,26 11,12,17,26 PM_SMBCLK D 32 HB_A060877-SAVR01 11/28 Delete NFC Function 2013/02/06 SWAP JTP pindefine for Pre_MP ESD diode on SB 10/22A ESD request Delete D90, covered by ME design 10/22A ESD request Delete D2, covered by ME design 1 JBLG Conn@ C Q52 2N7002KW_SOT323-3 KBL@ ACES_50578-0040N-001 H12 KSI1 KSI6 KSI5 KSI0 KSI4 KSI3 KSI2 KSI7 KSO15 KSO12 KSO11 KSO10 KSO9 KSO8 KSO13 KSO7 KSO6 KSO14 KSO5 KSO3 KSO4 KSO0 KSO1 KSO2 LED 10/18B Update Keyboard pin define 26 2 +5VS 1 @ R269 R819 2 1 10K_0402_5% @ 6 5 2 0_0402_5% D26 2 2 11 2 0_0402_5% R66 HT-191UD5_AMBER_0603 510_0402_5% H18 H19 1 H_3P2x3P7N @ 1 H_3P2N @ H_3P2N @ 3 4 1 Q157A 2N7002DW-T/R7_SOT363-6 @ Q157B 2N7002DW-T/R7_SOT363-6 @ WL_BT_LED# 32 Amber LED bright while Wireless and/or WiMAX turns on. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 GND1 36 GND2 CVILU_CF17341U0R0-NH Conn@ H14 H_3P0 @ H15 H_7P0 @ 11/28 Add H18 ME only change to heng yuan kong, don't need modify H_4P0 11/28 Change H15 from H_3P0 to H_4P0 @ PCB Fedical Mark PAD FD1 @ FD2 @ FD3 @ FD4 @ 1 32 2 1 R376 300_0402_5% H13 H_3P0 @ JKB +3VS LED_WIMAX# 1 R268 H17 H_3P0 @ 1 32 32 White LED bright when system is power on. White LED blink when system is sleep mode. +5VALW H11 H_3P0 @ 1 KSI[0..7] KSO[0..15] CAPS_LED# B H10 H_3P0 @ 1 KSO[0..15] 1 KSI[0..7] PWR_SUSP_LED#32 HT-F196BP5_WHITE WLAN/WiMAX NPTH H9 H_3P2 @ 11/28 Add H19 For ME po kong R61 390_0402_5% 1 2 1 1 D25 1 KEYBOARD CONN. 1 POWER LED H8 H_3P0 @ 1 PTH H7 H_3P0 @ 2 H_3P3 @ C H6 +5VALW H29 10/10 Delete VGA screw hole H4/H5 1 S 2 G H_4P2 @ 1 KB_LED 1 +5VS_LED D 3 White LED bright when both AC-adaptor is plugged in and Battery is full charged Amber LED bright while charging battery from AC-adaptor. 32 Amber LED blink during Critical Low Battery 1 2 3 4 GND GND WLAN standoff H3 H_4P6x4P2 @ 1 1 2 3 4 5 6 H2 1 HT-191UD5_AMBER_0603 32 BATT_CHG_LOW_LED# H_4P6 @ 1 1 2 R3 510_0402_5% 2 1 CPU 10/19A Swap JBLG pin define 1 +5VS_LED 1 1 H1 R587 10K_0402_5% KBL@ G D23 2 D S 3 HT-F196BP5_WHITE +5VALW Screw Hole Q38 KBL@ AO3413_SOT23 +5VS BATT_FULL_LED#32 1 1 2 2 Keyboard LED R60 390_0402_5% 1 2 1 D24 1 BATT CHARGE /FULL LED B ISPD 11/30 Update CPU config and PN CPU (Default) CPU@ SA00004SX00 ZZZ DA6000WJ000 UC1 CPUI73537UR1@ UC1 CPUI53337UR1@ UC1 CPUI73537UR3@ SA00006DB40 SA00006D850 ???????????? UC1 CPUI53337UR3@ PCB LA-9862P Ivy Bridge i7 3537U R1 Ivy Bridge i5 3337U R1 ???????????? Ivy Bridge i7 3537U R3 Ivy Bridge i5 3337U R3 PCH (Default) HM76R1@ BD82HM76 SLJ8E C1 SA00005FHA0 Lid SW Battery Reset UH1 +3VL HM70R1@ UC1 CPUI33227UR1@ UC1 CPUI32375MR1@ UC1 CPUI33227UR3@ SA00006D970 SA00006ED40 ???????????? Ivy Bridge i3 3227U R1 VDD 1 2 C453 0.1U_0402_16V4Z LID_SW# 1 C452 10P_0402_50V8J 10/25A Change SW4 netname from BI to ENLDO and change pin1,2 to GND (delete R5) 10/16Add Battery Reset function 3 1 A VOUT 3 TJG-533-V-T/R_6P 1 ENLDO 2 4 UC1 CPUP2117UR1@ UC1 CPUC847R1@ UC1 CPUP2117UR3@ UC1 CPUC847R3@ SA000061230 SA00005VK00 ???????????? ???????????? Ivy Bridge Pentium 2117U R1 Ivy Bridge Celeron 847 R1 Ivy Bridge Pentium 2117U R3 Ivy Bridge Celeron 847 R3 SW4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 4 Ivy Bridge i3 2375M R3 2 10/18 Power side need add off- page type 5 ???????????? Ivy Bridge i3 3227U R3 A @ 38 Ivy Bridge i3 2375M R1 SA00005MQ50 Panther Point 82HM70 C-1 HM70 32 5 6 2 GND U21 APX9132ATI-TRL_SOT23-3 UC1 CPUI32375MR3@ 3 2 TP/ISPD/KB/LED/Screw Document Number Rev 1.0 VFKTA Monday, March 11, 2013 Sheet 1 33 of 46 A B C +5VALW +5VALW TO +5VS +3VALW TO +3VS Load switch D VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm E +5VS U1 1 2 @ 1 C1 4 +5VALW 5 SUSP# 6 7 +3VALW VIN1 VIN1 VOUT1 VOUT1 ON1 CT1 VBIAS GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 1 14 13 12 C2 1 180P_0402_50V8J 2 C9 1 330P_0402_50V7K 2 @ 11 10 2 1 +3VS 9 8 15 @ 2 C3 0.1U_0402_10V7K 1U_0402_6.3V6K 2 3 SUSP# C8 1 TPS22966DPUR_SON14_2X3 C10 1U_0402_6.3V6K 2 1 0.1U_0402_10V7K @ 1 2 SUSP SUSP 1 1 D Q189 Q5527 D 2 G D Q190 2N7002KW_SOT323-3 2 G 2N7002KW_SOT323-3 S Q60 2 Q6A 2N7002KDWH_SOT363-6 2 SUSP# SUSP# SUSP D S 2 G G S 2N7002KW_SOT323-3 2N7002KW_SOT323-3 1 3 2 32,39,40 SUSP 3 PCH_PWR_EN 1 32 R468 470_0805_5% 6 1 1 9 R421 22_0805_5% 1 R422 100K_0402_5% R470 470_0805_5% 22,23 +1.05VS_VCCP 1 PCH_PWR_EN# +0.75VS 3 PCH_PWR_EN# 1 1 885@ R5546 10K_0402_5% 2 2 R5545 10K_0402_5% 1 2 +1.8VS 2 +5VALW +3VL 2 +5VALW 10/18B Add R5546 2 3 S 2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue For S3 CPU Power Saving 1 R158 2 40,41 0.75VR_EN 220K_0402_5% 39 Q6B 2N7002KDWH_SOT363-6 5 +5VS TO +5VS_ODD +5VS_ODD 2 4 SUSP 0.75VR_EN 3 VCCP_PWRGOOD R457 470_0805_5% 2013/02/06 change QC5,QH3,QH4,QW1, Q6 ,QA1 QR1 Q53 from SB00000EO10 to SB00000DH00 DVT 2nd source for X1 code issue 6 1 ZPODD@ 3 3 Q53A +5VS 3 R440 1 C471 0.1U_0402_10V7K ZPODD@ Q45 2 Vgs=-4.5V,Id=3A,Rds<97mohm 1 1 3 2 2 47K_0402_5% ZPODD@ 2 ZPODD@ 1 AO3413_SOT23 C217 0.01U_0402_25V7K NONZP@ R120 0_0805_5% 2 21 2N7002DW-T/R7_SOT363-6 Q53B ZPODD@ ZPODD@ ZPODD@ R441 100K_0402_5% 1 4 ODD_EN# 1 5 2 +5VS G +3VS D 1 ODD_EN# 2N7002DW-T/R7_SOT363-6 S 2 ZPODD@ +5VS_ODD 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D DC-DC INTERFACE Document Number Rev 1.0 VFKTA Sheet Monday, March 11, 2013 E 34 of 46 A B C D EMI Part (47.1) PL102 FBMA-L11-201209-121LMA50T_0805 1 2 A51 need add fuse 1 @ PJP1 PF1 1 2 3 4 1 2 1 DC_IN_S1 1 1 PC103 100P_0603_50V8 PC101 100P_0603_50V8 2 PC102 1000P_0603_50V7K 2 2 1 ACES_50299-00401-001 1 7A_32V_S1206-H-7.0A 2 1 2 3 4 VIN PL101 FBMA-L11-201209-121LMA50T_0805 1 2 PC104 1000P_0603_50V7K 2 2 For ML1220 RTC (38.2) - PBJ101 @ 2 + 1 PR101 560_0603_5% 1 2 +RTC_R PR102 560_0603_5% 1 2 +RTCBATT ML1220T13RE +RTC 01/17: Change PBJ101 footprint to BJ_ML1220T10_2P 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title DCIN/PRECHARGE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number STODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A Sheet D 35 of 46 A B Other component (37.1) PL3 FBMA-L11-201209-121LMA50T_0805 1 2 VMB PL2 FBMA-L11-201209-121LMA50T_0805 1 2 PF2 1 BATT_S1 D 2 BATT+ 10A_125V_TR2/6125FF10-R 1 2 PR14 1K_0402_1% OTP (39.7) 1 PC7 1000P_0402_50V7K PC8 0.01U_0402_25V7K 2 1 1 +3VL 32,37 +3VL 32 32 1 2 @ PR5 0_0402_5% 1 2 VCIN0_PH EC_SMB_DA1 29,32,37 EC_SMB_CK1 29,32,37 1 1 2 32 @ PC11 0.1U_0402_10V7K 2 2 BATT_PRES PR3 20K_0402_1% PR21 100_0402_1% 1 PR20 100_0402_1% 2 2 2 PR19 1K_0402_1% 1 1 2 PR4 12.1K_0402_1% @ PR2 0_0402_5% 1 2 1 PROCHOT_IN 1 EMI Part (47.1) PR16 6.49K_0402_1% 2 1 PR1 1K_0402_1% 2 ADP_I PH1 100K_0402_1%_TSM0B104F4251RZ BATT_P5 EC_SMDA EC_SMCA 2 1 @ ACES_50299-01001-W01 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 PJP2 C 2 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A B C Sheet D 36 of 46 A B C D for reverse input protection 1 3 Charger controller (40.1), Support component (40.2) D S 2 G PR226 2 2 2 PD230 BAS40CW_SOT323-3 DH_CHG 1 PR210 PQ201 AON7408L @ 2 4 0_0603_5% 2 1 2 PR241 357K_0402_1% PR247 309K_0402_1% PR248 10K_0402_1% 1 2 29,32,36 1 EC_SMB_CK1 PR249 ADP_V 32 1 29,32,36 ADP_I 32,36 2 EC_SMB_DA1 For A51 ADP_V function @ PC246 0.1U_0402_10V7K 2 100P_0402_50V8J @ PR246 0_0402_5% 1 2 @ PC247 0.1U_0402_10V7K 2 47K_0402_1% PC245 2 1 ILIM and external DPM 3.61A 1 VIN 1 PR245 66.5K_0402_1% 1 2 1 Max. 2 Typ 17.23V 17.63V PC244 0.1U_0402_25V6 Min. 2 1 3 1 Vin Dectector H-->L L--> H PC223 10U_0805_25V6K 1 2 1 2 PC206 680P_0603_50V8J @EMI@ 3 2 1 1 EMI Part (47.1) 2 PC243 0.01U_0402_25V7K 2 1 2 BQ24735_ACDET PR244 422K_0402_1% 2 1 VIN PR242 100K_0402_1% BQ24735_ILIM ACIN PC242 0.1U_0603_16V7K +3VALW 3 18,32 2 BQ24735_BATDRV ILIM SCL 11 3 1 2 BQ24735_ACOK 10K_0402_1% BATDRV 10 1 PR239 6 +3VL ACOK 12 PR236 10_0603_1% 2 CSOP1 SRP1 PR237 6.8_0603_5% 2 CSON1 SRN1 13 SRN SDA 5 ACDRV 9 4 8 BQ24735_ACDRV 14 CMSRC BQ24725RGRR_QFN20_3P5X3P5SRP IOUT 3 7 BQ24735_CMSRC ACDET 2 2 PC222 10U_0805_25V6K AON7406L PR227 0.01_1206_1% 4 2 GND 4 DL_CHG 1 CSON1 1 ACP 15 2 LODRV CHG 5 16 PQ202 ACN 2 1 1 BQ24735_LX 2 3 2 1 PC205 2 1 PC241 0.1U_0402_25V6 BATT+ PL202 4.7UH_ETQP3W4R7WFN_5.5A_20% REGN BTST HIDRV PAD 1 1 PD231 RB751V-40_SOD323-2 BQ24735_REGN2 PR229 2.2_0603_5% 1 BQ24735_BST 2 17 18 20 19 PHASE 1 VCC 21 2BQ24735_BATDRV_1 5 2 1U_0603_25V6K PU200 1 PR233 4.12K_0603_1% PC237 1 DH_CHG BQ24735_LX PR228 10_1206_1% 1 1 2 BQ24735_VCC 1 2 1 2 PC238 0.1U_0603_25V7K 1 2 PR235 4.12K_0603_1% 1 PR234 4.12K_0603_1% 1U_0603_25V6K BQ24735_ACN BQ24735_ACP 2 PC239 1 2 BQ24735_BATDRV 0.047U_0402_25V7K CSOP1 PC236 0.1U_0402_25V6 SI7716ADN-T1-GE3_POWERPAK8-5 2 2 3 1 1 2 3 4 VIN SI7716ADN-T1-GE3_POWERPAK8-5 BQ24735_ACDRV_1 2 PQ207 5 PC240 0.1U_0402_25V6 3 PR206 4.7_1206_5% @EMI@ 2 PL201 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 2 1 5 PR211 0.01_1206_1% 4 1 1 B+ 1 4 1 2 4 PC231 0.1U_0402_25V6 1 2 PC230 2200P_0402_50V7K 5 1 PQ205 2 3 2 P2 1 2 3 PC213 10U_0805_25V6K P1 PQ203 PC235 0.1U_0402_25V6 VIN TPCA8057-H_PPAK56-8-5 PC234 0.01U_0402_50V7K EMI Part (47.1) 1 1 3M_0402_5% 2 1 PC214 0.1U_0402_25V7K 2 1M_0402_5% PC211 10U_0805_25V6K PR225 1 PQ209 SSM3K7002FU_SC70-3 4 4 Please locate the RC Near EC chip 2011-02-22 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A B C Sheet D 37 of 46 A B C D 5V Peak Current 10A OCP current 12.03A FSW=390kHz Delta I=4.29A,ripple=4.29*17m=72.93mV DCR 15.5mohm+/-15% ESR 17mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :10.8mohm , 13.6mohm 3/5VALW controller (35.1), Support component (35.2) 1 @ PC345 100P_0402_50V8J 1 2 2 1 20 BOOT2 LGATE1 17 LX_5V 16 LG_5V 2 PL352 2.2UH_ETQP3W2R2WFN_8.5A_20% 1 2 PU330 RT8243AZQW_WQFN20_3X3 4 1 3 2 1 1 2 2 PC342 1U_0603_10V6K 2 1 2 EMI Part (47.1) 2 3 2 3.3V Peak Current 8A OCP current 9.68A Delta I=1.28A ,ripple=1.28x15m=19.2mV FSW=455kHz DCR 35mohm +/-15% ESR 15mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :19mohm , 23.5mohm 33 2 @ PR341 0_0402_5% 1 2 1 VS_ON 1 32 PQ352 FDMC7692S_MLP8-5 PC341 4.7U_0603_10V6K 1 + @ PR332 100K_0402_5% 3 PC344 4.7U_0603_10V6K ENLDO PR340 2.2K_0402_1% 1 2 PC343 4.7U_0603_6.3V6K EC_ON PR338 100K_0402_1% 2 1 1 32 PC360 0.1U_0603_25V7K 3/5V_B+ EMI Part (47.1) +3VLP PR334 499K_0402_1% 1 2 AON7406L PQ332 +5VALWP 220U_6.3V_M LDO5 SECFB LDO3 15 14 13 11 12 VIN ENLDO LGATE2 4 2 2 1 2 3 1 @EMI@ PC336 @EMI@ PR336 680P_0603_50V8J 4.7_1206_5% 2 1 SNUB_3V 2 1 PC331 220U_6.3V_M 5 PHASE1 + UG_5V PC351 UGATE1 PHASE2 1 10 UGATE2 PR356 4.7_1206_5% @EMI@ LG_3V 18 AON7408L PQ351 2 SNUB_5V 9 BST_5V PC355 0.1U_0402_10V7K 2 BST1_5V1 3 2 1 8 LX_3V 19 1 +3VALWP UG_3V 4 @ PR355 0_0402_5% 1 2 PC356 680P_0603_50V8J @EMI@ PL332 4.7UH_ETQP3W4R7WFN_5.5A_20% 2 1 5 21 PAD BYP1 5 7 3 2 BST_3V PGOOD FB1 6 PC335 @ PR333 0.1U_0402_10V7K 0_0402_5% 1 2 BST1_3V 1 2 BOOT1 2 1 PR351 19.1K_0402_1% 1 2 FB_5V ENTRIP1 POK TON PQ331 AON7408L PR335 100K_0402_1% 18,32 4 1 2 PR337 226K_0402_1% 1 2 PR342 56K_0402_1% 1 2 PR357 143K_0402_1% FB_3V 2 4 1 3/5V_B+ ENTRIP2 5 +3VL 1 2 3 2 PR331 20K_0402_1% 1 2 PC340 10U_0805_25V6K 1 2 PC339 0.1u_0402_50V7K 2 1 1 PR330 14K_0402_1% 1 2 3/5V_B+ 5 PL331 HCB2012KF-121T50_0805 PR350 30K_0402_1% 1 2 FB2 B+ PC361 10U_0805_25V6K EMI Part (47.1) 1 @ PJ333 +3VLP 2 2 1 @ 1 +3VL 1 +3VALWP JUMP_43X39 1 PJ331 2 2 +3VALW JUMP_43X118 (100mA,40mils ,Via NO.= 2) @ 1 +5VALWP 1 PJ332 2 2 +5VALW JUMP_43X118 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title 3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A B C Sheet D 38 of 46 A DDR controller (35.3), Support component (35.4) PL151 HCB1608KF-121T30_0603 1 2 B+ EMI Part (47.1) 1.5V_B+ PR155 1 BST_1.5V-1 2 +1.5V BST_1.5V 1 PC160 10U_0805_6.3V6K 2 +1.5VP PR163 0_0402_5% 1 2 1 PC163 0.033U_0402_16V7K 6 7 8 2 1.5V_B+ @ PR160 10.2K_0402_1% 2 1 FB_1.5V 2 +1.5VP PR161 510K_0402_1% 1 2 PR162 10K_0402_1% EN_1.5V 1 SYSON 2 19 20 VTT BOOT VLDOIN 17 1 +5VALW TON_1.5V 2 18 UGATE VDDQ PC156 680P_0402_50V7K 32 VTTREF_1.5V 5 FB VDD 9 PC164 1U_0603_10V6K 4 VTTREF 1 +5VALW 2 3 GND RT8207MZQW_WQFN20_3X3 VDDP S3 4 1 VTTSNS S5 11 CS 21 PAD VTTGND PGND TON 12 VDD_1.5V 2 PR156 4.7_1206_5% PR159 5.1_0603_5% 1 2 1 2 3 1 FDMC7692S_MLP8-5 PQ152 5 PC162 1U_0603_10V6K 1 2 LGATE 1 2 14 13 SNUB_+1.5VP 2 PC157 + 330U_D2_2V_Y 1 16 PR158 27.4K_0402_1% 1 2CS_1.5V PHASE 15 PGOOD 4 PU150 PC159 10U_0805_6.3V6K PC155 0.1U_0603_25V7K 1 2 DL_1.5V 10 PQ151 AON7408L SW_1.5V 1 2 3 PL152 0.68UH_PCMB053T-1R0MS_8.5A_20% 2 1 +1.5VP +0.75VSP DH_1.5V 5 1 2 PC154 10U_0805_25V6K 1 2 PC152 330P_0402_50V7K 2.2_0603_5% @ PJ151 1 1 @ PC166 0.1U_0402_10V7K 34 2 2 2 PR164 0_0402_5% 2 1 0.75VR_EN EN_0.75VSP 1 1 1 +0.75VS +1.5VP JUMP_43X39 @ PJ152 1 1 2 +1.5V JUMP_43X118 @ PC167 0.1U_0402_10V7K @ (15A, 600mils ,Via NO.= 30) OCP=18A (0.5A,40mils ,Via NO.= 1) PJ180 2 2 +1.8VS 1.8VS controller (35.15), Support component (35.16) On S3 Lo Hi On On Lo Lo On Off (Hi-Z) 0_0402_5% @ PR182 499K_0402_1% PC185 @ 0.1U_0402_10V7K FB_1.8V PR184 10K_0402_1% 1 PC183 22U_0603_6.3V6M On EN_1.8V 32,34,40 PC186 2 1 Hi @ PR181 1 2 1 Hi SUSP# 2 S0 0.75VSP 1 VTT_REFP 2 S5 PR183 20K_0402_1% 2 1 PC182 22U_0603_6.3V6M EN +1.8VSP 1 FB 2 2 GND PL182 1UH_NRS4018T1R0NDGJ_3.2A_30% 1 2 LX_1.8V 1 PG 3 PC187 68P_0402_50V8J 2 1 6 PC184 22U_0805_6.3VAM LX 2 1 5 IN 1 4 2 +5VALW PU180 SY8032ABC_SOT23-6 PL181 HCB1608KF-121T30_0603 1 2 2 S3 S4/S5 1.5VP 1 JUMP_43X79 1.5V Peak Current 16.8A OCP current 20 A FSW=495kHz DCR 13mohm ESR 9mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :10.8mohm , 13.6mohm STATE 1 +1.8VSP 680P_0402_50V7K 1 PR186 4.7_0402_1% 1 2 2 2 2 +0.75VSP 1 1 JUMP_43X118 @ PJ153 2 Off Off Off (Discharge) (Discharge) (Discharge) Note: S3 - sleep ; S5 - power off Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Deciphered Date 2015/04/19 Title 1.5VP/0.75VSP/1.8VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: A Sheet 39 of 46 5 4 3 2 1 D D 1.05VCCP controller (35.5), Support component (35.6) @ PR402 0_0402_5% 1 32,34,39 SUSP# @ PC402 0.1U_0402_16V7K 2 1 2 EMI Part (47.1) @EMI@ PR403 4.7_1206_5% 1 2 EMI Part (47.1) PL401 @EMI@ PC403 680P_0603_50V7K 1 2 C PU400 1 1 1 @ PR413 0_0402_5% 2 2 2 34,41VCCP_PWRGOOD 2 +3VALW SY8208DQNC_QFN10_3X3 PC411 22U_0603_6.3V6M 2 7 5 1 LDO 2 PG +1.05VS_VCCPP PC410 22U_0603_6.3V6M 2 1 PR401 100K_0402_5% PGD_1.05V 1 2 BYP 1 1 ILMT 4 PR404 75K_0402_1% FB 3 +3VS +3VS PL402 0.68UH_PCMC063T-R68MN_15.5A_20% 1 2 SW_+1.05VSP 10 2 LX 1 GND PC409 22U_0603_6.3V6M 9 1 PC406 0.1U_0603_25V7K 6 1 2 1 BS 2 EN PC408 22U_0603_6.3V6M IN PR406 PC407 1K_0402_1% 4700P_0402_16V7K 8 PC413 2.2U_0603_6.3V6K PC404 PC401 2 1 10U_0805_25V6K +1.05VSP_B+ PC412 4.7U_0603_6.3V6K 2 1 HCB2012KF-121T50_0805 2 1 0.1U_0402_50V7K 2 1 B+ SNUB_+1.05VSP 2 C 1 VCCIO_SENSE B 2 B 8 PR405 100K_0402_1% The current limit is set to 8A, 12A or 16A when this pin is pull low, floating or pull high respectively. @ PJ401 +1.05VS_VCCPP 2 2 1 1 +1.05VS_VCCP JUMP_43X118 (17A,680mils ,Via NO.=34) OCP=23.91A A A 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 +1.05VS_VCCP Document Number Rev 1.0 VFKTA Monday, March 11, 2013 Sheet 1 40 of 46 5 4 3 2 1 VID [0] 0 0 1 1 D VID[1] 0 1 0 1 VCCSA Vout 0.9V 0.85V 0.775V 0.75V D VCCSA controller (35.17), Support component (35.18) +VCCSAP @ 1 +VCCSA PJ602 1 2 2 JUMP_43X118 PEN@ 1 +1.05VS_VCCP C PR611 2 +VCCSA C 0.005_1206_1% PC626 22U_0603_6.3V6M 2 1 8 PC624 1U_0603_6.3V6M 2 1 34,40 VCCP_PWRGOOD 7 @ PR601 0_0402_5% 1 2 Vo VPP Vo POK D1 VEN/MODE D0 G978F11U_SO8 +VCCSAP 4 3 2 1 @ PR621 0_0402_5% 1@ PR622 2 0_0402_5% 1 2 H_VCCSA_VID1 9 H_VCCSA_VID0 9 0.9V PC618 22U_0603_6.3V6M 2 1 SA_PGOOD VIN PC616 22U_0603_6.3V6M 2 1 6 +5VALW GND PC615 22U_0603_6.3V6M 2 1 5 +VCCSA_B+ PC613 22U_0603_6.3V6M 2 1 PC628 22U_0603_6.3V6M 2 1 PU601 9 PC629 1U_0603_6.3V6M 2 1 2 32 PR610 100K_0402_5% 1 +3VS B B 2 +1.05VS_VCCP @ PJ601 1 1 2 +VCCSA_B+ JUMP_43X79 (6A, 240mils ,Via NO.= 6) A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 2015/04/19 Deciphered Date Title VCC_SAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 VFKTA Date: 5 4 3 2 Sheet 1 41 of 46 4 3 CPU_Core controller (36.1), Support component (36.3) @ PC535 1000P_0402_50V7K 2 UGATE1-1 0_0603_5% @ 4 3 2 1 PHASE1 PR530 2.2_0603_5% 1 2 1 PQ502 2 BOOTG LGATE1 4 PC527 0.22U_0603_16V7K UGATEG LGATEG TPCA8059-H_PPAK56-8-5 25 UGATE1 19 LGATE1 18 PHASE1 17 UGATE1 +CPU_B+ 16 15 9 PR557 27.4K_0402_1% PQ503 18,32 PR558 +3VS 2 UGATEG 1 PR504 @ 1.91K_0402_1% AON7518_DFN8-5 PHASEG 5 1 PQ504 PC516 0.22U_0603_16V7K 4 2 3 2 1 LGATEG PR516 2.2_0603_5% BOOTG TPCA8059-H_PPAK56-8-5 2.61K_0402_1% 1 PR562 12 1 11K_0402_1% 2 PR565 1 2 2 PC552 0.1U_0603_25V7K 1 2 PR564 422_0402_1% 1 2 1 PR563 649_0402_1% 2 local sense revese HW A B Rds(on)=2.2m-3.3m ohm 10K_0402_1%_ERTJ0EG103FA VSUM.1U_0402_16V7K 2 PR568 137K_0402_1% PC554 150P_0402_50V8J 1 2 PC556 2 1 1 PR513 3.65K_0603_1% +GFX_CORE PH4 1 PR567 2.05K_0402_1% 1 2 PC551 68P_0402_50V8J 1 2 PC555 6800P_0402_25V7K PC550 470P_0402_50V7K 1 2 1 2 PR566 499_0402_1% PL503 0.22UH_MMD-06DZNR22MEO1L_25A_20% 2 1 VSUM+ PC553 0.022U_0402_16V7K PR561 42.2K_0402_1% 1 2 2 PC549 PR560 470P_0402_50V7K 2K_0402_1% 1 2 1 2 C 2 UGATEG-1 4 0_0603_5% 3 2 1 1 1 2 2 B 14 5 BOOT1 VGATE 2 2 1 PR514 1_0402_5% 1 2 2 20 1 PR536 1_0402_5% VSUMG- PHASE1 1 1 UGATEG NTC 2 26 BOOTG 28 29 30 31 32 27 PGOODG COMPG FBG RTNG ISUMNG LGATE1 PR559 3.83K_0402_1% 2 1 +1.05VS_VCCP PH3 470K_0402_5%_ TSM0B474J4702RE 2 1 2 1 1 2 +5VS @ @ PC548 0.1U_0402_16V7K VR_HOT# ISEN2 21 PWM2 2 PR532 3.65K_0603_1% 1 0_0402_5% SDA VSUM+ 1 @EMI@ PC526 680P_0402_50V7K 2 1 2 1 @EMI@ PR526 4.7_1206_5% 1 PR553 499_0402_1% 2 1 PR554 130_0402_1% 2 1 PR555 75_0402_5% 2 1 PR556 54.9_0402_1% 1 8 2 @ 2 @ PC547 47P_0402_50V8J 1 22 VDD +CPU_CORE For ULT 17W 1+1 CPU_CORE LL= -2.9mΩ, Fsw = 450 kHz Icc_TDC=16A, Iocp_cpu=39.6A GFX_CORE LL= -3.9mΩ, Fsw = 450 kHz Icc_TDC=21.5A, Iocp_gfx=39.6A @ PR551 PR550 1_0603_5% 0_0603_5% PC545 1U_0603_10V6K 23 PL502 0.22UH_MMD-06DZNR22MEO1L_25A_20% 2 1 VSUM- PC533 10U_0805_25V6K 2 1 7 PR552 Rds(on)=2.2m-3.3m ohm PC546 1U_0603_10V6K 2 1 6 VR_HOT# ISL95833HRTZ-T_TQFN32_4X4 BOOT1 5 24 VCCP ALERT# PGOOD SDA SCLK COMP 4 ISUMPG PAD 3 ALERT# FB 32 SCLK LGATEG 13 VR_SVID_DAT 0_0402_5% VR_ON RTN 8 2 PHASEG 12 VR_SVID_ALRT# 470K_0402_5%_ TSM0B474J4702RE NTCG ISUMN VR_SVID_CLK 8 1 11 8 PH2 NTCG ISUMP VR_ON 2 10 32 1 ISEN1 PR549 3.83K_0402_1% 1 2 PR548 1 2 C 27.4K_0402_1% 2 33 +5VS PU500 PR547 1 3 2 1 PR546 PHASEG D VSUMG+ 2 BOOT1 AON7518_DFN8-5 2 B+ PC534 10U_0805_25V6K 2 1 PC544 470P_0402_50V7K + 100U_25V_M 1 PR528 UGATE1 1 2 PR542 2K_0402_1% @EMI@ PC506 680P_0402_50V7K 2 1 2 1 @EMI@ PR506 4.7_1206_5% +3VS 2.67K_0402_1% 1 PC500 PR541 1 PQ501 PL501 HCB2012KF-121T50_0805 1 2 2 2 PC532 10U_0805_25V6K 2 1 PC531 10U_0805_25V6K 2 1 1 5 470P_0402_50V7K 2 2 1 1.91K_0402_1% 2 1 150P_0402_50V8J 2 VSUMG+ PC540 2 2 2 1 PC543 2200p_0402_25V7K 1 PR539 422_0402_1% PR543 11K_0402_1% PR545 2.61K_0402_1% PC542 0.1U_0603_25V7K 2 1 2 1 .1U_0402_16V7K PC541 2 1 2 1 1 1 VSUMG- 2 +CPU_B+ PR540 137K_0402_1% 1 2 1 PR544 13.3K_0402_1% 2 D PC539 1 PR538 499_0402_1% 1 2 PC510 0.1U_0402_50V7K PC538 68P_0402_50V8J 1 2 PR537 649_0402_1% PH5 10K_0402_1%_ERTJ0EG103FA PC536 0.01U_0402_25V7K 2 2 1 1 1 2 VCC_AXG_SENSE 9 VSS_AXG_SENSE 9 PC537 6800P_0402_25V7K 1 5 local sense revese HW 2 1 5 Close Phase 1 choke A PC557 @ 330P_0402_50V7K 1 2 8 VCCSENSE 8 VSSSENSE 1 2 PC558 0.01U_0402_25V7K Compal Secret Data Security Classification Issued Date local sense revese HW 2012/04/19 2015/04/19 Deciphered Date Title CPU_CORE Date: 5 Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Rev 1.0 VFKTA Sheet Monday, March 11, 2013 1 42 of 46 5 4 3 CPU_Core output CAP (Including MLCC) 36.4 2 1 GFX output CAP (Including MLCC) 36.5 +GFX_CORE 2 1 2 PC858 22U_0603_6.3V6M 2 1 PC857 22U_0603_6.3V6M 2 1 PC856 22U_0603_6.3V6M 2 1 PC855 22U_0603_6.3V6M 2 PC810 2.2U_0402_6.3V6M 1 PC854 22U_0603_6.3V6M 1 PC809 2.2U_0402_6.3V6M 2 1 PC808 2.2U_0402_6.3V6M 2 1 PC807 2.2U_0402_6.3V6M 2 1 PC806 2.2U_0402_6.3V6M 2 1 D 2 1 PC853 22U_0603_6.3V6M +CPU_CORE VCCP output Cap (Including MLCC) 36.6 D PC437 1U_0402_6.3V6K 2 1 PC438 1U_0402_6.3V6K 2 1 PC439 1U_0402_6.3V6K PC450 1U_0402_6.3V6K 2 1 PC451 1U_0402_6.3V6K 2 1 PC452 1U_0402_6.3V6K 2 1 2 PC453 22U_0603_6.3V6M PC436 1U_0402_6.3V6K 2 1 PC449 1U_0402_6.3V6K 2 1 2 1 PC426 22U_0603_6.3V6M PC435 1U_0402_6.3V6K 2 1 PC448 1U_0402_6.3V6K 2 1 2 1 PC425 22U_0603_6.3V6M PC434 1U_0402_6.3V6K 2 1 PC447 1U_0402_6.3V6K 2 1 2 1 PC422 22U_0603_6.3V6M PC433 1U_0402_6.3V6K 2 1 PC446 1U_0402_6.3V6K 2 1 2 1 PC421 22U_0603_6.3V6M PC432 1U_0402_6.3V6K 2 1 PC445 1U_0402_6.3V6K 2 1 2 1 PC420 22U_0603_6.3V6M PC431 1U_0402_6.3V6K 2 1 PC444 1U_0402_6.3V6K 2 1 2 1 PC419 22U_0603_6.3V6M PC430 1U_0402_6.3V6K 2 1 PC443 1U_0402_6.3V6K 2 1 2 1 PC418 22U_0603_6.3V6M PC424 10U_0603_6.3V6M PC429 1U_0402_6.3V6K 2 1 PC442 1U_0402_6.3V6K 2 1 1 PC417 22U_0603_6.3V6M PC423 10U_0603_6.3V6M 2 1 PC428 1U_0402_6.3V6K 2 1 PC441 1U_0402_6.3V6K 2 1 1 PC454 10U_0603_6.3V6M 2 1 2 PC864 10U_0603_6.3V6M PC870 1U_0402_6.3V6K 1 PC863 10U_0603_6.3V6M 2 1 PC869 1U_0402_6.3V6K 2 1 PC875 1U_0402_6.3V6K PC427 1U_0402_6.3V6K 2 1 PC862 10U_0603_6.3V6M 2 1 PC868 1U_0402_6.3V6K 2 1 PC876 1U_0402_6.3V6K 2 1 2 PC861 10U_0603_6.3V6M 2 1 PC867 1U_0402_6.3V6K 2 1 PC874 1U_0402_6.3V6K 2 1 PC440 1U_0402_6.3V6K 2 1 PC860 10U_0603_6.3V6M 2 1 PC866 1U_0402_6.3V6K 2 1 2 C PC873 1U_0402_6.3V6K 2 1 1 2 1 PC821 2.2U_0402_6.3V6M PC859 10U_0603_6.3V6M 2 1 1 2 1 PC820 2.2U_0402_6.3V6M 2 1 PC819 2.2U_0402_6.3V6M 2 1 PC818 2.2U_0402_6.3V6M 2 1 PC817 2.2U_0402_6.3V6M 2 1 2 PC816 2.2U_0402_6.3V6M PC865 1U_0402_6.3V6K 2 1 PC815 2.2U_0402_6.3V6M PC872 1U_0402_6.3V6K 2 1 1 PC814 2.2U_0402_6.3V6M 2 1 PC813 2.2U_0402_6.3V6M 2 1 PC812 2.2U_0402_6.3V6M 2 1 PC811 2.2U_0402_6.3V6M 2 1 2 +1.05VS_VCCP C 1 2 1 PC822 22U_0603_6.3V6M 2 1 PC835 22U_0603_6.3V6M 1 PC823 22U_0603_6.3V6M 2 1 PC824 22U_0603_6.3V6M 2 1 PC825 22U_0603_6.3V6M 2 1 PC826 22U_0603_6.3V6M 2 PC827 22U_0603_6.3V6M 1 + 2 B 1 2 1 PC828 22U_0603_6.3V6M 2 1 PC829 22U_0603_6.3V6M 2 1 PC830 22U_0603_6.3V6M 2 1 PC831 22U_0603_6.3V6M 2 + PC832 22U_0603_6.3V6M 2 2 PC833 22U_0603_6.3V6M Chief River ULV + 330uF*9m CPU 1 PC802 330U_D2_2V_Y B 1 +CPU_CORE 1 2 2 2 2 1 PC834 22U_0603_6.3V6M PC852 560U_D2_2VM_R4.5M 1 1 +CPU_CORE 2 22uF 10uF 2.2uF 14 1uF 470uF 560uF 16 PC803 470U_D2_2VM_R4.5M GFX_CORE 2 6 1.05V_VCCP 6 11 10 26 1 1 A A Compal Secret Data Security Classification 2012/04/19 Issued Date Deciphered Date 2015/04/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size 4 3 2 Document Number Rev 1.0 VFKTA Date: 5 Compal Electronics, Inc. PWR - PROCESSOR DECOUPLING Monday, March 11, 2013 Sheet 1 43 of 46 5 4 3 2 Version change list (P.I.R. List) 1 Page 1 of 1 for PWR D D C C B B A A 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2015/04/19 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 PWR-PIR Rev 1.0 VFKTA Monday, March 11, 2013 Sheet 1 44 of 46 A B C D E HW PIR (Product Improve Record) VFKTA LA-9862P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 0.2 1 2 NO DATE PAGE MODIFICATION LIST PURPOSE --------------------------------------------------------------------------------------------------------------------------------------------------1. 11/28 (P.30) Mount CA32(SE102104K00) BOM structure change 2. 11/28 (P.32) Change RB36 from 2.2k to 0 ohm and CB50 to @ Design change 3. 11/28 (P.24) Add @ to JHDMI BOM structure change 4. 11/28 (P.11) Move RD10, RD11 to page 12. 5. 11/28 (P.33) Delete NFC Function Design change 6. 11/28 (P.28) Change JCARD.10 to SDWP# and JCARD.11 to SDCD. Design change (P.28) Add QW1, RW3, RW4 for normal close type connector 7. 11/28 (P.13) Add D92 for LID_SW#_D to isolate the +3VL power rail from LID_SW# Design change 8. 11/28 (P.15) Update HDMI power circuit Design change 9. 11/28 (P.20) Change USB port 10 to NC. Design change 10. 11/28 (P.16) Change UH3 from socket to IC Design change 11. 11/28 (P.09) Change CC44 to 0805 size (SE00000PL00), Add CC40 For 1206 MLCC Crack issue (P.09) Change CC53 to 47U 0805 (SE00000PL00),Add CC50 (SE00000PL00) (P.12) Change CD31 to 0805 size (SE00000PL00) (P.29) Change CR10, CR12 to 0805 size (SE00000PL00) 12. 11/28 (P.14) change BOM structure C238,C239,C240,C241,C242,C243 to CRT@EMI@ EMI request 13. 11/28 (P.16) Change UH3 from socket to IC Design change 14. 11/28 (P.07) Change RC73 to 0 ohm (do not use short pad on this location) For debug 15. 11/28 (P.30) Change RA50 to 269@ Design change 16. 11/28 (P.31) Change SPK connector to 6 pin, change SPK_DET0 to SPK_DET, delete SPK_DET1 and RA96 Design change 17. 11/28 (P.21) Change SPK_DET0 to SPK_DET, delete SPK_DET1 Design change 18. 11/28 (P.13) Delete D92 and change the netname to BKOFF# for touch Screen Avoid LCD_INV leak to Touch/B 19. 11/28 (P.13) SWAP R92,R100 L60 config,SWAP R93.R101,L59 config BOM structure change 20. 11/28 (P.13) Reverse LVDS connector pin definition Design change 21. 11/28 (P.33) Change H15 from H_3P0 to H_4P0,Add h19 H_3P2N ME follow ME change ME request 22. 11/29 (P.28) Modify Jcard @ to update Netlist BOM structure change 23. 11/29 (P.13) Delete R87,R88,R89,R90,R92,R93,R100,R101,L59,L60,JCAM,JEDP Design change (P.13) Change L56 toL55,L58 to L57, JLVDS type and modify net name for LVDS Design change 24. 11/29 (P.14) add R62,R63,22-ohm (PN: SD028220A80) on CRT HSYNC/VSYNC trace. For CRT undershoot issue 25. 11/29 (P.16) Chane UH4, RH269, RH271 to @,change RH267 from shortpad to 0-ohm Design change 26. 11/30 (P.8) Add CC17~CC19 for ESD request ESD request 27. 11/30 (P.20) Move PLT_RST# ESD capacitor (CH104) to EC side (CB13) and mount 0.1uF ESD request 28. 11/30 (P.5) Change CC63 from @ESD@ to ESD@ for ESD request ESD request 29. 11/30 (P.30) Reserve RA31,RA38 for EMI request EMI request 30. 11/30 (P.32)Change PM_SLP_S4# from pin127 to pin84. (P.32)Change USB_EN#0 from pin84 to pin23. 31. 11/31 (P.33)Update CPU config&PN 32. 12/04 (P.29) Update S&C to 14640/14641 co-layout circuit ,add RR1~RR4, QR1, modify net-name Design change 1 2 REVISION CHANGE: 0.2 TO 0.3 3 NO DATE PAGE MODIFICATION LIST PURPOSE --------------------------------------------------------------------------------------------------------------------------------------------------1. 01/18 2. 01/18 3. 01/18 4. 01/18 5. 01/18 6. 01/18 7. 01/18 8. 01/18 9. 01/18 10.01/18 (P.28) (P.20) (P.07) (P.32) (P.05) (P.21) (P.32) (P.18) (P.32) (P.28) Delete QW2 Change RH166 from ShortPad to 0 ohm resistor. Delete RC3. Add RB12, RB37, connect EC_MUTE_INT from codec to EC Add CC35,CC20 reserve CC21 reserve CC23,CC24,CC25 reserve CC26,CC27 Change CB13 to 100P P/NSE071101J80 Add RW2 CW9 3 Design Change For ESD Request Design Change For boot bobo issue For ESD Request For ESD Request For ESD Request For ESD Request Design Change For EMI Request 4 4 2012/04/19 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2015/04/19 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D HW-PIR Rev 1.0 VFKTA Monday, March 11, 2013 Sheet E 45 of 46 5 HW PIR (Product Improve Record) 4 3 2 1 HW PIR (Product Improve Record) VFKTA LA-9862P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.3 TO 1.0 D NO DATE PAGE MODIFICATION LIST PURPOSE --------------------------------------------------------------------------------------------------------------------------------------------------- 1. 01/28 2. 01/28 3. 01/28 4. 01/28 5. 01/28 6. 01/28 7. 01/28 8. 01/28 9. 01/28 10.01/28 11.01/28 12.02/18 13.02/18 14.02/19 15.02/19 16.02/19 17.02/19 18.02/19 C 19.02/19 20.02/19 21.02/19 22.02/19 23.02/19 24.02/19 25.02/19 26.02/19 27.02/19 28.02/19 29.02/19 30.02/28 31.02/28 32.03/04 33.03/04 34.03/04 35.03/06 (P.33) Modify JTP pin with the same as VFKTA DIS (P.13) Reserve R267&R266 0 ohm (P.32) Change QB1 to SB00000EN00 (P.07) Change QC3 to SB00000PF00 (P.15) Change QY1 QY2 to SB00000PF00 (P.16) Change UH3 from SA00003K800 to SA00004LI00 (P.27/29)Change UR1 UR4 from SA00004KB00 to SA00003TV00 (P.13) Change L2 SM01000CD00E to SM01000JB00 (P.9/17/28/34/30/29) Change QC5,QH3,QH4,QW1,Q6 ,QA1, QR1, Q53 from SB00000EO10 to SB00000DH00 (P.30) Change RA42 from SM01000CY00 to SM01000A900 (P.29) Change LR2,LR3,LR4,LR5 from SM070001U00 to SM070001R00 (P.06) Swap H_EDP_TXN[0\1] to H_EDP_TXP[0\1] (P.13) Change C7 to SE076153K80 (15nF) (P.05) Delete CC33, CC36, C4; change R1 to short pad (P.07) Change RC73 to short pad (P.09) Delete CC61, CC83; change RC119 to short pad (P.11) Delete CD2, CD15 (P.12) Delete cD28, CD46 (P.13) Change R106 to shortpad (P.14) Delete C250 (P.16) Delete CH6, CH100; change RH67, RH68 to short pad (P.19) Delete RH254 (P.26) Delete CCL2, RCL5, RCL2, net: LAN_X1_R_R, LAN_X1_R (P.27) Delete net: LAN_X1_R (P.28) Change RW1 to shortpad (P.29) Delete CR7, CR8 (P.30) Change RA22, RA18, RA24 to short pad (P.41) Delete CB4, CB5, CB50 (P.42) Delete SW2, SW3 (P.32) Connect RB14 form CLK_EC_R to POK and reserve RB13,RB22,CB16 (P.20) change RH167 pin2 netname from CLK_EC_R to CLK_PCI_EC_R (P.20) change RH167 pin2 netname from CLK_PCI_EC_R to CLK_EC_R (P.32) Connect RB14 from POK_R to POK and reserve RB13,RB22,CB16 (P.28) Add RW5~RW8 for EMI request and change netname SD_DATA[0…3] to SD_DATA[0…3]_R on connector side (P.28) Add 10pF CV10~CV13 on SD_DATA[0:3] D Design Change For EMI cost down For X1 code issue For X1 code issue For X1 code issue For X1 code issue For X1 code issue For EOL issue For X1 code issue For X1 code issue For X1 code issue Design mistake for LCD sequence tuning for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for part count reduce for abnormal shut down power request For for for for C keep the same as DIS abnormal shut down power request EMI request EMI request. B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2012/04/19 Issued Date Deciphered Date 2015/04/19 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 Title HW-PIR Size A3 Date: Document Number Monday, March 11, 2013 Rev 1.0 Sheet 46 of 46 www.s-manuals.com