design, implementation and evaluation of an auxiliary energy

PONTIFICIA UNIVERSIDAD CATOLICA DE CHILE
ESCUELA DE INGENIERIA
DESIGN, IMPLEMENTATION AND
EVALUATION OF AN AUXILIARY ENERGY
SYSTEM FOR ELECTRIC VEHICLES, BASED
ON ULTRACAPACITORS AND BUCK-BOOST
CONVERTER
MICAH E. ORTÚZAR
Thesis submitted to the Office of Research and Graduate Studies in partial
fulfillment of the requirements for the Degree of Doctor in Engineering
Sciences
Advisor:
JUAN W. DIXON
Santiago de Chile, July, 2005
PONTIFICIA UNIVERSIDAD CATOLICA DE CHILE
ESCUELA DE INGENIERIA
Departamento de Ingeniería Eléctrica
DESIGN, IMPLEMENTATION AND
EVALUATION OF AN AUXILIARY ENERGY
SYSTEM FOR ELECTRIC VEHICLES, BASED
ON ULTRACAPACITORS AND BUCK-BOOST
CONVERTER
MICAH E. ORTÚZAR
Members of the Committee:
JUAN W. DIXON
LUIS MORÁN
JOSÉ RODRIGUEZ
MARCELO GUARINI
BIMAL K. BOSE
RAFAEL RIDDELL
Thesis submitted to the Office of Research and Graduate Studies in partial
fulfillment of the requirements for the Degree of Doctor in Engineering
Sciences
Santiago de Chile, July, 2005
A mi Familia y mis amigos,
A todos los que me apoyaron.
AGRADECIMIENTOS
Después de más de cuatro años de trabajo y estudio son muchos los cambios, muchas las
experiencias vividas, profesional y personalmente. El apoyo de mi familia, desde distintos
lugares del mundo, ha sido fundamental, me ha ayudado en momentos críticos y hoy me
acompañan en este paso. A ellos, mi Papá, Mamá; a mis hermanos, a Margarita y Thomas,
a todos ellos muchas gracias.
Mis amigos han jugado un papel importante durante este período. Ellos han sido mi
segunda familia y un apoyo emocional imprescindible. Un cariñoso saludo a todos ellos.
También me siento profundamente agradecido de todos quienes me apoyaron al interior del
departamento de Ingeniería Eléctrica. Un agradecimiento especial a Eduardo Cea por su
ayuda y su amistad. Muchas gracias a Betty y Elena por su apoyo materno, gracias a
Virginia y Carlos por cuidar de nosotros. Gracias también a Nelson Saleh por su ayuda y
buena voluntad.
Una mención especial merece el profesor Juan Dixon y su familia por quienes me sentí
muy acogido. Juan se involucró a fondo en este proyecto y gracias a su empuje e iniciativa
hemos llegado a puerto. Todos los resultados y logros de este proyecto se deben, en gran
medida, a su iniciativa y su experiencia. También agradezco su amistad y comprensión a lo
largo de varios años en que hemos trabajado juntos. Un saludo especial para Juan.
CONTENTS
Pág.
TABLE INDEX............................................................................................................ 7
FIGURE INDEX .......................................................................................................... 8
RESUMEN................................................................................................................. 10
ABSTRACT ............................................................................................................... 12
I
II
INTRODUCTION ............................................................................................ 14
I.1
I.2
Electric and hybrid vehicles ..................................................................... 14
Integrating different energy systems ........................................................ 16
I.3
What are ultracapacitors and how do they work? .................................... 19
I.4
State-of-the-art traction systems using ultracapacitors ............................ 23
I.5
I.6
Objectives and hypothesis........................................................................ 27
Methodology ............................................................................................ 29
STATIC CONVERTER DESIGN AND IMPLEMENTATION ..................... 32
II.1 Introduction .............................................................................................. 32
II.2 Power design ............................................................................................ 35
II.2.1 Buck-boost topology...................................................................... 35
II.2.2 Static converter components design and selection ........................ 39
II.3 Safety features .......................................................................................... 45
II.4 Thermal design......................................................................................... 46
II.5 Mechanical design.................................................................................... 48
III
MONITORING AND CONTROL SYSTEM .................................................. 51
III.1 Introduction .............................................................................................. 51
III.2 Control algorithms.................................................................................... 51
III.3 Communication layout ............................................................................. 56
III.4 Implementation via DSP .......................................................................... 57
III.5 Real-time monitoring software................................................................. 58
III.6 Failure detection....................................................................................... 59
IV
URBAN CIRCUIT TESTS............................................................................... 60
IV.1 Introduction .............................................................................................. 60
IV.2 Test circuit................................................................................................ 60
IV.3 Tests results .............................................................................................. 61
V
RESULTS ANALYSIS .................................................................................... 65
V.1 Economic approach on results.................................................................. 65
V.2 Related researches .................................................................................... 68
V.3 General discussion.................................................................................... 70
VI
CONCLUSIONS .............................................................................................. 73
REFERENCES........................................................................................................... 75
A P P E N D I C E S................................................................................................... 82
Appendix A: Buck-Boost Converter Operation Analysis .......................................... 83
Appendix B: Disipated energy and heat generation in semiconductors..................... 86
Appendix C: Economic Evaluation Considerations................................................... 91
Appendix D: TMS320F241 DSP Controller, Texas Instruments .............................. 92
Appendix E: DSP code, Assembler Language........................................................... 94
7
TABLE INDEX
Pág.
TABLE 1-1: ENERGY DENSITY COMPARISON FOR GASOLINE AND DIFFERENT BATTERY
TYPES........................................................................................................................................15
TABLE 4-1. URBAN TESTS RESULTS SUMMARY. .................................................................................64
TABLE 5-1. TOTAL MEAN COSTS COMPARISON WITH BATTERIES AS THE MAIN ENERGY
SOURCE. ...................................................................................................................................66
TABLE 5-2. TOTAL MEAN COSTS COMPARISON WITH HYDROGEN + FUEL CELL AS THE MAIN
ENERGY SYSTEM. ..................................................................................................................68
TABLE B-1: INSTANTANEOUS POWER LOSSES WHILE CONDUCTING 150A IN
SEMICONDUCTORS. ..............................................................................................................88
TABLE B-2: MEAN POWER LOSSES WHILE CONDUCTING 150A IN SEMICONDUCTORS. ...........88
TABLE B-3: MEAN POWER LOSSES THROUGHOUT TIME, WHILE CYCLING 150 A CHARGE AND
DISCHARGE OPERATIONS FOR 19.09S WITHIN 1MIN PERIOD. ....................................89
TABLE B-4: WATER-COOLED HEAT-SINK’S REQUIRED THERMAL RESISTANCE TO ENSURE
TEMPERATURE COMPLIANCE FOR EACH SEMICONDUCTOR AND CASE................90
8
FIGURE INDEX
Pág.
FIGURE 1-1: POWER CIRCUITS OF TWO DIFFERENT HYBRID CONFIGURATIONS: A) PARALLEL
HYBRID; B) SERIAL HYBRID. ...........................................................................................18
FIGURE 1-2: PHYSIC PHENOMENA IN ELECTROSTATIC CAPACITORS, ELECTROLYTIC
CAPACITORS AND ULTRACAPACITORS (ELECTRONIC DLC), (MILLER AND
SMITH, 2004).........................................................................................................................20
FIGURE 1-3: RAGONE PLOT OF SPECIFIC ENERGY (WH/KG) VERSUS SPECIFIC POWER (W/KG)
FOR DIFFERENT ENERGY-STORAGE TECHNOLOGIES (EPCOS, 2001). ...................22
FIGURE 1-4: ELECTRIC VEHICLE, CONVERTED FROM A CONVENTIONAL ICE-POWERED PICKUP TRUCK CHEVROLET LUV. ..........................................................................................31
FIGURE 2-1: STATIC-CONVERTER-INTERFACED CONNECTION.......................................................33
FIGURE 2-2: EV POWER DEMAND PROFILE...........................................................................................34
FIGURE 2-3: BUCK-BOOST TOPOLOGY EQUIVALENT CIRCUIT........................................................36
FIGURE 2-4: BUCK OPERATION. ENERGY IS TRANSFERRED FROM THE BATTERY TO
ULTRACAPACITORS. .........................................................................................................37
FIGURE 2-5: BOOST OPERATION. ENERGY IS TRANSFERRED FROM ULTRACAPACITORS TO
THE BATTERY. ....................................................................................................................38
FIGURE 2-6: 2700F ULTRACAPACITOR FROM EPCOS. .........................................................................40
FIGURE 2-7: ULTRACAPACITOR BANK WITH CELL BALANCING UNITS INSTALLED.................41
FIGURE 2-8: INDUCTANCE DESIGN CONFIGURATION AND FINAL APPEARANCE. .....................42
FIGURE 2-9: 3300 UF ELECTROLYTIC FILTER CAPACITOR. ...............................................................43
FIGURE 2-10: PM400DSA060 FROM POWEREX.......................................................................................44
FIGURE 2-11: SNUBBERS CONNECTED TO SEMICONDUCTOR TERMINALS. .................................45
FIGURE 2-12: SAFETY ELEMENTS IN POWER CIRCUIT. ......................................................................46
FIGURE 2-13: THERMAL MODEL OF ONE IGBT-DIODE PAIR. ............................................................47
FIGURE 2-14: WATER-COOLED HEAT-SINK. ..........................................................................................48
FIGURE 2-15: COMPONENTS LAYOUT WITHIN STATIC CONVERTER. ............................................49
FIGURE 2-16: INSTALLED COMPONENTS IN CONVERTER CHASSIS................................................49
9
FIGURE 2-17: STATIC CONVERTER A) POWER CIRCUIT INSTALLATION, B) LOCATION IN
FRONT COMPARTMENT....................................................................................................50
FIGURE 3-1: HEURISTICS-SOC-CONTROL ALGORITHM AND SIGNALS MANIPULATION. ..........53
FIGURE 3-2: OPTIMAL CONTROL DATA GENERATION AND NEURAL NETWORK TRAINING
PROCESSES. .........................................................................................................................55
FIGURE 3-3: OPTIMAL-CONTROL ALGORITHM, IMPLEMENTED USING NEURAL NETWORKS.56
FIGURE 3-4: COMMUNICATION AND COMMAND FLOW DIAGRAM. ...............................................57
FIGURE 3-5: DSP CONTROL BOARD, SIGNALS AND DATA PORTS. ..................................................58
FIGURE 3-6: CONTROL AND DATA MONITORING/ACQUISITION SOFTWARE SCREENS. ...........58
FIGURE 4-1: URBAN CIRCUIT TEST COURSE.........................................................................................61
FIGURE 4-2: LOAD CURRENT AND BATTERY VOLTAGE WITHOUT AES’S POWER SUPPORT...62
FIGURE 4-3: CURRENTS AND BATTERY VOLTAGE FOR A POWER-SUPPORTED SYSTEM. ........63
10
PONTIFICIA UNIVERSIDAD CATOLICA DE CHILE
ESCUELA DE INGENIERIA
DEPARTAMENTO DE INGENIERÍA ELÉCTRICA
DISEÑO, IMPLEMENTACIÓN Y EVALUACIÓN DE UN SISTEMA AUXILIAR
DE ENERGÍA PARA VEHÍCULOS ELÉCTRICOS, BASADO EN
ULTRACAPACITORES Y CONVERTIDOR BUCK-BOOST
Tesis enviada a la Dirección de Investigación y Postgrado en cumplimiento parcial de
los requisitos para el grado de Doctor en Ciencias de la Ingeniería.
MICAH E. ORTÚZAR
RESUMEN
El trabajo expuesto en esta tesis explora los factores clave que impiden a los vehículos
eléctricos ser ampliamente aceptados en los mercados de transporte público y privado. En
particular, se analizan las limitaciones que presentan los sistemas de almacenaje de energía
para entregar altas potencias durante la aceleración o recibirlas durante el frenado. Para
resolver estos problemas de potencia se propone la combinación de elementos de alta
potencia específica con elementos de alta energía específica. En este contexto se ha
diseñado, implementado y evaluado un Sistema Auxiliar de Potencia (SAP), basado en
ultracapacitores y un convertidor Buck-Boost para ser usado en combinación con baterías
de plomo-ácido. Los procesos de diseño e implementación se describen en detalle; también
se presentan los resultados del proceso de evaluación. Finalmente se complementa la
discusión de los resultados con un análisis desde el punto de vista económico de la
implementación de este tipo de sistemas.
La falta de elementos de almacenaje de energía eléctrica que presenten, simultáneamente,
alta potencia específica y alta energía específica, y los altos costos de estos equipos, se
consideran los mayores obstáculos para introducir vehículos de cero emisiones en los
mercados de transporte público y privado. La combinación de elementos de alta energía
específica, como celdas de combustible o baterías avanzadas, con elementos de alta
11
potencia específica, como los ultracapacitores, se presenta como la solución más viable
para solucionar los problemas de baja autonomía y/o desempeño deficiente en el corto
plazo.
El SAP propuesto, basado en ultracapacitores y convertidor buck-boost, se ha diseñado e
implementado en un vehículo eléctrico a escala real en combinación con baterías de
plomo-ácido. Los procesos de diseño e implementación, así como el período de pruebas y
sus resultados, se describen en detalle.
Los resultados de la evaluación muestran que, con el SAE instalado y operando en el
vehículo, la potencia disponible ha aumentado de 40 kW a 85 kW. Se han evaluado dos
algoritmos de administración de energía, uno basado en heurística y el otro basado en
técnicas de control óptimo aplicado a redes neuronales; el rendimiento del vehículo
(km/kWh) aumentó en un 5.2% y un 8.9% con el primer y segundo algoritmo,
respectivamente. Del análisis económico se concluyó que, si se consideran los costos
solamente, con el sistema propuesto se requeriría que la vida útil de la batería se extendiese
en un 50% o más para compensar los costos del SAE.
Para mejorar la autonomía y para realizar, en el futuro, nuevos análisis al sistema
desarrollado, se ha instalado una batería de Na/Ni-Cl2 (conocida comercialmente como
batería ZEBRA) en reemplazo de las baterías de plomo-ácido.
Members of the Doctoral Thesis Committee:
JUAN W. DIXON
LUIS MORÁN
JOSÉ RODRÍGUEZ
MARCELO GUARINI
BIMAL K. BOSE
RAFAEL RIDDELL
Santiago, July, 2005
12
PONTIFICIA UNIVERSIDAD CATOLICA DE CHILE
ESCUELA DE INGENIERIA
DEPARTAMENTO DE INGENIERÍA ELÉCTRICA
DESIGN, IMPLEMENTATION AND EVALUATION OF AN AUXILIARY
ENERGY SYSTEM FOR ELECTRIC VEHICLES, BASED ON
ULTRACAPACITORS AND BUCK-BOOST CONVERTER
Thesis submitted to the Office of Research and Graduate Studies in partial
fulfillment of the requirements for the Degree of Doctor in Engineering Sciences by
MICAH E. ORTÚZAR
ABSTRACT
This thesis addresses key issues that prevent electric vehicles from being broadly adopted
by private and public transportation markets. In particular, the limitations of energy storage
devices to deliver energy at high power rates during acceleration and accept high power
regeneration during braking are analyzed. To solve available power problems, the
combination of a high specific-power storage device with a high specific-energy storage
device is proposed. Accordingly, an Auxiliary Energy System (AES), based on
ultracapacitors and a buck-boost converter, has been designed, implemented and evaluated
in an electric vehicle. The system’s design and implementation are described; also an
evaluation process and its outcomes are presented. Finally, an economic approach is
applied to the general discussion on obtained results.
The lack of a single energy storage element that presents, simultaneously, high specific
power and high specific energy for electric vehicles, and the high cost of these devices, are
identified as the main obstacles to successfully introduce zero-emission vehicles to public
and private transport markets. The combination of high specific-energy storage devices or
elements, such as advanced batteries or hydrogen (through Fuel Cells), with high specific
power storage devices, such as ultracapacitors, is presented as the most viable solution to
the problems of low autonomy and/or poor performance in the short term.
13
The proposed AES, based on ultracapacitors and a buck-boost static converter, has been
designed and implemented in an electric vehicle in combination with lead acid batteries
energy storage. The design and implementation processes of the proposed system are
described in detail.
Evaluation results demonstrated that, with the AES installed in the vehicle, available
power was increased from 40 kW to 85 kW. Two energy management algorithms were
evaluated, one based on heuristics and the other one based on optimal control techniques
applied to neural networks; the vehicle’s yield (km/kWh) was increased in 5.2% and 8.9%
with the first and second algorithms, respectively. Economic analysis concluded that, in
terms of costs only, with the proposed system a battery life extension of 50% would be
needed to compensate for the AES’s costs.
For better autonomy and to perform developments in the future on the integrated system, a
Na/Ni-Cl2 battery (commercially know as ZEBRA battery) has been installed in exchange
for the lead-acid battery.
Members of the Doctoral Thesis Committee:
JUAN W. DIXON
LUIS MORÁN
JOSÉ RODRÍGUEZ
MARCELO GUARINI
BIMAL K. BOSE
RAFAEL RIDDELL
Santiago, July, 2005
14
I
INTRODUCTION
I.1
Electric and hybrid vehicles
In the early days of the automotive era, around the end of the 19th century and
beginning of the 20th century, electric-powered and internal-combustion-enginepowered vehicles not only offered comparable performance characteristics, but also,
electric vehicles where more reliable and safe. Accordingly, the first known
automotive-hire service in the US (the Electric Carriage & Wagon Company,
established on 1897) was served by electric vehicles (Kirsch, 1996). However,
because of the low power and low autonomy (inability to run long distances without
recharging) presented by electric vehicles (EV), this early advantage ended quickly
when design improvements performed on internal combustion engines (ICE) made
them reliable enough to be competitive. While a series of unfortunate events and final
bankruptcy buried the EC&WC’s future, the scarce autonomy EVs presented plus
governing technical and economical conditions in the early 20th century resulted in
the general adoption of ICE-powered vehicles in the US and worldwide.
During the fourth quarter of the 20th century and due to several circumstances, such
as the oil crisis, environmental issues and technological breakthroughs, the effort to
develop viable EVs regained strength. Power electronics technology advances during
the ‘70s, and subsequent improvements in the ‘80s, gave birth to new efficient and
powerful inverters, which made viable the use of AC motors, which are simpler,
more efficient and with more specific power than the classic DC motor. In addition,
around the late ’80s the brushless DC motor, invented in 1962 by T.G Wilson and
P.H Trickey (Wilson and Trickey, 1962), was improved and made competitive. This
machine, a version of the synchronous motor in which permanent magnets in the
rotor establish the excitation field, behaves as a DC motor when adequate electronic
control is applied. Hence, it incorporates the DC motor’s advantage of high torque at
low speeds, but also incorporates the advantage of AC-motor’s simplicity and high
specific power, while achieving an excellent dynamic behavior.
15
These advances dissipated doubts about efficiency and specific power in EVs.
Nevertheless, EVs continued to be a poor competitor to ICE-powered vehicles,
mainly due to the reduced capacity of energy storage devices (compared to specific
energy in fossil fuels). This handicap, even though still present to date, has been
constantly reduced due to technological advances (new battery technologies, fuel
cells, etc.). Nowadays, electric propulsion systems efficiency rates are much higher,
surpassing 80% (Eaves and Eaves, 2004), against a typical of around 18% for
conventional gas engines (Fueleconomy, 2005) and 35-40% for modern Diesel
engines in urban drive conditions. Still, energy density (Wh/l) and specific energy
(Wh/kg) is considerably higher in fossil fuels than in most advanced batteries (API,
1988; Chan and Wong, 2004). This is shown in table 1-1.
Table 1-1: Energy density comparison for gasoline and different battery types.
97 Octane
Gasoline
Batteries
Lead-Acid
Energy Density
[Wh/Lt]
9,662
60-90
Specific Energy
[Wh/Kg]
12,146
30-45
NiMH
Li-ion
130-170 140-200
60-70
90-130
ZEBRA
Zn/Air
186
269
118
230
These facts imply that, in vehicles of similar characteristics, the useful energy content
in a gasoline tank is several times higher than that contained in an advanced battery
pack of comparable weight and dimensions, which translates to lower autonomy for
EVs. For example, a 30-liter gas tank can deliver 52 kWh of useful energy to the
wheels (accounting for ICE loses); on the other hand, a 100-kg Li-ion battery can
deliver 12 kWh to the wheels, almost 1/5th of the energy delivered by gasoline
weighting over 3 times more.
16
The aforementioned issue plus the problem of high initial cost and low specific
power of most batteries conform the main obstacles to successfully introduce
competitive EVs to the public and private transport industry.
A comprehensive solution would require the development of more advanced
batteries, achievable only through major research breakthroughs and investment in
new technologies, or the integration of fossil-fuel energy-storage and electric power
conversion and management (higher efficiency, lower noise, lower maintenance costs
and lower environmental impact).
The second scheme may achieve higher autonomy than pure EVs and higher
efficiency than regular ICE-powered vehicles but, in order to reach maximum
efficiency and minimum emissions, the main energy transformer (Diesel or gas
engine, gas turbine, fuel cell, etc.) must work at its optimum power output which will
contrast with the variable power requirements of the vehicle. Also, to reach its
potential, the system should be able to recover energy from braking, which fossilbased energy-storage systems cannot do. Therefore, the integration of these
dissimilar energy conversion mechanisms require a temporary auxiliary-energystorage device; in such a way the vehicle is able to recover, and reuse, energy from
braking, and the main energy transformer (ICE, gas turbine, FC, etc.) is dimensioned
to satisfy mean (not peak) power demand, reducing the acquisition cost. These
auxiliary energy storage devices should have high power density, high specific power
and high efficiency. Vehicles that use such a combination of different energy storage
devices are commonly known as hybrid systems.
I.2
Integrating different energy systems
Recent commercial debut of hybrid vehicles is a proof of the improved efficiency and
performance of electric powered vehicles, regardless of the original source of energy
(electricity, gasoline, natural gas, hydrogen, etc.). Nevertheless, in terms of power-toweight ratio and cost, new hybrid models still do not strongly compete with
traditional gasoline or diesel-powered vehicles; moreover, although hybrids’ yield
(km/lt) is usually higher than most gas-powered vehicles, it is comparable to that of
some diesel models. Also, the use of combustion engines and complicated gearboxes
17
surely influences cost and weight. On the other hand, power is an issue that must be
resolved using appropriate auxiliary energy sources to support peak power
requirements. Therefore, all new topologies that could offer improvements in terms
of cost, weight and power should be explored and tested by researchers. In
accordance, the project presented here studies the technical and economical viability
of a seldom-explored hybrid configuration: the combination of batteries and
ultracapacitors.
At this stage, it is convenient to define different types of hybrids and the energy
sources they use or could use.
a) Parallel hybrid: is the combination in parallel of two different energy sources, both
with independent mechanical outputs that are combined in a special gearbox to
deliver or accept energy from the wheels (Fig. 1-A). This topology has been applied
in most commercial models; it usually combines an internal combustion engine and
an electric motor, which is connected to an electrochemical storage device, such as
batteries.
b) Serial hybrid: both energy sources deliver energy to the power train through the
same electro-mechanical converter (an electric motor), to which they are electrically
connected in parallel, as shown in Fig. 1-B. In this case, any two sources that deliver
electrical energy could be used, as long as they are compatible in terms of electrical
variables. This topology is also the only possible when the main energy source is a
battery or hydrogen (through Fuel Cell), because (unlike ICE) they do not produce
mechanical power.
18
AESU
Traction
Motor
Gearbox
A)
Power
Inverter
+
Auxiliary
Energy
Storage Unit
-
Internal
Combustion
Engine
Gasoline or Diesel
tank
MESU
MESU
B)
Traction
Motor
+
+
-
-
Power
Inverter
Main Energy Storage Unit
(Batteries, Fuel Cell, Gas
turbine, Diesel Engine , etc.)
Auxiliary
Energy
Storage Unit
AESU
Figure 1-1: Power circuits of two different hybrid configurations: A) Parallel
hybrid; B) Serial hybrid.
The two (or more) energy sources involved in the hybrid configuration can be
differentiated by their capability of storing energy and delivering power. A source of
high energy density serves for an extended driving range and may be called the Main
Energy System, because a vehicle could eventually run long distances powered by
this source only, even though the power and/or efficiency characteristics could be
poor. A powerful and efficient reversible source is the best compliment to the above
mentioned and may be called the Auxiliary Energy System, because a vehicle
running with this kind of source would perform well and efficiently but only for a
few miles; thus, it depends on the previous one for medium and extended-range
applications.
19
For the Main Energy System (MES), the most popular and proven choice has been
the internal combustion engine (ICE), followed by the gas turbine and, lately, the
Fuel Cell (FC). For the Auxiliary Energy System (AES), the most mentioned
candidates are high power batteries, ultracapacitors and flywheels, of which only the
first two are commercially available. All of these AES offer high efficiency, high
power-density and reversibility (Rutquist, 2002).
Because an ICE’s natural output is mechanical power (at manageable speeds for
gearboxes) and any unnecessary energy transformation is undesirable, it is usually
applied in parallel configuration. For the gas turbine, and most other candidates for
main energy sources, such as FCs, primary and secondary batteries, the series
configuration is more suitable. Recent developments in the areas of FCs and batteries
(Zinc-Air, ZEBRA, etc.) suggest a good chance of being a competitive alternative to
the ICE for Main Energy System in the near future (DOE, 2003), using series hybrid
configuration.
The two commercially available storage-device alternatives to implement the AES
are advanced batteries and ultracapacitors. Of these, the second present several
advantages over batteries for this particular application. The higher specific power
and higher efficiency are the most notable; but also, the longer cycle life and no
maintenance characteristics translate conveniently into no-replacement-cost and
lower-service-cost (Mazaika and Schulte, 2005).
These facts motivated the research described in this thesis, regarding the
development of an Auxiliary Energy System (AES) based on ultracapacitors and a
static converter. This AES has been conceived to be used in series hybrid
configurations (Jeong et al, 2002) in combination with different main energy systems.
I.3
What are ultracapacitors and how do they work?
Electronic double layer capacitors, DLC, or ultracapacitors, were first developed and
patented in 1961 by SOHIO. The construction of an ultracapacitor consists of a pair
of metal foil electrodes, each of which has an activated carbon (AC) fiber mat
deposited on metal foil. The activated carbon side of each electrode is separated by
an electronic barrier such as glass paper then sandwiched or rolled into a package. An
20
aqueous or organic electrolyte salt impregnates the activated carbon as shown in
Figure 1-2. The electronic properties of an ultracapacitor are strongly dependent on
the porosity of the activated carbon and on the molecular size of the electrolyte ions.
Activated carbon electrodes used in ultracapacitors have specific surface areas of
1000 to 2300 m2/g and charge separation distances, d in Figure 1-2, on the order of
10 Angstrom or less (Miller and Smith, 2004).
Figure 1-2: Physic phenomena in electrostatic capacitors, electrolytic capacitors
and ultracapacitors (electronic DLC), (Miller and Smith, 2004).
The electrostatic capacitor is generally constructed of metal films, ceramic, or glass,
mica or other dielectric material. The electrostatic capacitor in Figure 1-2 consists of
two metal electrodes separated by a dielectric of thickness d. A potential across the
two metal electrodes creates a uniform electric field in the insulating medium the
properties of which determine the voltage rating (Miller and Smith, 2004).
An electrolytic capacitor is similar to the electrostatic unit in construction except for
the presence of a conductive electrolytic salt that is in direct contact with the metal
current collector, or cathode. The anode is made from an etched metal foil that has
been anodized by application of an electric potential when the foil is immersed in an
electrolyte during manufacture. An electrolyte different from the forming electrolyte
21
is used as the ionic conductor. When the formed anode foil with its alumina dielectric
layer is rolled up along with the cathode foil, an insulating separator such as Kraft
paper is placed on the outside of the anode foil to insulate it. The negative foil is
typically the outside of the electrolytic can.
When an external potential is applied across the electrolyte terminals, a uniform
electric field is established across the anodized layer of alumina while a decaying
electric field exists some distance, δx, into the electrolyte according to Poisson’s
equation. Because of the presence of an electric field that extends into the electrolyte,
this capacitor will have a more limited breakdown voltage than an electrostatic
capacitor. Electrolytic capacitor manufacturers design for breakdown voltages
somewhat above the surge rating of the unit. Typically, higher surge rated electrolytic
capacitors also have higher resistance, hence a higher equivalent series resistance,
ESR, and therefore higher losses in power electronic circuits. Another consequence
of an electric field in the electrolyte is the fact that capacitor current is now a function
of both voltage change and capacitance change as a function of voltage (Miller and
Smith, 2004).
The voltage rating of ultracapacitors is constrained by the same phenomena of
electric field presence within the electrolyte as in conventional metal foil electrolytic
capacitors. Ultracapacitors with organic electrolytes have voltage ratings of <3.0 V
per cell whereas with aqueous electrolytes the voltage rating drops to <1.23 V per
cell, typically 0.9 V. In all ultracapacitors the terminal capacitance consists of the
series combination of an anode DLC and the cathode DLC, so the net rated voltage is
twice the value of the electrolyte decomposition voltage. Organic electrolyte
ultracapacitors have higher decomposition voltages and higher specific energy but
higher resistance than aqueous types. Low conductivity of organic-electrolyteultracapacitors results in higher ESR. ESR can be reduced in general by the addition
of vapor grown carbon fiber to the AC.
Because capacitance is proportional to the electrodes surface-area and inversely
proportional to charge separation distance d, ultracapacitors advantage conventional
capacitors, such as electrolytic and electrostatic capacitors, by their porous-ACelectrodes enormous effective areas and the extremely small charge separation
22
distance (Miller and Smith, 2004). The drawback, despite their two capacitive layers
instead of one, is the limited maximum voltage ultracapacitors withstand, usually
between 2.3V and 2.8V.
Ultracapacitors have greater specific power (more than 1.5kW/kg) than conventional
or advanced batteries; and higher specific energy (of about 3 to 5 Wh/kg) than
aluminum electrolytic capacitors (Dietrich, 2001; Burke and Miller, 2002). Their
advantage over batteries, in terms of power, is due to their reduced equivalent series
resistance (ESR) and that in these elements, unlike batteries, there are no chemical
reactions involved in the process of charge and discharge. Therefore, the speed
needed to deliver energy does not depend on the speed of such reactions or the ability
of chemical components to recombine, but on electrostatic phenomena, which does
not require molecular mutation to take place. Also, the longer cycle life and good
behavior at low temperatures (Schneuwly and Smith, 2005) are important
advantages.
Figure 1-3 shows how ultracapacitors close the gap between batteries and electrolytic
capacitors in terms of specific power and energy.
Figure 1-3: Ragone plot of specific energy (Wh/kg) versus specific power (W/kg)
for different energy-storage technologies (EPCOS, 2001).
23
Because they present low losses and high cycle life at high power demands, these
elements of recent development cover a wide field of uses in power engineering
applications, especially in schemes with high peak power demand and medium-low
energy requirements (Cohen and Smith, 2002). Consequently, they present
advantages for complementary use in electric vehicles (EVs) and hybrid electric
vehicles (HEV), especially in their energy storage systems.
Accordingly, there are an increasing number of studies in which ultracapacitors are
used as a complement of the main energy system (ICE, FC, batteries, etc.) in hybrid
vehicles.
I.4
State-of-the-art traction systems using ultracapacitors
Contents of this section show the bibliography analysis made during the thesisproject formulation period. Works reviewed in this process served as a knowledge
base of the up-to-date developments in Auxiliary Energy System using
ultracapacitors and their results. All publications discussed in this section are
contemporary or previous to the project formulation. Works published thereafter, as
well as publications presenting this project’s results, are discussed in chapter V.
Publications regarding ultracapacitors and auxiliary energy storage may be classified
in three groups: i) the ultracapacitor industry reports and surveys, which deal with
new material fabrication processes, specific characteristics measurements and testing
under different operating conditions; ii) the speculative kind, whose approach is
focused in forecasting long term industry trends and suggesting certain technology
adoption for the particular application (analysis and conclusions presented in these
essays are based on inference and experience acquired within the industry); iii)
finally, a third group presents technical reports on practical applications, which
expose useful data about behavior and performance obtained from experimental
prototypes (or rigorous simulations using real data sets). Publications within this last
group describe the state-of-the-art power topologies for EVs and HEVs, therefore an
updated analysis on viability of these schemes can be extracted from them.
The first group of publications presents studies that describe the state of the industry
and its projections (Cohen and Smith, 2002). Production-models characteristics and
24
behavior under stress (and abuse) are measured to evaluate adequacy for different
applications (Jehoulet et al, 2000; Varakin et al, 2001; Goesmann et al, 2002; Conte
and Pirker, 2005). Projected future materials improvements and costs are also
forecasted, based on research’s preliminary results and suggested technology
inversions (Burke and Miller, 2001). Most of these works are presented by
ultracapacitor manufacturers, a fact that could suggest questionable objectiveness, but
data contained in them should be reliable because they are subject to the industry
scrutiny and benchmarking. The most useful information contained in these
publications is related to behavior under abuse and safety considerations (Goesmann
et al, 2002; Conte and Pirker, 2005).
The second group of publications could be considered the vanguard analysis that may
inspire future developments. Even though they lack real-life experimental results,
these works are a sample of the engineering analysis process preliminary to any
serious innovative attempt (Furubayashi et al, 2000; Mitsui et al, 2002; Dixon et al,
2000).
The third classification group, consisting of practical applications reports, comprises
most publications on ultracapacitors to be found. There is a wide variety of explored
topologies and the analysis scope spread over an ample spectrum of profoundness.
Miscellaneous applications from peripheral-load power-support (Folchert et al, 2002)
to ultracapacitors-as-the-single-energy-source configurations (Barrade and Rufer,
2001) can be found. There are several reports on HEVs implementations using
ultracapacitors in combination with non-reversible energy sources such as ICEs, FCs
and primary batteries among others (Furubayashi et al, 2000; Burke and Miller 2001;
Di Napoli et al, 2001; Lott and Späth, 2001; Varakin et al, 2001; Jeong et al, 2002;
Okamura, 2002). A couple of publications describing idle stop systems were found
(Furubayashi et al, 2001; Mitsui et al, 2002); this application consists of using
ultracapacitors in urban buses to power the starter motor of ICEs, which are turned
off at every stop to avoid inefficient and contaminating idling conditions. In these
cases, ultracapacitors are used to avoid battery deterioration due to successive peak
power episodes and to decouple this strongly-perturbing load from other on-board
electronic loads. Finally, there is a constantly-growing number of reports that present
25
HEV implementations combining ultracapacitors as Auxiliary-Energy-Systems and
different types of batteries as Main-Energy-Systems (Arnet and Haines, 2000; Härri
and Egger, 2001; Heinemann et al, 2001; Wight et al, 2001; Wight et al, 2002). These
works conformed the most valuable and updated information source when this
project was elaborated, because they expose practical details and evaluation results of
the early experimental implementations on the topology being evaluated in this
research. A thorough review of the highlights of each publication found in this subgroup is presented in the following pages.
Arnet (Arnet and Haines, 2000) presents the hardware and algorithm concepts used in
the implementation of an AES based on ultracapacitors to be implemented in an
electric vehicle using lead-acid batteries as MES. This design was part of Solectria
Corporation’s new energy storage devices development program. The static converter
used in his design has a Buck-Boost topology, such as the one used in the project
presented in this thesis. He also used algorithms that establish an inverse relation
between the vehicle’s kinetic energy and the ultracapacitor’s state of charge (SOC).
This work is contemporary with the first publication that emanated from this project
(Dixon et al, 2000), in which general hardware configuration and algorithm concepts
were presented; coincidently, Arnet’s general approach is very similar to that
exposed in (Dixon et al, 2000), therefore early conclusions on the feasibility of this
implementation could have been extracted from his findings, but his results were
preliminary and did not evaluate the general performance of the equipment in reallife operation. Also, some differences appeared in hardware design and algorithm
implementation, hence Arnet’s work and this project results could complement eachother.
Härri (Härri and Egger, 2001) introduces an energy scheme concept he calls SAM
(Super Accumulator Module), which consists on combining batteries and
ultracapacitors using a topology he refers to as Virtual Parallel (VP). But the actual
semiconductor configuration is not at all clear, nor is under what criterion the
different operation modes are selected and the capacitor SOC controlled. Test results
and performance data are not presented either. Therefore, this essay does not provide
useful orienting insights.
26
Heinemann’s work (Heinemann et al, 2001) is interesting because of exposed
temperature management data and ultracapacitor behavior under different operation
conditions. Also, his exploration of different energy management strategies presents
interesting alternatives. Nevertheless, his findings are mostly simulations or small
scale bench tests, and do not deliver conclusive data about the overall efficiency
increase and/or available power.
By 2002, Wight’s publications (Wight et al, 2001; Wight et al, 2002) had the most
illustrative results on ultracapacitors and lead-acid batteries combination for EVs.
Data presented in both works summarize test procedures on real-life-scale vehicles
using the static converter developed by Arnet and two different ultracapacitor brands,
one in each publication. The first study shows a complete set of tests comprising
urban, suburban, acceleration and dynamometer experiments on two identical
vehicles, both equipped with lead-acid batteries as MES, the first one using the
ultracapacitor-based AES and the second one (control subject), which did not have an
AES. General conclusions showed that, when using that particular ultracapacitorbased AES, more available power was observed by the driver, acceleration was faster
and more energy could be extracted from the batteries before reaching the
“discharged” threshold minimum voltage (which allowed some increased autonomy).
Nevertheless, even though more energy was extracted from the batteries, in most
experiments the overall efficiency or yield (km/Wh) was lower on the vehicle
equipped with the AES. The second essay shows almost identical tests but using a
different ultracapacitor brand. Results resemble very much those obtained in the first
publication; the amount of energy extracted from batteries in the vehicle equipped
with the AES was greater in all tests than that extracted from batteries in the control
vehicle. This time the results on efficiency where non-conclusive.
From available literature, at the time of the research project-formulation, it could be
concluded that there was scarce experience of this kind of application and few reallife-scale tests had been performed. Results obtained by Wight suggested that the use
of a high-specific-power AES, like the one proposed in this research, would lessen
main battery deterioration due to the reduction of peak power demanded and
therefore, would probably extend battery life. On the other hand, Wight’s results
27
were not conclusive regarding overall efficiency impact that the use of this AES
produced on EVs; there is a chance that efficiency results from his tests could have
been influenced by the algorithm structure or its parameters and/or by the efficiency
characteristics of his particular static converter.
This reasoning suggested that, by incorporating an ultracapacitor-based AES to EVs,
in addition to battery life extension and a better acceleration response, overall
increase in vehicle efficiency could be achieved if improvements where performed on
static-converter design and energy-management algorithm structure.
I.5
Objectives and hypothesis
The central objective of this research is to identify and improve some of the
deficiencies that prevent clean and efficient transport technologies, such as EVs, from
successfully competing against traditional pure-ICE-based vehicles. This objective
has been partially realized in previous analysis, identifying obstacles such as reduced
autonomy, high cost and limited power of EVs and HEVs as the predominant barriers
to achieve competitive clean vehicles.
Reduced autonomy is a characteristic of pure EVs, which are powered with reduced
energy-density electrochemical batteries. This problem has been partially overcome
with the development of HEVs, equipped with Main Energy System (MES) of higher
specific energy. Nevertheless, some of the energy converters used in these
configurations are not as clean or efficient as it would be desirable, as in the case of
Internal Combustion Engines (ICEs) and Fuel Cells (FCs) (Galliers, 2003).
The problem of high cost, common to all clean mobility solutions, is particularly
pronounced in the case of FCs, for which forecasts are not optimistic in the short and
medium terms (Galliers, 2003; Chan and Wong, 2004). In the case of ICEs, although
actual costs are not prohibitive, simple reasoning concludes that their complexity
makes them expensive to maintain. Furthermore, if battery technologies are
consistently improved and acceptable energy densities are achieved, it is not
unreasonable to speculate that manufacturing costs of an electrochemical storage unit
with fewer and simpler components could be lower than those of an intricate ICE. Of
course complex manufacturing of special alloys and compounds have to be perfected
28
and made cheaper, but that is not impossible given the rate at which manufacturing
processes are advancing. Hence, electrochemical batteries seem to be the alternative
clean-energy-source that could first break the barrier of unacceptable costs and
consistently bring them to competitive levels.
The power issue is also prevalent in all technologies previously reviewed. In the case
of HEVs efficiency considerations make it transcendental that their MES’s work at
constant or near-constant power levels, lower than the peak power demanded; also,
cost constraints force the MES’s power-rating reduction to levels near mean power
demand. This leaves the burden of power on the AES, whose duty is to quickly
deliver or accept bursts of energy as a response to the power-train’s demands. The
first elements used for AES implementations were high power batteries, but these
require sophisticated charge equalization management (Schneuwly and Smith, 2005)
and present a short cycle life, which had an impact in cost; that is why new energystorage elements such as ultracapacitors and flywheels are being tested and
implemented in HEVs to address high power issues. In the case of battery-powered
pure EVs, batteries present varied problems, such as low specific power, DODdependant cycle life (Mazaika and Schulte, 2005), inefficiency at high power
demands, etc. This has motivated the experimentation of different technology
combinations to satisfy separate energy and power needs. This is particularly
important when primary batteries (such as Zn-air) or high-specific-energy but lowspecific-power batteries (such as Na/Ni-Cl2 or ZEBRA) are used; in the case of these
battery technologies, very promising in terms of specific energy, power support is
fundamental.
From this analysis it can be deduced that, in the medium term, the clean transport
technology that will most certainly reduce its costs is battery electrochemical storage.
Of which some chemistries have lately achieved important specific-energy
improvements. Therefore, an efficient, cost-effective and reliable power support unit
could close the circle and make battery-powered EVs a competitive choice in the near
future.
This reasoning has motivated the development of an ultracapacitor-based AES to be
implemented in a lead-acid battery-powered vehicle. The lead-acid technology would
29
be subsequently changed to Na/Ni-Cl2 (ZEBRA) of greater energy density and lower
power density.
The incorporation of this power support system would certainly increase available
power, but it also raises obvious concerns about costs. On the other hand, a question
regarding other EVs limitations arise: would this system have a negative effect on
efficiency and therefore on autonomy? In this author’s opinion, no, on the contrary:
the reduction of maximum power demanded to the battery would increase battery
operation efficiency and more energy would be recovered from regenerative braking
even when the battery is fully charged; this would more than compensate for the
expected losses produced in the static converter interfacing energy flow to and from
ultracapacitors. If this reasoning proves correct, then costs could also be
compensated, or even reduced, as a result of energy savings and battery life
extension.
This expectation, founded on intuitive reasoning, could be formulated as a hypothesis
to be demonstrated.
“The adequate use of ultracapacitor-based Auxiliary-Energy-System in electric
vehicles powered with lead-acid batteries, under congested city driving conditions,
increases total energetic efficiency and extends its autonomy. That is, in driving
conditions with a high number of stops and accelerations respective to the covered
distance, the total energy spent (per kilometer) will be measurably lower in a leadacid battery equipped vehicle that uses a ultracapacitor-based AES than that spent in
the same vehicle without the AES. The AES-equipped vehicle would also be able to
cover a longer distance with one charge.”
The demonstration or refutation of this hypothesis will be the central aim of this
thesis. A discussion on costs will also be included in the final analysis, but does not
fall within the preset scope of this study.
I.6
Methodology
To demonstrate, or refute, the proposed hypothesis, a real-life scale AES prototype
using ultracapacitors and a static converter was designed and constructed. The system
was implemented in an EV and tested in an urban drive circuit. Finally, results were
30
analyzed and compared to those obtained without the use of the AES, leading to final
conclusions, from which economical implications where drawn.
The AES design and implementation were key processes to ensure the success of this
project. The ease of power flow control, operational safety and overall system
efficiency, depended directly on the adequacy of the power topology, as well as the
thorough study and design of converter components and control system. A BuckBoost power topology was used, where the ultracapacitor bank was connected at the
low voltage side of the converter, allowing bi-directional power flow with variable
voltage at the ultracapacitor terminals. The specially designed and constructed
smoothing inductor (of 1.6 mH) and water-cooled heat-sink allowed high efficiency
and high power rating by ensuring low amplitude ripple current and stable thermal
management. A control and monitoring system was also designed and implemented
using a DSP from Texas Instruments. This system allowed the implementation of
different energy management strategies without hardware modification and provided
real time information through its monitoring and data-logging features.
The electric vehicle used in this work, was transformed from a conventional
Chevrolet “LUV” truck, shown in Figure 1-4, which is similar in weight and shape to
a Chevrolet S-10; its drive train is powered by a Brushless DC traction motor (32
KW nominal power and 53 KW maximum power) and a 54 kW inverter (Dixon et al,
2000). The vehicle’s main energy system was formed by a pack of 26 lead-acid
batteries connected in series (356 Vdc), which has been recently replaced with a
ZEBRA (Zero Emission Battery Research Activity) battery (371 Vdc). The Auxiliary
Energy System was implemented with a 20-Farad ultracapacitor bank and a BuckBoost converter, with a nominal voltage of 300 Vdc, and a nominal current of 200
Adc.
31
Figure 1-4: Electric vehicle, converted from a conventional ICE-powered pick-up
truck Chevrolet LUV.
The test circuit was a slow and mid-speed driving urban route. Special care was taken
to perform tests under similar environmental and technical conditions, such as
ambient temperature, traffic conditions, tire pressure, etc.
Tests were performed without regeneration, with battery-only-regeneration and with
AES-assisted regeneration (two algorithms were tested). Available power (kW) and
yield (km/kWh) were the measured performance indicators.
32
II
STATIC CONVERTER DESIGN AND IMPLEMENTATION
II.1 Introduction
The battery pack, composed of 26 series-connected lead-acid batteries, has a no-load
voltage that ranges from 358V, when recently charged, to 312V when discharged.
This voltage is also load-dependant, reaching under 250V when heavily loaded and in
low SOC condition. On the other hand, it can reach more than 400V when it has been
recently charged and regenerative braking is applied. These are extreme conditions
which not only deteriorate batteries and shorten their life, but may also damage
power inverter (traction equipment has minimum and maximum voltage limits of 250
and 400 V respectively). This situation cannot be avoided unless the vehicle’s drive
train power is restricted according to battery voltage. This strategy would avoid
inverter damage and could help preserve batteries longer, but would severely affect
vehicle performance and efficiency (by restricting power and regeneration); it would
limit available power when batteries are partially discharged and, over time, batteries
aging would also noticeably affect performance. In other words, batteries would go
through a long agony and this would be reflected in vehicle performance. This is
where the Auxiliary Energy System fills the gap.
As previously defined, the most adequate hybrid configuration to be implemented in
a battery-powered EV is a series-hybrid topology, shown in Figure 1-1B. Even
though it is called ‘serial’ hybrid (because of the serial mechanical output), the Main
and Auxiliary Energy Systems are connected in parallel. Therefore, if the Main
Energy System (batteries) remains the same, the AES must be designed in such a way
that it adapts to the pre-established power-circuit voltage-rating, and there is an
adequate supporting-power-flow during peak power demand.
Even though there have been some experiences connecting ultracapacitors directly to
the Main Energy System (Jeon et al, 2005; Massé and Freeman 2005), a static
converter should interface power connection between batteries and ultracapacitors for
several reasons, but three are fundamental. First, batteries work at relatively constant
voltage levels while capacitor’s voltage is directly related to their SOC, therefore to
33
use all or most energy storage capacity of ultracapacitors a voltage interface is
required. Second, the only way to implement different energy management strategies
is by controlling power flow and SOC of at least one of the energy source units, and
this can only be done by placing a static converter between the two sources. Third,
directly connected capacitors will only support power demand during transients,
being useless for more prolonged high power episodes. Thus, EV’s power circuit will
be configured as shown in Figure 2-1.
MESU
+
Traction
Motor
+
Power
Inverter
Lead-Acid Batteries
-
-
Static
Converter
Ultracap .
Bank
AESU
Figure 2-1: Static-converter-interfaced connection.
Given the vehicle’s drive train power rating of 53kW and mean power consumption
under 10kW in urban drive conditions, it would be desirable to install an Auxiliary
Energy System with a power rating over 40kW. Even though the battery can deliver
power above mean demand value (which, by the way, is a very relative value) a static
converter with power rating in the order of 40kW will ensure power support under
any condition, as long as there is energy left in the ultracapacitor bank. The topology
and design of this power converter will be addressed later.
Intuition would suggest that the Main Energy System, batteries in this case, should
deliver mean power consumed by the vehicle and the AES would complement it to
satisfy instantaneous vehicle power demand. Accordingly, the ultracapacitor-bank’s
energy storage capability should be large enough to store as much energy as that
34
integrated between the mean power and real power consumption lines in a typical EV
power profile such as the one shown in Figure 2-2, which was obtained from an
experimental EV in urban driving conditions.
Urban Vehicle Power Profile
40
30
Power [kW]
20
10
Inst. Consumed Power
0
Mean Consumed Power
-10
30
40
50
60
70
80
-20
-30
Time [s]
Figure 2-2: EV power demand profile.
The problem with this reasoning is that power consumed by a vehicle is a stochastic
process whose mean value is not the same all the time (Mazaika and Schulte, 2005).
That is, a vehicle running in suburban mid-speed traffic one day and in congested
downtown traffic the next day will have different mean power consumed values.
Which one is the ‘real’ mean power? Both actually, because there is no single mean
power for a vehicle and this value depends on the situation to which it is inserted.
Therefore, the MES cannot be dimensioned for ‘one’ mean power value and the AES
for the remaining energy. It follows that the design of a vehicle’s power system
cannot aim to have the AES available in every condition, because in particular
situations, such as long hill climbing, it would have to contain great amounts of
energy not to be depleted after prolonged high power demands. Similarly, the MES
cannot be dimensioned to deliver a reduced-average-like power, because, if left to
power the whole system alone, it has to perform acceptably. Hence, the AES cannot
be considered an always-available system, and it is a matter of trade-offs to install a
35
small, cheap, seldom-available system, or a big, expensive, always-available power
source. The idea is to have the system available ‘most’ of the time at a ‘reasonable’
cost. Both of which are relative concepts but that is the nature of consumer products.
These concepts were incorporated when dimensioning the system, but because of the
experimental nature of this system, costs were not the priority constraint.
To have an idea of the amount of energy the vehicle will use in a single powerdemanding operation, acceleration and hill climbing (the most demanding tasks in
terms of power) energy requirements are the best examples. The vehicle in question
plus its Auxiliary Energy System weighs around 2000 kg. Therefore its kinetic
energy at 60 kph is about 77 Wh. This amount of energy plus losses will be spent to
accelerate from 0 kph to 60 kph. If a constant speed over a hill climb of 30 m height
difference is desired, an approximate amount of 163 Wh (potential energy difference)
plus air drag and mechanical losses will be spent. Considering these figures, the AES
was designed to store enough energy to consecutively support power during both
tasks. Thus the ultracapacitor bank has a 255 Wh energy-storage-capacity, of which
only 90 % would be used because of efficiency concerns. This allows sustained
power support during most demanding regular tasks in city driving conditions.
II.2 Power design
Terminal voltage in a capacitor bank, by definition depends directly on its state of
charge (SOC). More precisely, the ultracapacitor-bank’s SOC is proportional to its
square voltage; hence, as energy is transferred to and from the bank its voltage will
change accordingly. For this reason, the static converter topology, shown in Figure 21, must be able to transfer energy between a relatively constant voltage source
(battery) and a variable voltage source (ultracapacitor).
II.2.1 Buck-boost topology
The above mentioned characteristics of the static converter call for a power topology
that adapts to the variable nature of capacitor voltage and the relatively constant
battery voltage. For this reason a buck-boost topology was chosen. Figure 2-3 shows
an equivalent circuit of the power circuit in which the battery is represented by a
36
voltage source and an internal resistance. The ultracapacitor bank is also represented
by a voltage source (which, for short periods of time, it is) and its equivalent series
resistance (ESR). This topology is conceived to establish controlled bidirectional
power transfer between both sources as long as ultracapacitor voltage VU is smaller
than battery voltage VB. If this condition does not hold, a current will flow through
diode D2.
Battery
iBAT
iC
Rint
T2
D2
+
+
VC
LS
ultracapacitor
bank
iU
C
ESR
VB
T1
Buck Side
D1
VS
+
VU
Boost Side
Figure 2-3: Buck-boost topology equivalent circuit.
During ‘buck’ operation, energy goes from battery to ultracapacitor. This task is
performed by commutating semiconductor T2 at a frequency f (period T) and duty
cycle δ. This operation is shown in Figure 2-4, where it is clear how current iC
through semiconductor T2 has strong discontinuities. Capacitor C acts as a filter so
the battery sees a smoother continuous current.
37
iU
T= 1/f
iBAT
iC
iC
T2
δ
VB
iU
D1
VU
iBAT
Time
Figure 2-4: Buck operation. Energy is transferred from the battery to
ultracapacitors.
In buck operation, mean currents through battery i BAT and through ultracapacitors iU
behave like in a DC transformer (where a=δ) and may be calculated accordingly, as
long as δ ≥ VU VB . This is applied in equations 2.1 and 2.2.
i BAT
iU =
VU 

VB −

δ 

=
 ESR

 2 + R int 
 δ

(VB ⋅ δ − VU )
(ESR + R int⋅ δ )
2
(2.1)
(2.2)
During ‘boost’ operation, energy goes from ultracapacitor to battery pack. This
operation is very similar to the one previously described. Semiconductor T1 is
commutated at a frequency f and a duty cycle δ. Figure 2-5 shows this operation and
current waveforms. As before, strong discontinuities are present in current iC which,
again are filtered by capacitor C.
38
iU
T= 1/f
i BAT
iC
iC
D2
δ
VB
T1
iU
VU
iBAT
Time
Figure 2-5: Boost operation. Energy is transferred from ultracapacitors to the
battery.
Once again, mean currents i BAT and iU can be analyzed like in a DC transformer,
where the turns ratio is 1/ (1 − δ ) , as long as (1 − δ ) ≥ VU VB . This has been applied
in equations 2.3 and 2.4.
i BAT
 VU


− VB 
(1 − δ )

= 

ESR 
 R int +


(1 − δ )2 

(2.3)
iU =
(VU − VB ⋅ (1 − δ ))
(R int⋅ (1 − δ )2 + ESR )
(2.4)
Ultracapacitor current ripple amplitude is an important design variable, because
mechanical vibrations, induced-current-losses and undesirable EMI could be
produced if special care is not taken. Expression 2.5 shows the maximum ripple
amplitude as a function of VC, f and LS (calculated in Appendix A).
iU _ max_ ripple =
VC
4 ⋅ f ⋅ Ls
(2.5)
39
II.2.2 Static converter components design and selection
The converter was designed and tested to deliver up to 60 kW, but current was
limited to 150A on the ultracapacitors side to avoid high losses. Hence, the converter
can deliver a peak power of 45 kW, which decreases with ultracapacitor voltage,
reaching 30 kW at ultracapacitor voltage of 200 V (which is seldom lower).
According to this power rate and interconnected systems, buck-boost converter
components were selected or designed to work properly at currents up to 200A and
voltages up to 400V.
a) Ultracapacitor bank
Battery voltage can decrease to levels below 250V on heavy loads (when working in
battery-only mode), but usually stays over 300V when a regular load is applied. With
AES power-support this voltage decreases, at the most, to 300V on full load.
Therefore, to avoid voltage crossing, the ultracapacitor bank maximum voltage rating
was set to 295 V.
The AES was implemented with 132 series-connected ultracapacitors. These units
have 2700 Farads each, an ESR of 1 mOhm and a voltage rating of 2.3 V. The bank
totals 20.45 Farads, an equivalent series resistance of 132 mOhm, and a total
maximum voltage of 303.6 V (limited by software to 295 V). Figure 2-6 illustrates
one ultracapacitor and its physical characteristics.
40
Figure 2-6: 2700F ultracapacitor from Epcos.
Due to slight differences in capacitance, ultracapacitors may charge unevenly and
some units may eventually overcharge. To avoid this, dissipative voltage limiters
were installed in each unit as shown in Figure 2-7.
41
Figure 2-7: Ultracapacitor bank with cell balancing units installed.
b) Smoothing inductance LS
For the smoothing inductance design, maximum current ripple amplitude of 5A was
the aim. Therefore, according to expression 2.5 and considering a 12 kHz
commutation frequency and a battery voltage of 360 V, the inductance LS should
have at least 1.5 mH. It also should be able to conduct currents up to 200A without
saturating and/or generating excessive resistive losses.
After pondering the electromagnetic relations between material saturation, coresection area and core-length, number of turns and final achieved inductance, an aircore design was implemented, because it would not saturate and the high reluctance
could be compensated with more turns, of lower volume and weight ‘cost’ than the
other core alternatives required (Ortúzar, 2002).
42
For the winding conductor was fabricated from a 12 cm wide, 0.5 mm thick
laminated aluminum sheet was used, to cope with skin effect.
Figure 2-8 shows the inductance design schematic and final appearance. Its
theoretical inductance value was calculated at 1.37 mH, but the measured inductance
was 1.6 mH, this increase was due to larger core section-area produced by packaging
elements.
Figure 2-8: inductance design configuration and final appearance.
This inductance weighed 22 kg, which was reasonable considering another
implementation in which an inductance of only 27 uH and more than 40kg weight
was designed (Arnet and Haines, 2000) using a continuous-gap powdered composite
pot-core.
c) Converter capacitor C
The inclusion of capacitor C as a low-impedance voltage-source near the converter
semiconductor has two main purposes: first, prevent dangerous voltage surges in
semiconductor terminals due to parasitic inductance and high di/dt; and second, filter
currents between the battery and buck-boost converter.
Surge voltage levels depend on parasitic inductance value, 7.5 uH in this case,
current level and battery voltage level. In this case, energy contained in this parasitic
inductance at maximum rated current calls for low capacitor values below 20 uF.
43
Current filtering between battery and converter called for larger capacitance values
than those required for voltage surge prevention. Nevertheless capacitor value cannot
be excessively large because of dynamic response delays introduced by LC circuit
formed by this capacitor and smoothing inductance LS. Finally, because of its good
simulated behavior, a 3300 uF electrolytic capacitor, shown in figure 2-9, was
installed to perform current filtration and voltage surge control, both of which were
properly achieved.
Figure 2-9: 3300 uF electrolytic filter capacitor.
d) Semiconductor
Given the converter’s commutation-frequency, power and voltage requirements, an
IGBT technology semiconductor was selected to operate the static converter. An
Intellimod (IGBT with integrated gating circuits), model PM400DSA060 from
Powerex, with maximum voltage rating of 600V and 400A current capability was
chosen. The electronic device, shown in Figure 2-10, also has integrated over-current
and over-voltage protections.
44
Figure 2-10: PM400DSA060 from Powerex.
e) Snubbers
As mentioned above, parasitic inductance in conductors between battery and static
converters may produce voltage surges due to high di/dt during commutations, which
is prevented by installing capacitor C. Nevertheless, capacitor C and conductors to
IGBT also have non-negligible parasitic inductances, which may also produce
voltage surges; thus snubber nets are installed directly at semiconductor terminals
and conductors to IGBT are made of laminated-cooper for better performance.
In this case, two different snubbers were installed: one single (low-parasiticinductance) capacitor and, in parallel, a diode-capacitor-resistor combination (to
avoid destructive currents through IGBT and possible oscillations). Figure 2-11
shows the snubber nets and their connections.
45
Dumped capacitordiode snubber
Capacitor snubber
Figure 2-11: Snubbers connected to semiconductor terminals.
II.3 Safety features
A series of hardware and software safety measures were implemented to prevent
malfunction and/or dangerous situations. Software measures are mainly failure
detection capabilities, which are described further on.
The equipment was hardware-protected by fuses on each side of the static converter
and a diode to allow boost discharge, preventing capacitor C overcharge if the fuse
on the battery side blows. Figure 2-12 shows these safety elements installed in the
power circuit.
46
MESU
+
Traction
Motor
+
Power
Inverter
Lead-Acid Batteries
-
-
Static
Converter
Ultracap .
Bank
AESU
Figure 2-12: Safety elements in Power circuit.
II.4 Thermal design
Due to weight and size constraints, thermal considerations for a good heat-sink
design were required. Like any other power electronic device, the static converter
must dispose of its energy losses before they buildup temperature inside the
semiconductor package. To determine the required heat-sink’s thermal-resistance a
thermal model was elaborated. This model, representing both IGBT-diode pairs, is
shown in Figure 2-13.
47
INTELLIMOD PM400DSA060
PQ1
TjQ
Rth(j-c)Q
PF1
TjF
Rth(j-c)F
Tc
Rth(c-f)
PQ2
TjQ
Tf
Rth(f-amb)
Tamb
Rth(j-c)Q
PF2
TjF
Rth(j-c)F
Figure 2-13: Thermal model of one IGBT-diode pair.
Expressions 2.6, 2.7 and 2.8 describe temperatures behavior in relation to the
semiconductors dissipated power. Conduction plus commutation losses in IGBT and
conduction losses in diode are referred to as PQ and PF, respectively. These values
will depend on instantaneous current, voltage drop across juncture and on duty cycle.
Tc = Tamb + (Rth ( c− f ) + Rth ( f −amb ) )⋅ (PQ + PF )
(2.6)
T jQ = Tamb + (Rth ( c − f ) + Rth ( f −amb ) )⋅ (PQ + PF ) + Rth ( j −c )Q ⋅ PQ
(2.7)
T j F = Tamb + (Rth ( c − f ) + Rth ( f −amb ) )⋅ (PQ + PF ) + Rth ( j −c )F ⋅ PF
(2.8)
To obtain operating conditions on a worst-case scenario, power losses were
calculated for an intensive charge-discharge cycle. The simulated operation consisted
on a discharge from 290V to 150V at maximum allowed current and a consecutive
charge in the same conditions once every minute (details in Appendix C). Total mean
losses were calculated at 257 W, while maximum instantaneous power losses were of
412.4 W.
48
Individual semiconductor mean power losses and thermal characteristics provided by
the manufacturer (Appendix D) were applied to the thermal model mentioned above.
The required heat-sink’s thermal resistance was calculated to maintain junctures and
case temperatures below maximum levels for the evaluated operation conditions. The
required thermal resistance for the heat-sink is of 0.107 ºC/W.
Because no satisfactory alternative was found on the market, a two-piece machinedaluminum heat-sink was designed and constructed. The design schematic and
disassembled prototype are shown in Figure 2-14.
Figure 2-14: Water-cooled heat-sink.
The theoretical thermal resistance for this heat-sink was calculated (Ortúzar, 2002) at
0.01023 ºC/W, much lower than required leaving a broad margin for possible higher
dissipated power.
II.5 Mechanical design
Considering the high power levels this converter would manage and the severe
conditions it would work under, mechanical design and construction standards should
be the highest. Therefore, these tasks were carefully planned and several tests were
performed before final installation. Figure 2-15 shows the projected layout before
construction.
49
uProcessor and control
circuit box.
Snnubers
INTELLIMOD
Power connectors to
ultracapacitor bank
Capacitor C
Current LEM
Fuse F1
Positive terminal to
battery
Heat-sink
Water circuit pipes.
Negative Terminal to
battery
Figure 2-15: Components layout within static converter.
Laminated conductors and placed components within the converter chassis are shown
in Figure 2-16. Also snubbers connected directly to the semiconductor terminals are
visible.
Laminated
conductors
Control
circuits
Snubbers
Intellimod
Heat-sink
Figure 2-16: Installed components in converter chassis.
50
Some of the converter’s power connections and water circuit fitting are shown in
Figure 2-17A. The location on top of the traction inverter allowed installing short
power cables and water-cooling circuit hoses. Figure 2-17B shows the buck-boost
converter with its cover, located in the front compartment under the hood.
A)
B)
Figure 2-17: Static converter A) power circuit installation, B) location in front
compartment.
51
III
MONITORING AND CONTROL SYSTEM
III.1 Introduction
In addition to power-circuit design and assembly, several guidelines were established
regarding the monitoring and control system-requirements to ensure controllable
behavior, safety, ease of debugging and means to evaluate performance.
The implemented energy management algorithms would determine the AES behavior
under different situations and, consequently, the system adequacy to different driving
conditions. Such an algorithm for an AES like this one should ensure two basic
conditions: 1) to provide power support to the traction system on most probable
driving conditions (prioritary rule); and 2) the long term State of Charge (SOC)
convergence (i.e. to have stored energy for accelerations and space to store it after
braking). At the same time the implemented algorithm should provide both
conditions with the highest possible efficiency. These challenges were addressed by
implementing and testing two different energy management algorithms, the first one
based on heuristics and the second one based on the offline optimization of power
flows for known conditions and the training of Neural Networks (NN) to apply this
experience on a real-time basis.
To allow for easy implementation of these and other energy-management-algorithms,
a basic structure or shell was designed, over which algorithms would be programmed
to manipulate high-level variables. Within this shell, a series of low-level functions
are performed, such as ultracapacitor-current-control, voltage-driven current-limiting
(to prevent ultracapacitor overcharge), failure detection and diagnosis, and usercontrol of low level variables for debugging, among others. This structure consists of
a combination of hardware and software elements, which will be detailed in this
section.
III.2 Control algorithms
The control algorithms to be implemented and evaluated were programmed in the
DSP using specially-defined high-level variables. These algorithms could use and
52
manipulate acquired variables such as motor speed and power, battery voltage and
SOC, and system temperature among others. The output these algorithms delivered
was the ultracapacitor current-reference, which would then be processed by the lowlevel control loop and final PWM command signals would be delivered to the IGBT
power module.
Two different algorithms were implemented and evaluated. The aim was to compare
performance and energy efficiency of an intuitive heuristics-based algorithm to those
achieved by an optimal-control-based algorithm. Both energy management strategies
were programmed above the low-level control shell and data was acquired using the
monitoring program.
a) Heuristic-based energy management algorithm.
The first implemented algorithm was based on the notion that long term vehicle
energy behavior can be compared to an energy pendulum, where on one side there is
electrical energy ready to swing the pendulum to the kinetic energy side and return.
This pendulum obviously has losses but these can be supplied by the Main Energy
System (the battery) while fast energy swings can be managed by the Auxiliary
Energy System. This reasoning did not take into account energy variation due to a
change in the vehicle’s altitude position but resembles energy behavior for most
situations in city driving. The mentioned heuristic is designed to prepare
ultracapacitors (with energy to deliver or space to store it) for the next most probable
situation, i.e. deliver power when vehicle is stopped and receive it when vehicle is
driving at high speeds. Therefore, it is a reaction to the present situation and serves
for long-term convergence of ultracapacitor SOC. But for the immediate future a
short-term-oriented rule was included: a software-defined battery-current limit, which
operates delivering the required balance current to maintain battery current within
established values (as long as there is energy in the ultracapacitors to deliver, or
space to store it). These features complement each other. One reacts to speed changes
and establishes a new SOC reference for the ultracapacitors accordingly. The second
(with priority over the first one) reacts to instantaneous power level changes and
maintains battery working inside pre-defined boundaries.
53
Figure 3-1 shows a schematic of the first strategy implementation. In this picture
several low-level tasks have been omitted for simplicity. Algorithm-related tasks are
ain dri
ve
inside the light-brown area.
and m
Buck-Boost
Converter
Ultracapacitor
Bank
PWM
Battery
Motor
Control Unit
V UCAP
LEM
I Ucap
-
PI
Real Current
System Current
Voltage
protection
Speed
P erson
al
Comp
uter
Batt. State of charge
Ah
Counter
2
()
PI
Speed - UcapSOC
Charge ref.
+
-
Real charge
Batt Voltage
Current reference
+
RS 232
Flash Mem.
TMS320F241
Figure 3-1: Heuristics-SOC-control algorithm and signals manipulation.
The system showed excellent performance with this algorithm. Battery power was
effectively limited and during non-demanding periods the AES used the opportunity
to adjust ultracapacitor’s SOC to be ready for the next power-demanding episode.
These two operations were complementary and did not pull the system’s SOC in
different directions.
b) Optimal control energy management algorithm.
Even though the first implemented algorithm performed more than acceptably, there
was still no certainty about the efficiency of energy management. Therefore, a second
54
algorithm was designed and programmed by a master’s degree program student, as
part of the same research project (Moreno et al, 2004). This algorithm was based on
the application of optimal control techniques to determine the optimal power support
for a real-life power-demand-profile.
The optimal control process consisted on calculating (offline) the optimal powersupport for real power demand data series. To do this, thirty power-demand data
series were recorded while driving an EV on urban driving conditions. For each of
these data series a power support sequence that would minimize the energy extracted
from the battery was found; this is the power support that, if delivered by an AES,
would maximize the system efficiency for that driving sequence. An efficiency
model of the drive system and the AES was used to implement the cost function. A
constraint that forced the ultracapacitors’ state of charge at the end of the exercise to
be the same than that at the beginning of it ensured optimization consistency. The
power demand data series, together with the corresponding optimal power support
data series, were used as the knowledge base to train a Neural Network (NN) offline.
The NN would then apply the learned information to determine the power support on
real-life experiments, to do this the NN would imitate optimal control behavior on
situations similar to those optimized before. Figure 3-2 illustrates the optimal control
data generation process and how that information is used to train the NN.
55
Data
Data Logging Process
Batts. only
Power
10100
11100
11110
10010
11101
11100
00010
Speed
00110
01000
00001
00101
01010
00001
01010
Voltage ...
10100
11110
00110
01000
01010
11101
10010
Iterations
Optimal Control
Process (eficiency
model)
Application of learned information
Batts. + AES
Optimal Power Support data
Power
10100
11100
11110
10010
11101
11100
00010
Speed
00110
01000
00001
00101
01010
00001
01010
Voltage Power - support
10100
00110
11110
00001
00110
00101
01000
01010
01010
00001
11101
11110
10010
11101
Neural Network
Training
Figure 3-2: Optimal Control data generation and Neural Network training
processes.
During offline optimal control path calculation, results obtained presented a mean
calculated efficiency increase of 5% compared to that obtained with the simulated
operation of the SOC-control-algorithm (illustrated in Figure 3-1). This predicted a
positive change in vehicle efficiency using the new optimal-control algorithm.
Thirty different power demand series, with calculated optimal power-support data,
were used on the NN training process. The Levenberg–Marquardt training algorithm
was used. Of the 30 data series, 10 were used for NN training and the remaining 20
for validation. The validation indicator used was the mean square error. To define
optimal net architecture, ‘prunning’ algorithms were used (the Optimal Brain
Surgeon algorithm in particular). Figure 3-3 illustrates interaction of trained NN with
the DSP variables to implement optimal control algorithm.
56
LEM
Motor
Control Unit
PWM
Battery an
Ultracapacitor Bank
I Ucap
-
PI
V UCAP
d main dr
ive
Buck-Boost
Converter
Actual Current
Batt. Voltage
Load Current
Voltage
Protection
Speed
Person
a
Comp l
uter
Batt SOC
Ah
counter
RS 232
Flash Mem.
Current Reference
+
Neural Network
Iload(k)
Iload(k-1)
Pload(k)
Pload(k-1)
V(k)
V(k-1)
E(k)
E(k-1)
Bias(+1)
Bias(+1)
TMS320F241
Figure 3-3: Optimal-control algorithm, implemented using neural networks.
The trained NN presented excellent replication of optimal behavior learned during
the training process. This was verified after training by comparing the power-support
output from the NN to the optimal output of one validation data series.
III.3 Communication layout
The basic shell mentioned above consists of a hardware command-andcommunication layout, which is managed by a central microprocessor. A low-level
routine, programmed in this microprocessor, allows implementation of dataacquisition functions, a communication protocol and the basic current control loop.
The command and communication layout is illustrated in Figure 3-4.
Ultracapacitor
Bank
LEM
Motor
Control Unit
PWM
Batt e
ry
Buck-Boost
Converter
I Ucap
V UCAP
and m
ain dr
ive
57
l
P ersona
ter
C ompu
RS 232
Batt Voltage
Motor Current
Speed
Control Circuit Board
Flash Mem.
Batt. State of charge
Ah
Counter
Figure 3-4: Communication and command flow diagram.
III.4 Implementation via DSP
The command and communication layout was implemented in a power-electronicsoriented DSP, the TMS320F240 from Texas instruments. This microprocessor was
installed in a specially designed circuit board that included signal conditioning for
data acquisition, an external flash memory to store user-manageable controlparameters, communication ports and command signal ports.
The board with DSP and associated circuitry is illustrated in Figure 3-5.
58
Figure 3-5: DSP control board, signals and data ports.
III.5 Real-time monitoring software
Given the need, and special aim of this work, to acquire and analyze power system
behavior data, special monitoring and acquisition software was programmed in
Visual Basic. The definition of a DSP-PC communication protocol and the simplicity
of programming in this environment allowed implementing a satisfactory real-time
monitoring feature, while monitored data could be stored for further analysis. Figure
3-6 illustrates the main control screen and a data monitoring screen.
Figure 3-6: Control and data monitoring/acquisition software screens.
59
The screen on the left shows and allows modification of user-controllable parameters.
Data monitoring and low-level control can be commanded from this window too. The
screen on the right shows monitored data in a real-time sliding-chart.
III.6 Failure detection
This feature was designed with the double purpose of preventing dangerous
conditions and facilitating the debugging process. The failure detection operates as a
software routine that interrupts operation when an abnormal condition is detected.
Three abnormal condition types are sensed: battery-side fuse blown, failure signal
received from IGBT module and communication interrupted while operating in PCsupervised mode. In all cases gating operations are disabled and failure information is
displayed in the monitoring software’s main control screen (if connected). Operations
will remain disabled until re-enabled by user with monitoring software. The last
failure cause is always stored and displayed on the main control screen.
60
IV
URBAN CIRCUIT TESTS
IV.1 Introduction
Once all supporting parts of the system (power and control) were tested and ready,
the evaluation process was prepared. The goal was to determine and quantify the
improvements in vehicle performance due to the use of the AES. This assessment
would be used to determine the technical and economic contribution of this kind of
equipment to pure electric vehicles and the possible application to hybrid vehicles.
The performance indicators to be evaluated were: available power (kW) and yield
(km/kWh), with and without the aid of this particular AES. Therefore, a protocol to
measure these variables was established.
During tests, the monitoring system logged and stored variables such as vehicle
speed, battery and ultracapacitor voltage, power demanded by motor and power
delivered by AES among others. Of more than 40 tests, 23 where performed
measuring total energy used (as seen from the charger) in four different conditions:
without regeneration, with battery-only regeneration and with AES-assisted
regeneration using both described algorithms.
Every test was performed with identical tire pressure, at the same time of the day and
over a period of one month to ensure relatively identical conditions. The driver plus
one passenger rode on tests when the AES was out of action, but an extra passenger
was included when this power support system was used to emulate the AES’s extra
weight.
IV.2 Test circuit
Because this system is conceived to support power mainly during acceleration and
braking periods, its application is naturally directed to urban driving. Hence, a 14 km
urban-drive circuit was established as the standard measure. The circuit has a slow
driving portion (inside university campus) and a faster one but with stops every one
to two hundred meters. The stops where introduced to simulate congested urban
driving conditions. Most stops were dummy traffic jams, which were actually marks
61
on a map where identical stops had been programmed for every test. The
approximate mean speed was of 18 km/h, with maximum speeds of 60 km/h. Figure
4-1 illustrates the map of the test course.
0m
100m
200m
300m
Figure 4-1: Urban circuit test course.
IV.3 Tests results
The general driving appreciation was that available power had noticeably increased,
allowing fast accelerations, even when batteries were deeply discharged. This can be
corroborated by analyzing data plots obtained with the monitoring system. Figure 4-2
illustrates normal load currents for a urban drive and corresponding battery voltage
when no power support is applied.
62
160
Current [A]
120
80
I_Load
40
0
463
-40
483
503
523
543
563
583
603
Voltage [V]
-80
350
340
330
320
310
300
290
280
463
V_Batt
483
503
523
543
563
583
603
Time [s]
Figure 4-2: Load current and battery voltage without AES’s power support.
In this case, battery current is the same as load current. The clearest sign of how
power affects battery is the voltage depression during high current demands. Here
battery voltage reaches 280V at 140A current output.
On the other hand, when power support is enabled, battery current never surpasses its
maximum allowed value (40A in this case), while system voltage-regulation is
reinforced. This sign of increased available power can be appreciated in Figure 4-3.
63
160
Current [A]
120
80
I_Load
I_AESU
I_Batt
40
0
162
-40
182
202
222
242
262
Voltage [V]
-80
350
340
330
320
310
300
290
280
162
V_Batt
182
202
222
242
262
Time [s]
Figure 4-3: Currents and battery voltage for a power-supported system.
When the AES supplies power support, battery power output is limited to around 12
kW. This is done by supplying the balance demanded current. In this way battery
does not “see” peak demanded power but values near mean demanded power.
Negative power is also limited to a fixed value around -3 kW; this value is
automatically manipulated by software when it detects battery voltage rising to
prevent gassing, which is especially useful when batteries have been recently
charged. In this plot this feature can be observed when battery voltage approaches
340 V.
The motor-drive controller, a microprocessor provided by the drive manufacturer,
disables power when battery voltage decreases under 250 V. This generally occurred
to battery-alone configuration when demanded current surpassed 160 A, but never
occurred with AES-supported system. From this, battery available power may be
calculated at around 40 kW. The AES-supported system has nominal power of 45
kW+12 kW from battery, but up to 85 kW in total could be delivered if required, by
using all 40 kW form battery.
64
The vehicle’s yield (km/kWh) was calculated with measured run kilometers and
recharging-energy spent after every test. The spent energy was that measured at the
charger, thus it accounted for total energy, including charging losses.
This indicator was measured under four different conditions: batteries-only without
regeneration, batteries-only with regeneration, AES-power-assisted with SOC control
algorithm, and finally AES-power-assisted with optimal control algorithm.
Table 4-1 shows these results, in which yield (km/kWh) improvements are calculated
in comparison to the batteries-only with regeneration case.
Table 4-1. Urban tests results summary.
Drive City
Circuit (km)
kWh Used
Ah Used
km/kWh
km/kWh
Improvement
Batteries without
Regeneration
14.2
5.45
13.90
2.61
-
Batteries with Regeneration
14.2
4.61
11.23
3.09
-
Batteries with AES (SOC
Control)
14.2
4.36
10.55
3.25
5.2%
Batteries with AES (Optimal
Neural Network Control)
14.2
4.24
10.58
3.36
8.9%
65
V
RESULTS ANALYSIS
V.1 Economic approach on results
An AES, installed in a lead-acid battery powered vehicle, produces, as shown in
previous chapters, an improvement in maximum power rating and vehicle autonomy.
These facts would probably extend the battery life due to reduction in maximum
power demanded. These results imply performance and cost-reduction benefits,
which can be measured to calculate the cost-benefit relation of this equipment and
therefore, the feasibility of including it in future EV configurations. Nevertheless,
performance and/or comfort improvements are hard to evaluate in terms of added
value in a market that is virtually non-existent. Therefore, a cost-benefit analysis will
be presented including only cost-related benefits generated by this equipment. This
analysis will be made in terms of total mean costs $/km of an EV powered with leadacid batteries and compared to the same vehicle using an ultracapacitor-based AES,
as the one described herein.
To obtain the total mean cost ($/km) of a vehicle, all present and future costs must be
calculated and added using a discount rate representing the capital cost and risks
throughout time. The result represents the present value (PV) of all costs, which can
also be expressed as a monthly payment throughout the vehicle’s lifetime using the
same discount rate. This payment divided by the amount of kilometers run per month
will represent the total mean cost ($/km) of the vehicle. This analysis will be
performed over a lifetime of 12 years.
The costs considered are: the ‘core’ (vehicle’s chassis, power train and accessories1);
original
and
replacement
batteries
throughout
vehicle’s
lifetime2;
AES
(ultracapacitors3 + static converter4); cost of spent energy5, annual maintenance6 and
the residual value7 at the end of the period analyzed (notes in Appendix C). Electric
energy prices are forecasted values calculated by the Energy Information
Administration (EIA, 2005).
The base case is the aforementioned test vehicle, powered from 26 lead-acid
batteries. This case is compared to the same vehicle with the AES installed for peak
66
power support. For the evaluated alternative two different assumptions were explored
for the increase in battery life, first a rather optimistic 50% extended life and second
a more realistic 20% extended life.
Table 5-1 illustrates all of these costs and the corresponding present value and total
average cost for each case analyzed.
Table 5-1. Total mean costs comparison with batteries as the main energy source.
Component
Vehicle
Batteries Only
(1)
(2)
Bateries
(3)
(4)
Ucaps + static converter
(5)
Total cost of energy
(6)
Maintenance
(7)
Residual value
PV of total costs
(8)
Total average cost ($/km)
Cost change percentage
Batteries (50%+) + Ucaps
Batteries (20%+) + Ucaps
$ 8,000
$ 16,181
$ 8,000
$ 11,595
$ 8,000
$ 13,897
$0
$ 3,288
$ 2,856
$ 5,160
$ 3,024
$ 2,856
$ 5,160
$ 3,024
$ 2,856
-$ 450
-$ 724
-$ 578
$ 29,874
$ 29,910
$ 32,358
$ 0.191
$ 0.192
$ 0.207
0.1%
8.3%
-
Total average costs calculated for each case show that AES’s convenience is relative
to the battery life extension it produces. If batteries last 50% longer (an optimistic
hypothetic scenario) with the AES working, the total mean cost is almost the same as
the cost of the vehicle working on batteries only; therefore, in this case, battery life
savings are high enough to compensate for the AES’s cost. On the other hand, if
batteries last 20% more cycles (a more realistic scenario), then the total mean costs
are 8.3% higher for the vehicle equipped with the AES. Hence, in terms of costs only,
the system described in this paper would only justify its inclusion in a lead-acid
battery equipped vehicle if battery life extension is equal or higher than 50%. If
customer satisfaction is included in the analysis, then more accurate data about
battery life extension would be needed to evaluate the convenience of the system. In
the case when battery life is extended by 20%, customer satisfaction would have to
be high enough to justify an increase in total costs of approximately 8%.
Nevertheless, the added complexity of the whole system plus the higher component
count could increase failure probability and/or maintenance costs. These facts, as
67
well as the influence of costumer satisfaction are hard to measure in a market (EV’s
market) where there is scant experience regarding component failure and costumer
acceptance.
Continuing the research project’s line of investigation, oriented to evaluate feasible
vehicles for the short and medium terms, it is interesting to evaluate the integration of
other promising battery technologies for MES and the AES presented herein.
Therefore a new EV configuration, that combines a ZEBRA (Na/Ni-Cl2) battery
MES and the same ultracapacitor-based AES, has been implemented for evaluation.
That experience does not fall within the scope of this thesis; therefore its outcome
will be presented and analyzed in other instances within the near future. At the
moment of this thesis redaction, the newly configured vehicle was undergoing
preliminary tests and being prepared to perform efficiency and power evaluations on
it.
Regarding long term aimed EVs, a probable scenario to consider is that in which
fuel-cell powered vehicles are adopted by automakers and the industry. For this
analysis, three power configurations are evaluated: the vehicle powered by fuel cells
only, fuel cells plus Li-ion batteries and fuel cells plus ultracapacitors. The efficiency
for a fuel cell vehicle (running on gas hydrogen from electrolysis) from the power
grid to the wheels, can be derived from the composition of typical efficiencies of all
conversion processes involved: electrolysis (72 %), fuel cell (54 %) and electric drive
train (89 %), with a total integrated efficiency of 34 % (Eaves and Eaves, 2004). The
yield achieved by the wheel-to-road conversion was assumed at 8 km/kWh,
equivalent to running 300 miles with 60 kWh coming out of the wheels (Eaves and
Eaves, 2004); therefore an integrated yield (power-grid to wheels) for a fuel-cell
only vehicle was calculated at 2.72 km/kWh. An extra 18 % yield was considered for
the fuel cell plus batteries configuration (because of regeneration savings), and a 24
% of extra yield was attributed to the configuration running on fuel cells and
ultracapacitors. These numbers were obtained from experience acquired while testing
the AES with and without regeneration.
Costs in Table 5-2 clearly illustrate how fuel cells represent an important percentage
in the cost structure, and therefore a small fuel cell drastically reduces mean costs,
68
which can be seen in the case of combination with batteries or ultracapacitors. The
use of a much smaller fuel cell (20 kW in combination cases) is compensated by the
power support from batteries or ultracapacitors during peak power demand; however,
this cannot be sustained for a long time due to the limited amount of energy stored in
these devices. Hence, the use of combination configurations would limit the amount
of continuous time allowed to drive at maximum power, making it unsuitable for
sustained high speeds or hill climbing. Nevertheless, these configurations equipped
with an AES such as the one described in this thesis could still perform more than
well in urban conditions and even on highways at reasonable speeds (assuming good
aerodynamics), and the mean cost is drastically reduced in almost equal amounts of
33.7 % and 31.7 % for combinations with ultracapacitors and batteries, respectively.
Table 5-2. Total mean costs comparison with Hydrogen + Fuel Cell as the main
energy system.
Component
FuelCell Only
FuelCell + Batteries
Vehicle(1)
Bateries(9)
Fuel Cell(10)
Ucaps(3) + static converter(4)
Total cost of energy(5)
(6)
Maintenance
Residual value(7)
$ 8,000
$0
$ 20,000
$0
$ 3,670
$ 2,856
-$ 238
$ 8,000
$ 5,706
$ 4,000
$0
$ 3,110
$ 2,856
-$ 238
$ 8,000
$0
$ 4,000
$ 5,160
$ 2,960
$ 2,856
-$ 238
PV of total costs(8)
$ 34,287
$ 23,433
$ 22,737
Total average cost ($/km)
$ 0.220
$ 0.150
$ 0.146
-31.7%
-33.7%
Cost change percentage
-
FuelCell + Ucaps
V.2 Related researches
During the last three years, a growing number of scientists have implemented and
tested systems of similar characteristics, which is a sign that this project was aimed in
the right direction. Moreover, by analyzing their results it is clear that some technical
issues have been well resolved in this design and innovative strategies, such as the
69
algorithms developed, have rewarded positive improvements. A brief review of
related publications of other authors during this period follows and relevant
conclusions will be compared to results from this project.
Presently general trends are inclined towards HEVs as a viable approach to zero (or
near zero) emission vehicles. The separation of energy-storage and power-support
tasks has proved a very efficient and effective strategy; more adequate elements have
been applied to each task, which has had a positive impact in power and efficiency,
and therefore in autonomy as well. Also, although HEV’s total costs are still not
competitive, its advantages compared to traditional ICE-vehicles are being
recognized by the industry, such as reduction in maintenance costs (King et al, 2005)
and improved comfort.
On the subject of available MESs for zero and near-zero-emission HEVs, most
projects are experimenting with FCs as being feasible in the long term, even though
primary and secondary batteries are the most viable in the short-medium term
because of costs and infrastructure concerns (Chan and Wong, 2004). Nevertheless,
there are two interesting researches showing hybrid systems using batteries as the
MES, both of them primary Zn/air batteries (Stanislowski et al, 2003; King et al,
2005), and ultracapacitor-based AESs.
In the case of power sources (AESs), batteries and ultracapacitors are currently the
only commercially available choices, where ultracapacitors have proved superior in
most cases. Longer and DOD-independent cycle life, good performance at low
temperatures(-40ºC), lower cost per kW and higher specific power are the most
outstanding advantages against batteries (Schneuwly and Smith, 2005; Jeon et al
2005). But also, performance evaluation in several researches have demonstrated
better overall system efficiency, and therefore lower operation costs and higher
autonomy in HEVs when evaluating ultracapacitors compared to power-batteries as
AES (Mazaika and Schulte, 2005).
Some studies have explored and confirmed the influence of energy management
strategies on vehicle performance and efficiency (Stanislowski et al, 2003; Mazaika
and Schulte, 2005), which has been an important subject in this thesis. This contrasts
with some other studies where ultracapacitors have been applied as AESs directly
70
connected to the power bus (Massé and Freeman, 2005; Jeon et al 2005), without a
static converter interface, an approach that limits or eliminates any possibility of
managing energy and power. Such an approach, even though it may save some losses
by eliminating a static converter, is inefficient in the use of ultracapacitor energy
storage space; its power support is uneven and only available during transients.
In the meanwhile, the use of ultracapacitor-based AESs grows in number and
application variety. An example is a sport HEV, integrating an ICE and ultracapacitor
power support (Martellucci and Santoro, 2005). This is a different approach than the
typical efficiency oriented HEV; nevertheless it confirms the power potential
ultracapacitors have.
Finally, some more specific technical papers seek to extend the knowledge regarding
ultracapacitor behavior. One interesting example evaluates performance under
thermal and mechanical stress (Conte and Pirker, 2005); another addresses key
issues, such as cell balancing, materials optimization and safety (Okamura and
Nakamura, 2003).
V.3 General discussion
Since the beginning of this project, relevant advances and results obtained from it
have been published in engineering journals and/or presented in specialized
symposiums. Among these publications, the most relevant published topics are:
system configuration proposal and simulated behavior analysis (Dixon et al, 2000);
partial results and system behavior description (Dixon and Ortúzar, 2001; Dixon et
al, 2003; Ortúzar et al, 2003); new energy management strategy proposal (Moreno et
al, 2004); fire incident description and analysis (Ortúzar et al, 2004); Final results and
system feasibility analysis (Ortúzar et al, 2005), and a new HEV configuration, using
a ZEBRA (Na/Ni/Cl2) battery and the AES described in this thesis (Dixon et al,
2005). The most relevant conclusions from those works have been mentioned in this
thesis; nevertheless, some have been omitted for practical reasons.
Regarding technical achievements in this project, it was demonstrated that power,
efficiency and yield were increased as a result of incorporating the ultracapacitorbased AES to an EV using lead-acid batteries as a MES. Power increase was
71
noticeable for different drivers, but also was measured in the form of voltage
depression reduction. This experience confirms previous findings about available
power (Wight et al, 2001; Wight et al, 2002), but also demonstrates that efficiency,
and therefore autonomy, can be increased using this type of power support. However,
it was established that efficiency increase is directly linked to energy management
adequacy. This finding can be extended to the reasonable deduction that the energy
storage system usage can be maximized with an adequate power and energy control.
In this way the MES and AES for a particular vehicle can be optimized in size and
weight and therefore costs may be reduced.
Conclusions are relative regarding the convenience of this type of AES for lead-acid
batteries-based vehicles. In an optimistic scenario, where batteries life-cycle
increases in 50%, the ultracapacitor-based AES’s cost is compensated by savings in
battery replacement and energy, while adding the value of higher power and
autonomy. In the not-so-optimistic scenario, where battery life-cycle increases by
20%, the present value of costs increase by about 8% when using the studied AES,
while vehicle power rating is improved; therefore, in this scenario the system’s
convenience will depend on the value of consumer satisfaction due to the improved
vehicle performance.
The experience acquired in this project, while working with the designed and
constructed AES, suggests that a better complement could be achieved if the
designed system is combined with more energy-oriented batteries (higher specific
energy, lower specific power). Primary batteries, such as Zn/air or Al/air, have
already been successfully tested in combination with ultracapacitor-based AES
(Stanislowski et al, 2003; King et al, 2005). But because of the extremely low
specific power these batteries have, such configurations need (and have used) a
second battery to provide power for prolonged high power demand episodes, like
uphill or high speed driving. Hence, a battery of power and energy characteristics in
between Zn/air and lead-acid could perfectly match with an ultracapacitor-based
AES.
As a consequence of previous analysis, the project described in this thesis has been
extended to evaluate the proposed approach: the better match of a higher specific-
72
energy (and lower specific-power) battery, and the designed AES for efficient and
powerful performance. This configuration has already been implemented using a
ZEBRA (Na/Ni-Cl2) battery and is being tested to determine behavior and
performance under different situations and driving conditions.
73
VI
CONCLUSIONS
In this thesis a power-energy system specially developed for state of the art Electric
Vehicles has been described, analyzed and evaluated. As for the project’s outcome, it is
valid to say that the general project objectives, as well as particular design objectives, have
been broadly fulfilled. During the whole process there has been constant screening and
interaction with other researchers working on similar projects, which has allowed for an up
to date critical evaluation and makes results presented here a real contribution to the
modern transport industry.
The search for innovative solutions to address contemporary transport and environmental
issues has motivated the development of a practical, powerful and clean transport
alternative. Starting from an EV configured with state-of-the-art equipment, key technical
problems have been addressed; namely: instantaneous available power, efficiency and
autonomy. An Auxiliary Energy System based on ultracapacitors and a buck-boost
converter has been designed, implemented and tested. Its performance has been technically
and economically evaluated, whose results have been extended to fuel-cell powered
vehicles.
In particular, the achieved power and energy management capabilities were more than
satisfactory, being able to deliver or accept more than 60 kW of power. The ease of powerflow control and overall system efficiency may be attributed to the thorough design of key
components, such as the 1.6 mH smoothing inductor and the water-cooled heat-sink,
among others, as well as the adequate topology configuration and implementation. These
features allowed for a powerful and controllable device that could be integrated into an
electric vehicle and safely interact with other power components without conflict.
The control and monitoring structure was also an important component of the Auxiliary
Energy System and one of the keys to the project success. The control system composed of
digital hardware and software, not only allowed for a fine control of power flow and safe
operation, but also supported the evaluation process by allowing the implementation of
different energy management strategies and by providing data logging and real-time
monitoring features.
74
The implemented system achieved an increase in vehicle yield (km/kWh), and therefore in
vehicle efficiency, of up to 8.9% using an optimum control energy management algorithm.
The available power was increased from an unreliable 40 kW value to a nominal 57 kW
and maximum 85 kW, which was evident to the driver.
Economical evaluation showed mixed results. While a hypothetical increase of 50% in
battery life would compensate for the costs of an AES such as the one being evaluated,
lower increases in battery life would not and, therefore, the influence of consumer
satisfaction would be the measure by which the convenience of this particular
configuration should be judged.
The hypothetical combination of fuel-cells and ultracapacitors was also economically
evaluated in comparison to pure fuel-cell as well as fuel-cell combined with batteries. The
outcome was that the reduction of fuel-cell size in both combination cases (with batteries
and with ultracapacitors) allowed for an important reduction in total costs, both alternatives
being more than 30% cheaper than the pure FC configuration in terms of total life cycle
costs.
This project’s results were compared to and complemented by those obtained from other
researchers working on similar projects. Also, relevant results from every stage of
development were published and presented in pertinent journals and symposiums. Thus,
conclusions presented here meet the highest standards of the international scientific
community and transport industry.
Therefore, it is fair to say that every major and particular objective of this thesis has been
fulfilled, and that the proposed hypothesis has been demonstrated and adequately
discussed.
Improvements achieved are consistent and significant, but as mentioned above, better
energy storage devices combinations may be implemented by using more energy-oriented
batteries. In this particular project, that challenge has already been assumed, therefore a
new high specific-energy ZEBRA (Na/Ni-Cl2) battery, in combination with the
aforementioned AES, has been installed in the same EV. The vehicle is now undergoing
preliminary tests; a general evaluation, like the one presented in this thesis, will be
performed in the near future.
75
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82
APPENDICES
83
APPENDIX A: BUCK-BOOST CONVERTER OPERATION ANALYSIS
Figure A.1 illustrates a buck-boost topology for current ripple analysis and equation
deduction.
Battery
iBAT
iC
Rint
T2
D2
+
+
VC
LS
C
ultracapacitor
bank
iU
ESR
VB
T1
Buck Side
D1
VS
+
VU
Boost Side
Figure A.1: Buck-Boost topology.
Equation A.1 defines the duty cycle (δ) as the percentage of time a semiconductor (T1 or
T2) is switched on.
δ=
t0
T
(A.1)
Where T is the commutation period and t0 is the amount of time the IGBT in question is
conducting.
Equation A.2 describes the mean voltage VS when IGBT T2 commutates (buck operation).
Vs =
t0
⋅ VC = δ ⋅ VC
T
(A.2)
Figure A.2 illustrates the current through Ls and its ripple. This plot will be used to deduce
equations that describe this current behavior.
84
di b
dt
di b
dt
(+ )
t0
(− )
∆ib
T-t0
T
Figure A.2: Current through Ls and it ripple.
The positive slope sections of the current waveform correspond to the portion of time the
semiconductor T2 is on. This slope depends on voltages VU and VB, resistances Rint and
ESR, and on the value of inductance Ls. The negative slope depends on VU, resistance ESR
and inductance Ls. If resistance values are neglected the positive and negative slopes can
be described as in equations A.3 and A.4.
dib
dt
(+)
dib
dt
(−)
=
VB − VU ∆ib
=
Ls
t0
=−
(R 2 ≈ 0 , R int ≈ 0)
∆ib
VU
=−
Ls
T − t0
(R 2 ≈ 0 )
(A.3)
(A.4)
Combining equations A.1, A.3 and A.4 leads to equation A.5, which describes current
ripple amplitude as a function of battery voltage VB, inductance Ls, commutation
frequency f and duty cycle δ.
∆i b =
VB
⋅ δ ⋅ (1 − δ )
Ls ⋅ f
1

f = 
T

(A.5)
The condition to maximal current ripple can be found when the derivate of equation A.5
respect to δ is equal to zero. Solving this equation results in a value for δ of 0.5. Replacing
this value in equation A.5 results in the maximum ripple value for current Ib, which is
expressed in equation A.6
85
∆i b max =
Vdc
4 ⋅ f ⋅ Ls
(A.6)
86
APPENDIX B: DISIPATED ENERGY AND HEAT GENERATION IN
SEMICONDUCTORS.
Losses in semiconductors can be classified, for calculation purposes, in commutation
losses and conduction losses. Both parameters are calculated separately as follows.
a) Commutation losses.
During semiconductor commutation (forced-commutation state transitions from off
to on and vice versa) currents and tension across semiconductor juncture do not
change instantaneously, therefore there exists a transition period in which the product
VCE·I is small but not zero. If the semiconductor commutates several thousand times
per second, the total amount of lost energy during these transitions is not negligible.
The instantaneous power losses during a commutation may be calculated by
obtaining and multiplying voltage and current waveforms during these operations, if
the instantaneous power is integrated along the whole commutation process the
energy lost during this operation is obtained. Nevertheless the manufacturer provides
an estimation of this value, plotted as a function of the collector current value and the
C-E voltage. By selecting the lost energy value from this plot, corresponding to the
application conditions, and multiplying it times the commutation frequency, the total
loss power corresponding to commutations is obtained. Equation B.1 shows this
equivalency, where P_conmut is expressed in Watts.
P _ commutation = (E on + E off )[J / cycle] ⋅ 12000[cycles / sec]
(B.1)
b) Conduction losses.
Conduction loses are present in the IGBT and anti-parallel diode, these are calculated
separately for each one according to manufacturer datasheet specifications.
Instantaneous conduction losses in IGBT are calculated multiplying instantaneous
current times the Collector-Emmiter voltage. This tension, obtained from the
component’s datasheet, depends on collector current and temperature.
Diode losses are calculated the same way. Conduction current is multiplied by diode
forward voltage, obtaining instantaneous power loss.
87
Given the buck-boost configuration and operating characteristics, as described in
chapter II.2.1, an IGBT and corresponding diode (in parallel with the opposite IGBT)
conduct current alternately, during δ and (1-δ) portions of commutation period,
respectively. If ripple is small enough compared to the DC component of current,
then the same current value (equal to mean current through ultracapacitors) may be
assumed for IGBT and diode when each one is conducting. This is valid for buck or
boost mode. Thus, mean conducted current through each component, and its
corresponding power loss value, may be calculated using the current through
ultracapacitors and the duty cycle, as shown in equations B.2 and B.3. This loss
power value is calculated the same way for both buck and boost operations, changing
only the component that produces it and the duty cycle value.
P _ conduction _ IGBT = VCE [V ] ⋅ I C [ A] ⋅ δ
(B.2)
P _ conduction _ diode = V FD [V ] ⋅ I C [A] ⋅ (1 − δ )
(B.3)
c) Losses in worst case scenario.
The current has been limited by software to 150 A at the ultracapacitors side, thus the
worst case scenario is when ultracapacitors are successively charged and discharged
at this maximum current. A charge-discharge cycle once every minute between 290
V and 150 V, representing a transfer of more than 70% of the stored energy, will be
simulated and losses calculated.
From equations B.1, B.2 and B.3, and values taken from the semiconductor
datasheet, the power losses for the diode and IGBT while conducting 150 A are those
shown in table B-1.
88
Table B-1: Instantaneous power losses while conducting 150A in semiconductors.
IC
Commut _ IGBT [W ]
Conduct _ IGBT [W ]
Conduct _ Diode [W ]
150
168 W
260*δ W
210*(1-δ) W
As stated in chapter II.2.1, a buck boost converter behaves as a DC-DC transformer
regarding current and voltage mean values. Therefore, if series resistances are small
enough, when transferring energy from a battery with voltage VB to the ultracapacitor
with voltage VU (buck operation), the duty cycle will be of a value very close to
δ=VU/VB. In the same way, when transferring current from the ultracapacitors to the
battery (buck operation), the duty cycle will be of a value very close to δ=(1-VU/VB).
Also, because at constant current the capacitor voltage will decrease (or increase)
linearly with time, the duty cycle will also change linearly with time. Thus, the mean
value for the duty cycle may be calculated by interpolating between maximum and
minimum duty cycle values for each operation. This mean duty cycle was used to
obtain mean power losses values shown in table B-2.
Table B-2: Mean power losses while conducting 150A in semiconductors.
Conduct _ IGBT [W ] Conduct _ Diode [W ]
Operation
δ
Commut _ IGBT [W ]
Buck
0.688
168 W
178.9 W
65.5 W
Boost
0.353
168 W
91.8 W
135.9 W
A 20.45 F capacitor will take 19.09s to be charged or discharged between 290 V and
150 V at a constant current of 150 A. As this exercise considers one charge and
discharge operation per minute, individual semiconductor mean power losses may be
calculated. These mean power values are shown in table B-3.
89
Table B-3: Mean power losses throughout time, while cycling 150 A charge and
discharge operations for 19.09s within 1min period.
Operation
Total Mean Losses in IGBT
Total Mean Losses in Diode
Buck
110.3 W
20.8 W
Boost
82.7 W
43.2 W
Adding all mean power losses yields the total mean power, equal to 257 W.
Transient thermal impedance was considered large enough to maintain a relatively
stable temperature; therefore the mean power loss can be used to calculate the
required thermal resistance to achieve a certain temperature.
d) Thermal resistance to ensure temperature compliance.
It was decided that a water cooled heat-sink would be used to control temperature in
the semiconductors; the water cooling system used to evacuate losses from the
inverter-motor group would remove heat form this heat-sink.
During summer days, at 35ºC external temperature, the maximum measured water
temperature in the water cooling system had been 55ºC. Also, the measured vehicle
mean power was around 10 kW during these tests. The inverter-motor group has a
total efficiency rated around 90%; hence the thermal resistance of the water cooling
system was calculated at 0.02ºC/W.
With the water circuit’s thermal resistance and the semiconductor’s total mean loss
power, the water temperature was calculated for the worst case scenario mentioned
before. In a day with 35ºC of ambient temperature, absorbing 1 kW of lost power
from the motor-inverter group and 257 W from the buck-boost converter, the water
temperature should rise to about 60.14ºC.
Using the total mean power loss calculated above, thermal resistances provided by
the semiconductor manufacturer (see Appendix D) and the water temperature
calculated above, the model shown in chapter II.4 was completed except for the heatsink’s thermal resistance (Rth(c-f)).
90
Using the maximum allowed temperature for semiconductors junctures (110ºC) and
semiconductor case (100ºC), the required heat-sink’s thermal resistance may be
calculated to ensure temperature limits on each semiconductor. These required values
are shown in table B-4.
Table B-4: Water-cooled heat-sink’s required thermal resistance to ensure
temperature compliance for each semiconductor and case.
Case
IGBT1
Diode1
IGBT2
Diode2
0.155 ºC/W
0.120 ºC/W
0.140 ºC/W
0.107 ºC/W
0.126 ºC/W
From table B-4 it can be deduced that, to ensure temperature compliance while
working at the intensive charge-discharge cycling mentioned above, the heatsink’s
thermal resistance must be equal or lower than 0.107 ºC/W.
91
APPENDIX C: ECONOMIC EVALUATION CONSIDERATIONS
1
Arbitrary estimated value of vehicle without energy source of US$8000. Represents an
approximate cost of structure, accessories and drive train.
2
Cost of lead-acid batteries for 12 years of operation, based on US$150/kWh (Chan and
Wong, 2004). On batteries only configuration (base case), batteries life is 35.000 km. On
the “50%+” case, batteries life is 52.500 km; for the “20%+” case, batteries life is 42.000
km. Replacement costs of US$1000 per replacement are included in battery costs.
3
Projected costs of ultracapacitors is US$30 per 2700F cell (Sund and Trice, 2001).
4
Estimated cost of static converter is US$1200.
5
Cost of energy is based on projections by Energy Information Administration (EIA,
2005).
6
Cost of maintenance is an estimated value of US$400/year.
7
The vehicle and battery residual values were estimated separately. A value of US$800 is
considered a reasonable price for a 12 year old vehicle in good conditions. The battery
residual value was calculated by applying the remaining/total cycles percentage to the
new battery value, reduced in 30% because of non-new equipment devaluation.
8
The Present Value (PV) of costs is the sum of all discounted costs. The rate used for
discount is 8% (Taylor, 2003)
9
The estimated life of a Li-ion battery for a hybrid vehicle is 6 years.
10
Fuel cells cost is US$200/kW (Chan and Wong, 2004).
92
APPENDIX D: TMS320F241 DSP CONTROLLER, TEXAS INSTRUMENTS
93
94
APPENDIX E: DSP CODE, ASSEMBLER LANGUAGE
;================================================================
;
Programa de Control para Sistema
;
Auxiliar de Energía, Basado en Ultracapacitores
;
y Convertidor Buck-Boost
;================================================================
.include "243_dsk.h"
;============================================================
;================================================================
;Definición de variables
.bss
TABLA_CARGA, 70
;dir 514
.bss
CODIGO_FALLA, 1
;dir 584
.bss
IFILT, 1
;
585
.bss
V_BATT, 1
;
586
.bss
V_COND, 1
;
587
.bss
IREF, 1
;
588
.bss
ANA3, 1
;
589
.bss
VELOCIDAD, 1
;
590.
.bss
ANA5, 1
;
591
.bss
REF_CARGA, 1
;
592
.bss
AH, 1
;
593
.bss
ANA6, 1
;
94
.bss
ANA7, 1
;
95
.bss
ANA0, 1
;
96
.bss
ANA2, 1
;
97
.bss
ANA4, 1
;
98
.bss
ANA1, 1
;
99
.bss
I_BB, 1
;
600
.bss
PWM, 1
;
1
.bss
ERROR, 1
;
2
.bss
IANTERIOR, 1
;
3
.bss
ACCALTO,1
;
4
.bss
ACCBAJO, 1
;
5
.bss
KP, 1
;
6
.bss
KI, 1
;
7
.bss
KP1, 1
;
8
.bss
KI1, 1
;
9
.bss
I_LIM, 1
;
10
.bss
V_LIM, 1
;
11
.bss
CERO, 1
;
12
.bss
FRECUENCIA, 1
;
13
.bss
I_LIM_TEMP, 1
;
14
.bss
CONTROL_VOLT, 1
;
15
.bss
MODO, 1
;
16
.bss
I_BATT, 1
;
17
.bss
ANA01, 1
;
18
.bss
ANA02, 1
;
19
.bss
ANA03, 1
;
20
.bss
ANA04, 1
;
21
.bss
IREF_TEMP, 1
;
22
.bss
IANTERIOR2, 1
;
23
.bss
PWM_TEMP, 1
;
24
.bss
CONTADOR_AH, 1
;
25
.bss
SIGN, 1
;
26
.bss
SIGN_TEMP, 1
;
27
.bss
CONT, 1
;
28
.bss
ERROR_CARGA, 1
;
29
.bss
IANT_CARGA1, 1
;
30
.bss
IANT_CARGA2, 1
;
31
.bss
SALIDA2, 1
;
32
.bss
TEMP,1
;
33
.bss
FLAG_CARGA, 1
;
34
.bss
CARGA, 1
;
35
.bss
FLAG_CARGA2, 1
;
36
.bss
CONTADOR_RX, 1
;
37
.bss
CONTADOR_TX, 1
;
38
.bss
CONTADOR_COMM, 1
;
39
.bss
.bss
RELLENO1, 1
RELLENO2, 1
;
;
.bss
.bss
.bss
.bss
I_LOAD, 1
I_COMP, 1
CONT_DIV, 1
DIVISION_ALTO,1
;
;
;
;
40
41
43
44
45
42
95
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
.bss
DIVISION_BAJO,1
V_COND_2,1
V_BATT_2, 1
MULTIPLO,1
EXPONENTE,1
RESTO, 1
MODO_FLASH, 1
READY, 1
READY2, 1
CONTADORSPI, 1
CONTADORSPI_TX, 1
CONTADORSPI_RX, 1
DIRSPI, 1
BUFFERSCI, 1
FLAG_HISTERESIS, 1
FLAG_FALLA, 1
FLAG_ESCALA, 1
DIRECCION_PEDIDA, 1
REGISTRO_PRUEBA, 1
DIVISOR, 1
I_LIM_NEG_T, 1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
;
65
66
.sect ".estados"
;----------------------------------------------------------------------;Definición de variables globales
.global INICIO
;================================================================
;================================================================
.sect
RSVECT
"vectors"
B
1F00h
INT1
B
GISR1
;Int externas, alta prioridad
INT2
B
GISR2
;Int Timer 1
INT3
B
PHANTOM
; PM 6 Int level 3
INT4
B
INT4_ISR ; PM 8 Int level 4
7
INT5
B
INT5_ISR ; PM A Int level 5
8
INT6
B
PHANTOM
; PM C Int level 6
;================================================================
6
9
;Inicializaciones generales
;===================================================================
; Constantes
I_LIM_MIN
dV_1
dV_2
I_LIM_NEG1
I_LIM_NEG2
V_BATT_LIM1
.set
.set
.set
.set
.set
.set
10
5
15
4
6
350
;===================================================================
.text
INICIO
deshabilitadas.
acc.
LDP
SETC
#0h
INTM
;Interrupt mode, 0=todas las mascarables
CLRC
CLRC
CLRC
CNF
SXM
OVM
;DARAM config, 1=RAM para datos.
;Sign extension, 0=supress extension.
;Overflow mode, 0=resultado de overfl va al
SETC
SPLK
LDP
SPLK
XF
#0000h, IMR
#0E0h
#068h, WDCR
;XF es un flag externo, 0=pin en low.
;Mascaras de interrupción (1-6).
; Configuración PWM
LDP
#0E8h
SPLK
#00000h, T1CNT
SPLK
#00000h, T2CNT
SPLK
#00000h, T1CMPR
SPLK
#00000h, T2CMPR
SPLK
#00320h, T1PR
SPLK
#01187h, T2CON
SPLK
#01146h, T1CON
SPLK
#00045h, GPTCON
;Desabilita el Watch Dog timer.
;Inicializo contadores en 1.
;Se inicia en PWM=0.
;Seteo Período timer a 833 ciclos(341)
;Seteo de control del contador 2.
;Seteo de control del contador 1.
;enciendo los pwm.
96
;Configuración de Comparadores del modulo Capture
SPLK
#00h, CAPFIFO
SPLK
#0010001001010000b, CAPCON
;=====================================================================
; Borrar datos en la RAM
;=====================================================================
LAR AR0,#0200h
; AR2 -> B0 start address
MAR *,AR0
; Set ARP=AR2
ZAC
; Set ACC = 0
RPT #0255
; Set repeat cntr for 255+1 loops
SACL *+
; Write zeros to B0 RAM
;=====================================================================
lectura
;Bloque
LDP
SPLK
SPLK
SPLK
de Configuración Puertos I/O
#000E1h
;Página 225 (7080h)
#0301Fh, OCRA
;Registro de control de puertos de entrada y
#0031Ch, OCRB
; salida.
#0E000h, PADATDIR
;Configura los pines del Puerto A para
SPLK
#0CF00h, PBDATDIR
SPLK
SPLK
#06020h, PCDATDIR
#00000h, PDDATDIR
;Bloque
LDP
SPLK
SPLK
BIT
BCND
LACL
LACL
LACL
LACL
Conversores A/D
#00E0h
#00000h, ADCTRL2
#3910h, ADCTRL1
ADCTRL1, 7
ESPERA10, NTC
ADCFIFO1
ADCFIFO1
ADCFIFO2
ADCFIFO2
;Configura los pines del Puerto B para
lectura
ESPERA10
;Se inicia conversión de datos 0 y 1
;Clear ADC FIFOs
;Clear ADC FIFOs
;Configuración SPI
SPLK
#00h, SPICCR
SPLK
#0Ah, SPIBRR
SPLK
#00000110b, SPICTL
SPLK
#040h, SPIPRI
SPLK
#10001111b, SPICCR
;=====================================================================
; Inicialización de rutina de comunicación
;=====================================================================
SCI_INIT:
LDP
#00E0h
SPLK #0027h, SCICCR
;1 stop bit,odd parity,8 char bits,
;async mode, idle-line protocol
SPLK #0003h, SCICTL1
;Disable RX ERR, SLEEP, TXWAKE
SPLK #0003h, SCICTL2
;Enable RX INT,enable TX INT
SPLK #0000h, SCIHBAUD
SPLK #0040h, SCILBAUD
;Baud Rate=38400 b/s (20 MHz SYSCLK)
SPLK #0023h, SCICTL1
;Relinquish SCI from Reset.
SPLK #0060h, SCIPRI
;Prioridad baja para el SCI
LAR
LAR
AR1, #SCITXBUF
AR2, #SCIRXBUF
;Load AR0 with SCI_TX_BUF address
;Load AR1 with SCI_RX_BUF address
;================================================================
;Bloque principal
;================================================================
;Lectura de Ah y parametros en mem Flash
CALL
CALL
CALL
LDP
LACL
SACL
LEER_PARAM_FLASH
LEER_AH_FLASH
LEER_TABLA_FLASH
#04
CERO
IANT_CARGA2
97
SPLK
#0, MODO
;================================================================
;Seteo de interrupciones
;================================================================
LDP
#0h
LACC IFR
;Load ACC with Interrupt flags
SACL IFR
;Clear all pending interrupt flags
CLRC INTM
;Enable interrupts
SPLK
#011011b, IMR
;Desenmascaro (INT1 e) INT2
LDP
SPLK
SPLK
#0E0h
#0101b, XINT1CR
#0101b, XINT2CR
;Configuración de las interrupciones
; externas.
LDP
SPLK
SPM
SPLK
#0E8h
#080h, EVIMRA
#00h
#03h, EVIMRC
LDP
LACL
SACL
#04h
CERO
IANT_CARGA2
;habilita interrupción de periodo1.
;habilita interrupción de captura
;Se almacena el cero en el registro de
;integración del control de corriente de
;referencia para que no parta en otro valor.
;================================================================
;LOOP principal, dummy
;================================================================
LOOP
LDP
#04h
LACL
FRECUENCIA
LDP
#0E8h
SACL
T1PR
SPLK
BIT
CC
#0E1h
;Esta parte del Loop verifica que esté prendido
PCDATDIR, 8
;el inversor principal de la camioneta para
NO_READY, NTC
;setear el bit Ready.
#05h
#01h, READY
#01h, READY2
XXXX
#05h
#00h, READY
READY2, 15
ESCRIBIR_AH_FLASH, TC
XXXX
LDP
BIT
BCND
B
#0E1h
PDDATDIR,15
RESETEA_AH, NTC
LOOP
RESETEA_AH
LDP
LACL
SPLK
CC
AH
#00h, AH
NO_READY LDP
;
LDP
BIT
BCND
LDP
SPLK
SPLK
B
;en el loop principal solo se verifica una
;entrada digital para ver si el AH counter
;tiene valores negativos, si es así se
;resetea a cero la cuenta de AH en el DSP.
#04
ESCRIBIR_AH_FLASH, NEQ
;la cuenta de AH en el DSP se guarda en el
;Registro de codigo de falla.
B
LOOP
;****************************************************************
;Escritura de Ah
;================================================================
; Interrupción por falla
;================================================================
GISR1
MAR
lAR
SST
SST
*,AR0
AR0,#0200h
#1, *+
#0, *
LDP
SACL
SACH
ACCBAJO
ACCALTO
LDP
LDP
LACL
SUB
;Esta es la pequeña rutina que almacena
;los valores de configuración al entrar a
;una Interrupción. se guarda ST0 y ST1,
;además de el acumulador alto y bajo.
#04h
#0h
#0E0h
PIVR
#01h
;Se carga el Periferal Interrupt Vector,
;Para ver si la falla fue en el IGBT 1 o 2.
98
BCND
LACL
SUB
BCND
B
FALLA1
FALLA2
SALIDA
LDP
LACL
SACL
LDP
SPLK
B
LDP
LACL
SACL
LDP
SPLK
B
LDP
LACL
LACC
MAR
LAR
LST
LST
CLRC
RET
FALLA1, EQ
PIVR
#011h
FALLA2, EQ
SALIDA
XINT1CR
XINT1CR
#0E0h
#05h
#01, FLAG_FALLA
SALIDA
#0E0h
XINT2CR
XINT2CR
#05h
#02, FLAG_FALLA
SALIDA
#04h
ACCBAJO
ACCALTO, 16
*, AR0
AR0,#0201h
#0, *#1, *
INTM
;se borra el flag de interrupción
;Falla en IGBT1
;se borra el flag de interrupción
;Se recupera el acumulador y los
;registros de estado
; load ST0
; load ST1
;================================================================
; Interrupción de conversión A/D y PI
;================================================================
GISR2
ESPERA1
ESPERA2
ESPERA3
MAR
lAR
SST
SST
SETC
LDP
SACL
SACH
*,AR0
AR0,#0200h
#1, *+
#0, *
XF
#04h
ACCBAJO
ACCALTO
RPT
NOP
LDP
SPLK
SPLK
BIT
BCND
SPLK
BIT
BCND
LACC
LDP
SACH
LDP
LACC
LDP
SACH
LDP
LACC
LDP
SACH
LDP
LACC
LDP
SACH
#120
#0E0h
#00000h, ADCTRL2
#3910h, ADCTRL1
ADCTRL1, 7
ESPERA1, NTC
#3934h, ADCTRL1
ADCTRL1, 7
ESPERA2, NTC
ADCFIFO1, 10
#04h
ANA0
#0E0h
ADCFIFO1, 10
#04h
ANA2
#0E0h
ADCFIFO2, 10
#04h
ANA1
#0E0h
ADCFIFO2, 10
#04h
ANA3
LDP
SPLK
BIT
BCND
LACC
LDP
SACH
LDP
LACC
#0E0h
#3958h, ADCTRL1
ADCTRL1, 7
ESPERA3, NTC
ADCFIFO1, 10
#04h
ANA4
#0E0h
ADCFIFO2, 10
;Almacenaje de datos para la int.
; save ST1
; save ST0
;Se inicia conversión de datos 0 y 1
;Se inicia conversión de datos 2 y 3
;Se guardan datos 0 y 2
;Se guardan datos 1 y 3
;Se inicia conversión de datos 4 y 5
;Se guardan datos 4 y 6
;Se guardan datos 5 y 7
99
LDP
#04h
SACH
ANA5
;================================================================
;FITRO
DMOV
ANA03
;Se suman los ultimos cuatro valores
DMOV
ANA02
;de corriente y se dividen por 4
DMOV
ANA01
; (promedio movil simple)
LACL
ANA0
SACL
ANA01
ADD
ANA02
ADD
ANA03
ADD
ANA04
SFR
SFR
SACL
IFILT
LACL
CERO
ADD
CERO
SUB
IFILT
SACL
IFILT
;================================================================
;Ajuste de Voltaje
LACL
ANA1
;Se carga el valor de voltaje de
SFR
;Batt y se divide por dos, para
SACL
V_BATT
;obtener el valor real, se guarda.
;================================================================
;Control de carga
;================================================================
;Valor de carga real Corregida
C_NEG
LACL
SFR
SACL
LACL
SUB
BCND
LACL
SUB
RPT
SFR
SACL
LACL
SUB
SACL
BCND
ZAC
B
RPT
SFR
SACL
ADD
ANA2
V_COND
CERO
C_NEG, C
IFILT
IFILT
;(IFILT - CERO)/16=~(IFILT - CERO)/(2*7.5).
CERO
#03
I_BB
V_COND
I_BB
I_BB
NO_CERO,C
NO_CERO
#03
I_BB
V_COND
;Se guarda el valor de la operación
;a esto se le resta I_BB,
***
NO_CERO
SACL
I_BB
;con esto se calcula la tensión del condensador,
SQRA
I_BB
;corregida con la corriente, y elevada al cuadrado.
PAC
SFL
;se divide por 256, ya que 300^2=90.000
SACH
CARGA, 7
;y ese numero no cabe en 16 bits
;================================================================
; Valor de ref. de carga
1023/8
analoga
valor
LACC
ANA4, 13
;el ADC, 6825 RPM equivale a 130 KPH =~
SACH
VELOCIDAD
;se almacena como velocidad la entrada
LACL
LAR
SUB
VELOCIDAD
AR5, #69
#69
;dividida por 8
MAS_DE_70, C
AR5, VELOCIDAD
*, AR5
#0FFh
#0FFh
#04h
*
#2250
;de la tabla correspondiente a 70
;si no, se toma la velocidad real
BCND
LAR
MAS_DE_70
MAR
ADRK
ADRK
ADRK
LACL
ADD
base.(2250=300^2/4*0.1)
RPT
#2
;si la velocidad es mas de 70 se toma el
;se le suma el offset de 512 a la velocidad
;para utilizar el valor como puntero de tabla
;entonces (1+100/128)=1/(0.56).
;al final se suma la carga
100
SFL
SACH
REF_CARGA, 7
;... y se almacena como referencia
;================================================================
;Verificación de comunicaión y Bit Ready.
LDP
BIT
BCND
LDP
LACL
SUB
BCND
OK
#05h
READY, 15
MODO_0, NTC
MODO
#04h
#03h
VALIDA_FALLA, EQ
LACL
SUB
BCND
SPLK
CONTADOR_COMM
#24000
OK, NC
#0, MODO
SPLK
SPLK
ADD
SACL
#01, CODIGO_FALLA
#00, CONTADOR_COMM
#24001
CONTADOR_COMM
;cuando se esta funcionando conectado
;a un PC y se hacen pruebas de PWM
;fijo o ref de corriente fija, se debe
;tener la precaución de comprobar que
;existe comunicación para continuar
;ya que si no se puede sobrecargar el
;ultracapacitor, esto evita que el
;equipo quede a la deriva con corriente.
;Si se ha perdido la comunicación se
;hace cero la corriente y se pasa a
;modo CERO, o sea apagado.
;OJO que si se deja el equipo en
;MODO_3 y se pierde la conexión
;el eqipo sigue funcionando.
;================================================================
;Rutina para verificar que las fallas detectadas sean reales y no solo Ruido.
VALIDA_FALLA
NOHAY
LDP
BIT
BCND
SPLK
LDP
SPLK
BIT
BCND
LDP
SPLK
LDP
SPLK
B
LDP
SPLK
LDP
#05h
FLAG_FALLA, 15
PRUEBA_FALLA2, NTC
#10000b, FLAG_FALLA
#000E1h
#0301Bh, OCRA
PADATDIR, 13
NOHAY, NTC
#000E1h
#0301Fh, OCRA
#04h
#02, CODIGO_FALLA
APAGA
#000E1h
#0301Fh, OCRA
#05h
BIT
BCND
SPLK
LDP
SPLK
BIT
BCND
LDP
SPLK
LDP
SPLK
SPLK
LDP
SPLK
SPLK
LDP
SPLK
FLAG_FALLA, 14
NOFALLA, NTC
#100000b, FLAG_FALLA
#000E1h
#0011Ch, OCRB
PDDATDIR, 14
NOHAY2, NTC
#000E1h
#0031Ch, OCRB
#04h
#03, CODIGO_FALLA
#00h, MODO
#0E8h
#00000h, T1CMPR
#00000h, T2CMPR
#0E1h
#0CF40h, PBDATDIR
LDP
SPLK
LDP
BIT
BCND
LDP
SPLK
LDP
LACL
BCND
#000E1h
#0031Ch, OCRB
#04h
CODIGO_FALLA, 15
CODIG_1, NTC
#0E1h
#0CF40h, PBDATDIR
#04
CODIGO_FALLA
MODO_0, NEQ
;Página 225 (7080h)
;Página 225 (7080h)
;Falla en IGBT1
;almaceno el codigo de falla corresp.
;Página 225 (7080h)
PRUEBA_FALLA2
APAGA
NOHAY2
NOFALLA
CODIG_1
;pasamos a modo cero
;se apagan los PWMs
;Se prende la luz de falla
;================================================================
; SELECCIÓN DE MODO DE FUNCIONAMIENTO
LACL
MODO
;Verifica el modo de funcionamiento
BCND
MODO_0, EQ
;y salta al codigo correspondiente.
SUB
#01h
101
BCND
MODO_1, EQ
LACL
MODO
SUB
#02h
BCND
MODO_21, EQ
LACL
MODO
SUB
#03h
BCND
MODO_3, EQ
SPLK
#0, MODO
B
MODO_0
;================================================================
;Calculo del error, saturación y control PI
MODO_3
cargarlo con
escala
en forma
ESC
NEXT
NEXT1
NEXT2
NEXT3
SAT_CERO
NO_SAT2 MPY
LDP
LACL
SUB
V_COND
#04h
#20
;Al encender el sistema primero hay que
;corrientes moderadas, para esto se hace una
SPLK
#525, IREF
;de corrientes hasta los 80 volts para cargar
BCND
LACL
SUB
SPLK
BCND
LACL
SUB
SPLK
BCND
MODO_2, NC
V_COND
#50
#545, IREF
MODO_2, NC
V_COND
#80
#575, IREF
MODO_2, NC
;lenta.
LACL
SUB
SACL
BCND
SUB
BCND
BIT
BCND
BIT
BCND
SPLK
LACL
SACL
SACL
B
ADD
BCND
BIT
BCND
BIT
BCND
B
SPLK
SPLK
B
SPLK
SPLK
LT
MPY
PAC
ADD
ADD
SACH
SACL
ROL
BCND
LACL
SUB
BCND
SPLK
B
SPLK
SPLK
REF_CARGA
CARGA
ERROR_CARGA
NEXT, NC
#4
NEXT1, C
FLAG_CARGA2, 15
ESC, TC
FLAG_CARGA, 15
NEXT3, TC
#1, FLAG_CARGA2
CERO
IANT_CARGA2
SALIDA2
NORMAL2
#4
NEXT2, NC
FLAG_CARGA2, 15
ESC, TC
FLAG_CARGA, 15
NEXT3, NTC
ESC
#1, FLAG_CARGA
#0, FLAG_CARGA2
NEXT3
#0, FLAG_CARGA
#0, FLAG_CARGA2
ERROR_CARGA
KI1
PAC
ADD
RPT
SFL
SACH
BIT
LACL
IANT_CARGA1
IANT_CARGA2, 16
IANT_CARGA2
IANT_CARGA1
SAT_CERO, C
IANT_CARGA2
#1000
NO_SAT2, NC
#1000, IANT_CARGA2
NO_SAT2
#0, IANT_CARGA1
#0, IANT_CARGA2
KP1
IANT_CARGA2, 3
#5
SALIDA2, 7
SALIDA2, 0
SALIDA2
;calculo y almaceno el error de carga,
;REF_CARGA-CARGA es el valor del error
;si la carga es menor que la ref. se suma un
;valor positivo a la integral con esto la
102
NORMAL
BCND
SPLK
B
SUB
BCND
SPLK
NORMAL, NTC
#0, SALIDA2
NORMAL2
#1023
NORMAL2, NC
#1023, SALIDA2
NORMAL2
;================================================================
;Control de voltaje de batt.
LACL
V_BATT
SUB
V_LIM
BCND
NO1, NC
LDP
#5
SPLK
#I_LIM_NEG1, I_LIM_NEG_T
B
NXT
NO1
LACL
V_BATT
SUB
#V_BATT_LIM1
BCND
NO2, NC
LACL
V_LIM
SUB
V_BATT
LDP
#5
SACL
I_LIM_NEG_T
LT
I_LIM_NEG_T
LACL
#I_LIM_NEG2
SUB
#I_LIM_NEG1
SACL
I_LIM_NEG_T
MPY
I_LIM_NEG_T
PAC
SACL
DIVISION_BAJO
SACH
DIVISION_ALTO
LDP
#4
LACL
V_LIM
SUB
#V_BATT_LIM1
LDP
#5
SACL
DIVISOR
CALL
RUTINA_DIV
LACL
CONT_DIV
ADD
#I_LIM_NEG1
SACL
I_LIM_NEG_T
B
NXT
NO2
LDP
#5
SPLK
#I_LIM_NEG2, I_LIM_NEG_T
NXT
;================================================================
;Control de cruces de tensión
LDP
#4
LACL
V_BATT
SUB
V_COND
BCND
NO3, NC
SUB
#dV_2
BCND
NO3, NC
LACL
I_LIM
SACL
I_LIM_TEMP
B
NXT2
NO3
LACL
V_BATT
SUB
V_COND
BCND
NO4, NC
SUB
#dV_1
BCND
NO4, NC
SACL
I_LIM_TEMP
LT
I_LIM_TEMP
LACL
I_LIM
SUB
#I_LIM_MIN
SACL
I_LIM_TEMP
MPY
I_LIM_TEMP
PAC
LDP
#5
SACL
DIVISION_BAJO
SACH
DIVISION_ALTO
LACL
#dV_2
SUB
#dV_1
SACL
DIVISOR
CALL
RUTINA_DIV
LACL
CONT_DIV
ADD
#I_LIM_MIN
LDP
#4
SACL
I_LIM_TEMP
B
NXT2
103
NO4
SPLK
#I_LIM_MIN, I_LIM_TEMP
NXT2
;================================================================
;Control de corriente de batt
LACL
ANA3
;se carga el valor de corriente
SUB
#512
;de carga, se centra en cero
??????"SUB
#512"
BCND
CORR_NEG, NC
;si I_load era neg se salta.
LDP
#05h
SACL
I_LOAD
;si no se guarda y se escala:
LT
I_LOAD
;para escalar se multiplica por
MPY
#600
;300 y luego se divide por 512
PAC
RPT
#8
SFR
SACL
I_LOAD
LDP
#04
LACL
CERO
;le sumo el cero artificial y lo
LDP
#05
SUB
I_LOAD
;guardo, con la convención de corr
BCND
NO_NEG, C
ZAC
NO_NEG
SACL
I_LOAD
;positivas bajo el cero.
B
ADELANTE
;salto adelante.
CORR_NEG LACL
#512
;si la corriente era negativa
SUB
ANA3
;le saco el cero,
LDP
#05h
SACL
I_LOAD
LT
I_LOAD
;la multiplico por 200 y la divido
MPY
#400
;por 512, segun la escala de la
PAC
;fuente de datos.
RPT
#8
SFR
LDP
#04
ADD
CERO
;le sumo el cero artificial y lo
LDP
#05
SACL
I_LOAD
;guardo.
ADELANTE
LDP
#04
;Para comprobar que se respeten
ADD
I_LIM_TEMP,1
;los limites de corriente se le
SUB
SALIDA2
;suma I_LIM y se resta la salida,
BCND
ADELANTE2, C
;si esta Ok se sigue adelante,
LDP
#05
;si no esta Ok se vuelve a cargar
LACL
I_LOAD
;I_LOAD y se le suma I_LIM
LDP
#04
ADD
I_LIM_TEMP,1
SACL
SALIDA2
;esto queda como la salida.
SACL
IANT_CARGA2
;y se limita a este valor la integral
ADELANTE2
LDP
#05
;Ahora se comprueba que esté por
LACL
I_LOAD
;sobre I_LOAD-I_LIM_TEMP
SUB
I_LIM_NEG_T
LDP
#04
SUB
SALIDA2
BCND
ADELANTE3, NC
;si esta dentro del limite se sigue
LDP
#05
;si no, se fija la salida como
LACL
I_LOAD
SUB
I_LIM_NEG_T
LDP
#04
SACL
SALIDA2
;se guarda y también se fija a este
SACL
IANT_CARGA2
;valor la integral
ADELANTE3
;================================================================
;Ajuste de ref de corriente para escala de voltaje de condensador
MODO_21
LDP
#04
LACL
V_COND
;para evitar las divisiones por
LDP
#05h
;cero ó números chicos se toma como
SACL
V_COND_2
;voltaje mínimo 70 V.
SUB
#70
BCND
VOLT_OK, C
SPLK
#70, V_COND_2
VOLT_OK
LDP
#04h
;se prepara la salida para escalar,
LACL
SALIDA2
;primero se le quita el cero y se
SUB
CERO
;ve si es negativo, si es así se
BCND
SALIDA_NEG, C
;salta adelante, si no sigue.
LACL
SUB
LDP
SACL
LT
CERO
I_COMP
SALIDA2
#05h
I_COMP
;si es positivo, se saca el cero
;para escalar.
104
DIVIDIR3 LACC
MENOR3
FIN_DIV3 LACL
LIMITADOR1
SALIDA_NEG
DIVIDIR4 LACC
MENOR4
FIN_DIV4 LACL
LIMITADOR2
ADELANTE4
LDP
#04h
MPY
V_BATT
LDP
#05h
PAC
SACH
DIVISION_ALTO
SACL
DIVISION_BAJO
SPLK
#04000h, MULTIPLO
DIVISION_ALTO, 16
ADD
DIVISION_BAJO
LT
MULTIPLO
MPY
V_COND_2
SPAC
BCND
MENOR3,NC
SACH
DIVISION_ALTO
SACL
DIVISION_BAJO
LACL
CONT_DIV
ADD
MULTIPLO
SACL
CONT_DIV
BIT
MULTIPLO, 15
BCND
FIN_DIV3, TC
LACL
MULTIPLO
SFR
SACL
MULTIPLO
B
DIVIDIR3
CONT_DIV
SUB
#300
BCND
LIMITADOR1, NC
SPLK
#300, CONT_DIV
LDP
#04h
LACL
CERO
LDP
#05h
SUB
CONT_DIV
SACL
I_COMP
SPLK
#0, CONT_DIV
B
ADELANTE4
LDP
#05h
SACL
I_COMP
LT
I_COMP
LDP
#04h
MPY
V_BATT
LDP
#05h
PAC
SACH
DIVISION_ALTO
SACL
DIVISION_BAJO
SPLK
#04000h, MULTIPLO
DIVISION_ALTO, 16
ADD
DIVISION_BAJO
LT
MULTIPLO
MPY
V_COND_2
SPAC
BCND
MENOR4,NC
SACH
DIVISION_ALTO
SACL
DIVISION_BAJO
LACL
CONT_DIV
ADD
MULTIPLO
SACL
CONT_DIV
BIT
MULTIPLO, 15
BCND
FIN_DIV4, TC
LACL
MULTIPLO
SFR
SACL
MULTIPLO
B
DIVIDIR4
CONT_DIV
SUB
#300
BCND
LIMITADOR2, NC
SPLK
#300, CONT_DIV
LDP
#04h
LACL
CERO
LDP
#05h
ADD
CONT_DIV
SACL
I_COMP
SPLK
#0, CONT_DIV
LDP
LACL
LDP
SACl
;se multiplica por V_BATT.
;el resultado de la mult. se pasa al
;ACC y se guarda para ser dividido
;comienza la división con 2^15.
;cargo el numero a dividir
;cargo el multiplo y multiplico por
;el numero divisor
;este se resta al numero a dividir
;si la resta es negativa se salta,
;si no es negativa se guarda el numero
;a dividir restado y al resultado se
;le suma el multiplo
;pruebo si llegue al fin de la division
;si es asi, salto al final,
;si no es asi corro la coma del
;multiplo una posición.
;vuelvo a iterar.
;si terminó la división compruebo que
;el resultado no sea mas de 150 amps
;se le introduce el cero al resultado.
;guardo el resultado final como I_COMP
;reseteo CONT_DIV para otra division.
;la división de numeros negativos es
;analoga.
#05h
I_COMP
#04h
;Manda el valor de I_comp calculado
;anteriormente como I_Ref ... y punto.
IREF
;================================================================
105
;Control de corrientes maximas para buck_boost y carga minima
;la corriente maxima se fija en 200
LACL
IREF
;compruebo que este por debajo
ADD
#400
SUB
CERO
;de este valor, si no, se fija al
BCND
MAX_NEG, C
;tope.
LACL
CERO
SUB
#400
SACL
IREF
MAX_NEG
LACL
CERO
;lo mismo para el maximo negativo
ADD
#400
SUB
IREF
;que es -200.
BCND
MAX_POS, C
LACL
CERO
ADD
#400
SACL
IREF
MAX_POS
LACL
CARGA
;si la carga es mayor que 22500
SUB
#351
;(que es el maximo) se impiden las
BCND
V_MAX, NC
;corrientes negativas, es decir
LACL
IREF
;no se permite cargar mas los
SUB
CERO
;condensadores.
BCND
V_MAX, NC
LACL
CERO
SACL
IREF
V_MAX
LACL
CARGA
;si la carga es menor que 2250
SUB
#35
;(que es el minimo 10%) se impiden
BCND
V_MIN, C
;las corrientes positivas, es decir
LACL
IREF
;no se permite descargar los
SUB
CERO
;condensadores.
BCND
V_MIN, C
LACL
CERO
SACL
IREF
V_MIN
B
MODO_2
;=====================================================================
MODO_0
LDP
#04h
SPLK
#00h, IANTERIOR
SPLK
#00, IANTERIOR2
SPLK
#00h, PWM
MODO_01
LDP
#0E1h
SPLK
#0E000h, PADATDIR
LACL
PBDATDIR
AND
#0CF40h
OR
#00001h
SACL
PBDATDIR
LDP
#0E8h
SPLK
#00000h, T1CMPR
SPLK
#00000h, T2CMPR
LDP
#05h
SPLK
#0, FLAG_ESCALA
LDP
#04h
B
FIN
;-------------------------------------------------MODO_1
LACL
SIGN_TEMP
SUB
SIGN
BCND
DALE_NOMAS, EQ
LACL
CONT
BCND
TIEMPO_MTO, NEQ
SPLK
#05, CONT
B
MODO_0
;por la
TIEMPO_MTO
SUB
#01
SACL
CONT
BCND
FIN_TM, EQ
B
MODO_0
FIN_TM
LACL
SIGN_TEMP
SACL
SIGN
DALE_NOMAS
NOLUZ
CTRL_CARGA:
BIT
BCND
LACL
LDP
SPLK
SPLK
LDP
SPLK
SACL
SIGN, 15
PWMEN1, TC
PWM
#0E1h
#0E080h, PADATDIR
#0CF00h, PBDATDIR
#0E8h
#00000h, T1CMPR
T2CMPR
;en modo cero solo se monitorean
;las variables, ambas PWM son 0.
;se modifican las salidas
;digitales correspondientes a los
;leds.
;En el modo_1 se trabaja segun una
;PWM determinada por el programa
;o recibida del PC monitor.
;se implementó un tiempo muerto que
;tiene el largo del Nº en esta línea
duración del período de PWM.
;Según el signo que aparece en el
;mismo registro de la PWM se envía
;la señal al IGBT correspondiente
;y el otro ...callaito no mas.
;También se encienden las luces
;correspondientes.
106
LDP
LACL
SUB
LDP
MAX = 290)
CTRL_CARGA2
recuperación=288
CTRL_CARGA3
BCND
SPLK
LDP
B
BIT
BCND
LDP
LACL
SUB
NOLUZ2
CONTROL_DESC
#290
#05h
CTRL_CARGA2, NC
#01, FLAG_HISTERESIS
#04h
MODO_0
FIN, NTC
V_COND
#285
LACL
LDP
SPLK
SPLK
LDP
SPLK
SACL
PWM
#0E1h
#0E040h, PADATDIR
#0CF00h, PBDATDIR
#0E8h
#00000h, T2CMPR
T1CMPR
V_COND
LACL
SUB
SACL
SPLK
B
IREF
I_POS
LACL
SUB
SACL
SPLK
B
IFILT
LST
;correspondientes.
FIN
I_NEG
LDP
LACL
LACC
MAR
LAR
LST
#1, *
CLRC
CLRC
RET
;Control de voltaje de condensador V de
#40
CONTROL_DESC, C
MODO_0
B
LDP
LACL
SACL
;corrientes negativas, es decir
#04
;-------------------------------------------------MODO_2
LDP
#04
LACL
CERO
SUB
IREF
BCND
MODO_0, EQ
BCND
I_POS, C
FIN
;(que es el maximo) se impiden las (V_COND
#04h
CTRL_CARGA3, NC
#04h
MODO_0
#05h
#00, FLAG_HISTERESIS
FIN
LDP
LACL
SUB
BCND
B
;si la carga es mayor que 22500( CARGA)
FLAG_HISTERESIS, 15
BCND
LDP
B
LDP
SPLK
B
PWMEN1
#04h
V_COND
IFILT
ERROR
#00, SIGN_TEMP
PI
IREF
;En MODO_2 se debe seguir una referencia
;de corriente obtenida del programa
;o recibida del PC monitor.
;Aquí se decide si la corriente es positiva
;o negativa.
;Si es negativa se saca el valor de error
;y se setea el signo en cero (equivale a -)
;Si es positiva, lo mismo pero al revés.
ERROR
#01, SIGN_TEMP
PI
#0E8h
EVIFRA
EVIFRA
#04h
ACCBAJO
ACCALTO, 16
*, AR0
AR0,#0201h
#0, *-
;este pedacito de rutina es el que finaliza
;la interrupción, borra los flags y ese
;tipo de cosas.
;recupera el acumulador y los registros
;de estado
INTM
XF
;================================================================
PI
;Esta es la rutina de control PI,
;aqui se calcula el PI para obtener
;la PWM necesaria.
107
SATURNEG SPLK
NOSATURADO
TODOCERO SPLK
LDP
#05h
BIT
FLAG_ESCALA, 15
CC
ESCALA_CORRIENTE, NTC
LDP
#04h
;Cargo el error para multiplicarlo por
LT
ERROR
;Ki
MPY
KI
PAC
;El resultado pasa al acumulador
ADD
IANTERIOR
;le sumo la integral anterior *1024
ADD
IANTERIOR2, 16
SACL
IANTERIOR
;guardo todo dividido por 1024
SACH
IANTERIOR2
ROL
;saco el bit mas significativo,
BCND
SATURNEG, C
;si es 1 esta negativo, en ese caso...
LACL
IANTERIOR2
;devuelvo el bit mas significativo
SUB
FRECUENCIA
;le resto el PWM mas grande posible
SUB
#01
ROL
;para ver si esta saturado,
BCND
NOSATURADO, C
;si no es así salto,
LACL
FRECUENCIA
ADD
#01
SACL
IANTERIOR2
;pero si esta saturado, guardo este Nº
B
NOSATURADO
; y salto igual
#0, IANTERIOR
;... se pone un cero en la integral
SPLK
#0, IANTERIOR2
MPY
KP
;multiplico el error por Kp
PAC
;lo paso al Acc.
ADD
IANTERIOR2,10
;le sumo la integral *1024,
ROL
;le saco el bit mas signif. para ver
BCND
TODOCERO, C
;si esta negativo, si es así salto...
ROR
;, si no devuelvo el bit
SACH
PWM,6
;y guardo la suma como PWM
B
MODO_1
;Paso al Modo_1 donde aplico la PWM.
#00h, PWM
B
MODO_0
;... y pongo un Cero.
;luego salto a Modo_0
;=====================================================================
ESCALA_CORRIENTE
LDP
#04h
LACL
V_BATT
LDP
#05h
SACL
V_BATT_2
LDP
#04h
BIT
SIGN_TEMP, 15
BCND
ESCALA_BOOST, TC
LT
V_COND
MPY
FRECUENCIA
LDP
#05h
PAC
;el resultado de la mult. se pasa al
SACH
DIVISION_ALTO
;ACC y se guarda para ser dividido
SACL
DIVISION_BAJO
B
ESCALAR
ESCALA_BOOST
LACL
V_BATT
SUB
V_COND
SACL
TEMP
LT
TEMP
MPY
FRECUENCIA
LDP
#05h
PAC
SACH
DIVISION_ALTO
SACL
DIVISION_BAJO
ESCALAR
DIVIDIR31
MENOR31
SPLK
SPLK
LACC
ADD
LT
MPY
SPAC
BCND
SACH
SACL
LACL
ADD
SACL
BIT
BCND
LACL
SFR
#00, CONT_DIV
#0400h, MULTIPLO
DIVISION_ALTO, 16
DIVISION_BAJO
MULTIPLO
V_BATT_2
MENOR31,NC
DIVISION_ALTO
DIVISION_BAJO
CONT_DIV
MULTIPLO
CONT_DIV
MULTIPLO, 15
FIN_DIV31, TC
MULTIPLO
;comienza la división con 2^10.
;cargo el numero a dividir
;cargo el multiplo y multiplico por
;el numero divisor
;este se resta al numero a dividir
;si la resta es negativa se salta,
;si no es negativa se guarda el numero
;a dividir restado y al resultado se
;le suma el multiplo
;pruebo si llegue al fin de la division
;si es asi, salto al final,
;si no es asi corro la coma del
;multiplo una posición.
108
SACL
MULTIPLO
B
DIVIDIR31
;vuelvo a iterar.
FIN_DIV31
SPLK
#01, FLAG_ESCALA
LT
CONT_DIV
MPY
#29
PAC
RPT
#4
SFR
LDP
#04h
SACL
IANTERIOR2
SPLK
#0, ERROR
RET
;=====================================================================
RUTINA_DIV
LDP
#5
SPLK
#0400h, MULTIPLO
;comienza la división con 2^10.
SPLK
#0, CONT_DIV
XDIVIDIR31
LACC
DIVISION_ALTO, 16
;cargo el numero a dividir
ADD
DIVISION_BAJO
LT
MULTIPLO
;cargo el multiplo y multiplico por
MPY
DIVISOR
;el numero divisor
SPAC
;este se resta al numero a dividir
BCND
XMENOR31,NC
;si la resta es negativa se salta,
SACH
DIVISION_ALTO
;si no es negativa se guarda el numero
SACL
DIVISION_BAJO
;a dividir restado y al resultado se
LACL
CONT_DIV
;le suma el multiplo
ADD
MULTIPLO
SACL
CONT_DIV
XMENOR31 BIT
MULTIPLO, 15
;pruebo si llegue al fin de la division
BCND
XFIN_DIV31, TC
;si es asi, salto al final,
LACL
MULTIPLO
;si no es asi corro la coma del
SFR
;multiplo una posición.
SACL
MULTIPLO
B
XDIVIDIR31
;vuelvo a iterar.
XFIN_DIV31
RET
;=====================================================================
;Captura de corriente
;Esta rutina captura los pulsos del Ah
;meter y los suma consistentemente para
INT4_ISR
MAR
*,AR0
;calcular el valor de Ah consumido.
LAR
AR0,#0200h
SST
#1, *+
SST
#0, *
;Primero se hece la rutina de guardar
LDP
SACL
SACH
CAP1_INT
SUMA_UNO
CAP2_INT
ACCBAJO
ACCALTO
#04h
;datos para la interrupción.
#0E8h
;Se carga el registro de flags de interr.
;por captura para ver que unidad capturó
;un flanco de subida.
LDP
LACL
SUB
BCND
LACL
SUB
BCND
SPLK
LDP
LACL
LDP
SACL
B
#01h
CAP1_INT, EQ
EVIFRC
#02h
CAP2_INT, EQ
#03h, EVIFRC
#04
IFILT
#05
REGISTRO_PRUEBA
BAD_INT2
SPLK
LACL
LDP
LACL
ADD
SACL
SUB
BCND
B
#01h, EVIFRC
CAP1FIFO
#04h
CONTADOR_AH
#01
CONTADOR_AH
#00B40h
SUMA_UNO, C
FIN_INT_CAP
LACL
ADD
SACL
SPLK
B
AH
AH
#0, CONTADOR_AH
FIN_INT_CAP
PLK
LACL
LDP
#02h, EVIFRC
CAP2FIFO
#04h
EVIFRC
#01
;Si fue la unidad 1 se borra ese flag,
;se lee el registro cap1fifo para borrarlo
;y asi se puede producir otra int.
;Se suma 1 al contador de Ah.
;Se guarda el resultado,
;resto 2880 para ver si pasó 1/5 Ah,
;si es así se suma uno al contador oficial.
;si no se salta al final de la int.
;este es el contador oficial, aqui se
;le suma 1 (corrido en 8 bits).
;se resetea el contador Ah.
;salto al fin de la int.
;Si fue la unidad 2 se borra ese flag,
;se lee el registro cap2fifo para borrarlo
109
RESTA_UNO
FIN_INT_CAP
LACL
BCND
SUB
SACL
B
CONTADOR_AH
RESTA_UNO, EQ
#01
CONTADOR_AH
FIN_INT_CAP
LACL
BCND
SPLK
LACL
SUB
SACL
AH
FIN_INT_CAP, EQ
#00B40h, CONTADOR_AH
AH
#01h
AH
LACL
LACC
MAR
LAR
LST
LST
CLRC
RET
ACCBAJO
ACCALTO, 16
*, AR0
AR0,#0201h
#0, *#1, *
INTM
;...el resto es analogo al anterior...
;=====================================================================
INT5_ISR:
;Esta rutina es la que maneja las
;comunicaciones con el PC Monitor.
MAR
*,AR0
lAR
AR0,#0200h
;Esta es la rutina de inicio de la int.
SST
#1, *+
SST
#0, *
LDP
#04h
SACL
ACCBAJO
SACH
ACCALTO
LDP
LACL
SUB
BCND
LACL
SUB
BCND
B
#00E0h
PIVR
#0006h
SCI_RX_ISR,EQ
PIVR
#0007h
SCI_TX_ISR,EQ
BAD_INT
;cargo el registro de flags de interrupciones
;salto a la rutina correspondiente a la
;evento que inició la interr.
;si no es ninguna de las ant. salto a bad_int
SCI_RX_ISR:
DP
SPLK
LACL
MAR
BCND
BIT
BCND
LACC
SACL
B
#04h
#0, CONTADOR_COMM
CONTADOR_RX
*,AR2
NO_GUARDA, EQ
CONTADOR_RX, 15
IMPAR, TC
*,8,AR4
*
ISR_END1
;esta es la rutna de recepción de datos
;Reseteo el contador de seguridad.
;Cargo el contador de recepción.
;activo el registro auxiliar AR2.
;Si el contador es 0 salto a NO_GUARDA.
;pruebo el bit menos signif para ver
;si el contador esta impar. salta...
;si es par carga el pedazo mas signif de dato
;y lo manda a su direccion destino en AR4.
;pasa al fin de la int.
IMPAR
dato
LACC
*,AR4
;si es impar carga el pedazo menos signif de
OR
SACL
*+
incrementa.
NO_GUARDA
para
B
*
;se hace OR con el pedazo mas signif y luego
;se guarda en la dirección destino, esta se
ISR_END1
;paso al final de la interrupción.
#032h
;en el caso de no estar esperando datos, lo
;que llega se interpreta como un comando,
LACL
SUB
*
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
GUARDAR_PAR, EQ
*
#033h
CONTINUAR_0, EQ
*
#037h
ENVIAR_PAR, EQ
*
#038h
BORRA_FALLA, EQ
*
#039h
NUEVO_CERO, EQ
*
#031h
;lo que se identifica el valor del
;comando y se salta a su rutina
;correspondiente.
110
GUARDAR_PAR:
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
BCND
LACL
SUB
CC
LACL
SUB
CC
LACL
SUB
CC
LACL
SUB
CC
B
RECIBIR_TABLA, EQ
*
#034h
CONTINUAR_1, EQ
*
#035h
CONTINUAR_2, EQ
*
#036h
CONTINUAR_3, EQ
*
#045h
RECIBIR_DIRECCION, EQ
*
#046h
ENVIAR_DIRECCION, EQ
*
#047h
ESCRIBIR_DIRECCION, EQ
*
#041h
GUARDAR_TABLA_FLASH, EQ
*
#042h
LEER_TABLA_FLASH, EQ
*
#043h
GUARDAR_PARAM_FLASH, EQ
*
#044h
LEER_PARAM_FLASH, EQ
ISR_END
DMOV
SPLK
SPLK
LAR
B
MODO
#0, MODO
#16, CONTADOR_RX
AR4, #KP
ISR_END
DMOV
SPLK
SPLK
LAR
B
;Aqui se espera recibir la tabla de ref de
MODO
;cargas la que tiene una longitud de 70,
#0, MODO
;por lo que se pone un 140 en el contador
#140, CONTADOR_RX
;de recepción.
AR4, #TABLA_CARGA
;Y apunto al comianzo de la tabla
ISR_END
;con el AR4.
RECIBIR_TABLA:
;Esta rutina guardará los parametros de
;funcinamiento como p Ej. Kp o Ki...
;estos datos son 7 por lo que se pone un
;16 en el contador de recepción.
;Se apunta el AR4 al Kp que es el primero
;de los datos a almacenar.
RECIBIR_DIRECCION:
DMOV
SPLK
SPLK
LDP
LAR
B
MODO
#0, MODO
#2, CONTADOR_RX
#05
AR4, #DIRECCION_PEDIDA
ISR_END
ESCRIBIR_DIRECCION
DMOV
SPLK
SPLK
LDP
LAR
B
MODO
#0, MODO
#2, CONTADOR_RX
#05
AR4, DIRECCION_PEDIDA
ISR_END
CONTINUAR_0:
ENVIAR_DATO
SPLK
SPLK
LAR
LDP
B
#0, MODO
#20, CONTADOR_TX
AR3, #CODIGO_FALLA
#0E0h
SCI_TX_ISR
SPLK
LDP
LAR
LDP
B
#2, CONTADOR_TX
#5
AR3, DIRECCION_PEDIDA
#0E0h
SCI_TX_ISR
;Continuar_0 significa que seguimos en
;modo apagado (0) y solo enviamos datos.
;los datos a enviar son 9 por lo que
;ponemos un 18 en el contador TX y
;apuntamos con AR3 al primer dato a enviar.
ENVIAR_DIRECCION
CONTINUAR_1:
;Esta rutina prepara la recepción del
111
CONTINUAR_2:
CONTINUAR_3:
ENVIAR_PAR:
SPLK
SPLK
LAR
B
#2, CONTADOR_RX ;valor de PWM desde el PC.
#1, MODO
AR4, #PWM_TEMP
ENVIAR_DATO
SPLK
SPLK
LAR
B
#2, CONTADOR_RX
#2, MODO
AR4, #IREF_TEMP
ENVIAR_DATO
SPLK
B
#3, MODO
SPLK
LAR
LDP
B
#16, CONTADOR_TX
AR3, #KP
#0E0h
SCI_TX_ISR
SPLK
#00, CODIGO_FALLA
ENVIAR_DATO
BORRA_FALLA:
LDP
B
NUEVO_CERO
#04h
ENVIAR_DATO
;
LACL
SACL
B
IFILT
CERO
BIT
BCND
LDP
LACL
BCND
B
SCICTL2, BIT7
SCI_TX_ISR, NTC
#04h
CONTADOR_TX
CONTINUAR1, NEQ
ISR_END
CONTINUAR1:
MAR
BIT
BCND
LACC
SACH
LDP
SACL
B
*,AR3
CONTADOR_TX, 15
TX_IMPAR, TC
*+,8,AR1
*
#05h
BUFFERSCI
FIN_TX0
TX_IMPAR:
LDP
LACC
MAR
SACH
B
#05h
BUFFERSCI,8
*, AR1
*
FIN_TX0
ISR_END1:
LACL
SUB
SACL
BCND
CONTADOR_RX
#01
CONTADOR_RX
ISR_END, NEQ;
CAMBIAMODO
LACL
MODO
SUB
BCND
LACL
SACH
AND
SACL
B
LACL
SUB
BCND
LACL
SACL
B
#1
PRUEB_MODO, NEQ
PWM_TEMP
SIGN_TEMP,1
#07FFFh
PWM
ISR_END
MODO
#2
ISR_END, NEQ
IREF_TEMP
SALIDA2
ISR_END
SCI_TX_ISR:
PRUEB_MODO
ENVIAR_DATO
;Esta recibirá un valor de referencia de
;corriente y lo pasará al control
; de corriente para que la produzca.
;Aqui solo se setea el modo y se pasa al
;pedazo de rutina de Continuar_0 que envía
;los datos.
;Envía los parametros almacenados en
;el DSP. (LAR
AR3, #KP)
;Esta rutina es llamada desde el PC cuando
;detecta una falla para borrarla del codigo
;También apaga la luz de falla.
;Esta rutina invocada por el PC resetea el 0
;al valor de corriente medido en el instante,
;obviamente no se llama a esta rutina si
;se esta funcionando en un modo distinto
;de 0.
;Antes de enviar datos se prueba el bit
;que indica que se está listo para
;mandar datos.
;se carga el contador de TX y si no es
;0 se envía lo que este esperando.
;si es 0 se pasa al fin de la int.
;Aqui se hace algo analogo a la recepción.
;Esta es la rutina que fianliza para la RX
;disminuye el contador de RX y si este
;no queda en 0 pasa afinalizar la int.
;si era 0 el contador prueba en que modo
;se encuetra funcionando, por que si es 1
;ó 2 carga la ref de PWM o de Corriente
;respectivamente para ser utilizadas.
;en los modos 1 y 2 el PC manda la PWM o
;una ref de Corriente que el DSP utiliza
;para obtener las salidas.
112
FIN_TX0: LDP
LACL
SUB
SACL
ISR_END:
LDP
LACL
LACC
MAR
LAR
LST
LST
CLRC
RET
GUARDAR_TABLA_FLASH:
CALL
LDP
LACL
ADD
RETC
SPLK
SPLK
SPLK
LDP
SPLK
LAR
GRABA1
LDP
SPLK
CALL
CALL
CALL
CALL
B
LEER_TABLA_FLASH:
CALL
LDP
LACL
ADD
RETC
SPLK
SPLK
SPLK
LDP
SPLK
LAR
LEE1
CALL
CALL
CAll
SPLK
ESP6
BIT
BCND
B
GUARDAR_PARAM_FLASH:
CALL
LDP
LACL
ADD
RETC
SPLK
SPLK
SPLK
LDP
SPLK
LAR
B
LEER_PARAM_FLASH:
CALL
LDP
LACL
ADD
RETC
SPLK
SPLK
SPLK
LDP
SPLK
#04h
CONTADOR_TX
#1
CONTADOR_TX
;Esta rutina disminuye en 1 el contador TX.
#04h
ACCBAJO
ACCALTO, 16
*, AR0
AR0,#0201h
#0, *#1, *
INTM
APAGA2
#05h
CONTADORSPI_RX
CONTADORSPI_TX
NEQ
#140, CONTADORSPI_TX
#00, CONTADORSPI_RX
#00, DIRSPI
#04h
#07, CODIGO_FALLA
AR7, #TABLA_CARGA
#05h
#0, CONTADORSPI
STAT
WRITE_ENABLE
WRITE
DIRECCION
ENVIASPI
APAGA2
#05h
CONTADORSPI_RX
CONTADORSPI_TX
NEQ
#140, CONTADORSPI_RX
#00, CONTADORSPI_TX
#00, DIRSPI
#04h
#09, CODIGO_FALLA
AR7, #TABLA_CARGA
STAT
LEESPI
DIRECCION
#00, SPITXBUF
SPISTS, 9
ESP6, NTC
RECIBESPI
APAGA2
#05h
CONTADORSPI_RX
CONTADORSPI_TX
NEQ
#16, CONTADORSPI_TX
#00, CONTADORSPI_RX
#160, DIRSPI
#04h
#07, CODIGO_FALLA
AR7, #KP
GRABA1
APAGA2
#05h
CONTADORSPI_RX
CONTADORSPI_TX
NEQ
#16, CONTADORSPI_RX
#00, CONTADORSPI_TX
#160, DIRSPI
#04h
#09, CODIGO_FALLA
;Aquí se finaliza la interrupción de comm.
;y para eso se recuperan todos los datos
;relevantes.
;se habilitan nuevamente las interrupciones.
113
LAR
B
AR7, #KP
LEE1
LEER_AH_FLASH
ESCRIBIR_AH_FLAS
ENVIASPI:
CALL
LDP
LACL
ADD
RETC
SPLK
SPLK
SPLK
LDP
SPLK
LAR
B
APAGA2
CALL
DP
LACL
ADD
RETC
SPLK
SPLK
SPLK
SPLK
LDP
SPLK
LAR
B
APAGA2
#05h
CONTADORSPI_RX
CONTADORSPI_TX
NEQ
#2, CONTADORSPI_RX
#00, CONTADORSPI_TX
#180, DIRSPI
#04h
#09, CODIGO_FALLA
AR7, #AH
LEE1
#05h
CONTADORSPI_RX
CONTADORSPI_TX
NEQ
#00h, READY2
#2, CONTADORSPI_TX
#00, CONTADORSPI_RX
#180, DIRSPI
#04h
#08, CODIGO_FALLA
AR7, #AH
GRABA1
LDP
LACL
SUB
BCND
ADD
SACL
LACL
BCND
LDP
SPLK
RET
SUB
SACL
MAR
LACL
LDP
SACL
BIT
BCND
LACL
B
#05h
CONTADORSPI
#32
NUEVA_PAG, EQ
#34
CONTADORSPI
CONTADORSPI_TX
SALTO1, NEQ
#0E1h
#06020h, PCDATDIR
NUEVA_PAG
SPLK
LACL
ADD
SACL
LDP
SPLK
B
#00, CONTADORSPI
DIRSPI
#32
DIRSPI
#0E1h
#06020h, PCDATDIR
GRABA1
RECIBESPI
LDP
LACL
MAR
SACL
LDP
LACL
SUB
SACL
BCND
LDP
SPLK
RET
LDP
SPLK
BIT
BCND
B
SALTO1
ESP7
SALTO2
ESP8
#02
CONTADORSPI_TX
*, AR7
*+
#0E0h
SPITXBUF
SPISTS, 9
ESP7, NTC
SPIRXBUF
ENVIASPI
SPIRXBUF
*+
#0E0h
*, AR7
#05h
CONTADORSPI_RX
#2
CONTADORSPI_RX
SALTO2, NEQ
#0E1h
#06020h, PCDATDIR
#0E0h
#00, SPITXBUF
SPISTS, 9
ESP8, NTC
RECIBESPI
114
BAD_INT:
LST
BAD_INT2:
LDP
SPLK
LDP
SPLK
#04h
#04, CODIGO_FALLA
#0E1h
#0CF40h, PBDATDIR
;Cuando se produce una interrupción
;y no se logra identificar el periferico
;que la produjo, se llama a esta rutina
;que avisa de la situación mediante el
LDP
LACL
LACC
MAR
LAR
LST
#1, *
CLRC
RET
#04h
;codigo de falla y vuelve al
ACCBAJO
;funcionamiento normal, recuperando antes
ACCALTO, 16
;los datos de configuación.
*, AR0
AR0,#0201h
#0, *-
LDP
SPLK
LDP
SPLK
LDP
LACL
LDP
SACL
#04h
#10, CODIGO_FALLA
#0E1h
#0CF40h, PBDATDIR
#04
IFILT
#05
REGISTRO_PRUEBA
INTM
;Cuando se produce una interrupción
;y no se logra identificar el periferico
;que la produjo, se llama a esta rutina
;que avisa de la situación mediante el
LDP
#04h
;codigo de falla y vuelve al
LACL
ACCBAJO
;funcionamiento normal, recuperando antes
LACC
ACCALTO, 16
;los datos de configuación.
MAR
*, AR0
LAR
AR0,#0201h
LST
#0, *LST
#1, *
CLRC
INTM
RET
;****************************************************************************
STAT
LDP
#0E1h
SPLK
#06000h, PCDATDIR
LDP
#0E0h
SPLK
#10001111b, SPICCR
SPLK
#0500h, SPITXBUF
ESP1
BIT
SPISTS, 9
BCND
ESP1, NTC
LACL
SPIRXBUF
LDP
#0E1h
SPLK
#06020h, PCDATDIR
ROR
BCND
STAT, C
RET
WRITE_ENABLE:
ESP2
WRITE
ESP3
DIRECCION
LDP
SPLK
LDP
SPLK
SPLK
BIT
BCND
LACL
LDP
SPLK
NOP
NOP
NOP
RET
#0E1h
#06000h, PCDATDIR
#0E0h
#10000111b, SPICCR
#0600h, SPITXBUF
SPISTS, 9
ESP2, NTC
SPIRXBUF
#0E1h
#06020h, PCDATDIR
SPLK
LDP
SPLK
SPLK
BIT
BCND
LACL
NOP
NOP
RET
#06000h, PCDATDIR
#0E0h
#10000111b, SPICCR
#0200h, SPITXBUF
SPISTS, 9
ESP3, NTC
SPIRXBUF
LDP
SPLK
#0E0h
#10001111b, SPICCR
115
ESP4
LEESPI
ESP5
APAGA2
LDP
LACL
LDP
SACL
BIT
BCND
LACL
RPT
NOP
RET
LDP
SPLK
LDP
SPLK
SPLK
BIT
BCND
LACL
NOP
NOP
RET
#05h
DIRSPI
#0E0h
SPITXBUF
SPISTS, 9
ESP4, NTC
SPIRXBUF
#10
#0E1h
#06000h, PCDATDIR
#0E0h
#10000111b, SPICCR
#0300h, SPITXBUF
SPISTS, 9
ESP5, NTC
SPIRXBUF
LDP
#0E8h
SPLK
#00000h, T1CMPR
SPLK
#00000h, T2CMPR
LDP
#0E1h
SPLK
#0CF40h, PBDATDIR
RET
;=====================================================================
; I S R - PHANTOM
;
; Description:
Dummy ISR, used to trap spurious interrupts.
;=====================================================================
PHANTOM:
MAR
*,AR0
lAR
AR0,#0200h
;Phantom es una rutina de interrupción
SST
#1, *+
;solo por si se desencadena accidentalmente
SST
#0, *
;una de las interrupciones que estan
LDP
#04h
;enmascaradas.
SACL
ACCBAJO
;la situación se avisa mediante el codigo
SACH
ACCALTO
;de falla y luego se retorna al
SPLK
#05, CODIGO_FALLA
;funcionamiento normal.
LDP
#0E1h
SPLK
#0CF40h, PBDATDIR
LDP
#04
LACL
IFILT
LDP
#05
SACL
REGISTRO_PRUEBA
LDP
#04h
LACL
ACCBAJO
LACC
ACCALTO, 16
MAR
*, AR0
LAR
AR0,#0201h
LST
#0, *LST
#1, *
CLRC
INTM
RET