Modeling Physical Interconnects

Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling Physical Interconnects
(Part 3)
Dr. José Ernesto Rayas Sánchez
1
Outline
Vias
Vias in PCBs
Types of vias in PCBs
Pad and antipad
Nonfunctional pads
Modeling vias
Calculating circuit element values with formulas
Obtaining circuit element values from EM simulations
Dr. J.E. Rayas Sánchez
2
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Vias
They implement the vertical connections (conductive
columns to connect traces on different layers)
Vias exist at many physical levels:
(R. Mellitz, 2003) 3
Dr. J.E. Rayas Sánchez
Vias in PCBs
They are formed by drilling a hole (either mechanically
or with a laser)
Blind via: a via not passing through the complete PCB
Through hole via: a via passing through the entire PCB
stackup
Buried via: a via connecting internal layers
Conducting vias are “plated” with copper
Plated through hole (PTH): conductive via passing
through the entire PCB stackup
Dr. J.E. Rayas Sánchez
4
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Types of Vias in PCBs
(R. Mellitz, 2003) 5
Dr. J.E. Rayas Sánchez
PCB Stackup
Example showing a 6-layer stackup
Dr. J.E. Rayas Sánchez
(S. C. Thierauf, High-Speed Circuit Board Signal Integrity, Artech, 2004)
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
6
Signal Integrity and High-Speed Interconnects
January-May 2006
Vias in the PCB Stackup
Dr. J.E. Rayas Sánchez
(S. C. Thierauf, High-Speed Circuit Board Signal Integrity, Artech, 2004)
7
Pad or Land
A ring of copper that surrounds a plated via (to ensure
electrical contact to traces even if there is some misalignment)
Dr. J.E. Rayas Sánchez
(S. C. Thierauf, High-Speed Circuit Board Signal Integrity, Artech, 2004)
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
8
Signal Integrity and High-Speed Interconnects
January-May 2006
Antipad
A hole in the power/ground plane to avoid electrical contact
Dr. J.E. Rayas Sánchez
(S. C. Thierauf, High-Speed Circuit Board Signal Integrity, Artech, 2004)
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Vias Connecting to Power/Ground Planes
Small copper fingers are used for thermal isolation
Dr. J.E. Rayas Sánchez
(S. C. Thierauf, High-Speed Circuit Board Signal Integrity, Artech, 2004) 10
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Nonfunctional Pads
They are used to
anchor the via to the
laminate
They increase
unwanted capacitive
coupling to
ground/power planes
☺
Increasing the antipad
decreases the coupling
Dr. J.E. Rayas Sánchez
(S. C. Thierauf, High-Speed Circuit Board Signal Integrity, Artech, 2004) 11
Modeling Vias
If the via is electrically small (if td(via) > 0.1tt), it can be
modeled with a lumped circuit
(R. Mellitz, 2003) 12
Dr. J.E. Rayas Sánchez
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling Vias (cont)
If the via is electrically small (if td(via) > 0.1tt), it can be
modeled with a lumped circuit
Lbarrel
Cpad
Lbarrel = 5.08h[ln(4h / d ) + 1] (nH)
Cpad
C pad =
1.41ε r D1T
(pF)
D2 − D1
D1 : pad diameter (in)
D2 : antipad diameter (in)
T : thickness of PCB (in)
εr: relative permeability of the PCB
h: via length (in)
d: via diameter (in)
Dr. J.E. Rayas Sánchez
(H. Johnson and M. Graham, High-Speed Digital Design, Prentice Hall, 1993) 13
Alternative Formula for the Via Inductance
If the via is electrically small (if td(via) > 0.1tt), it can be
modeled with a lumped circuit
Lbarrel
Cpad
Cpad
Lbarrel =
µ0
2π
⎡ ⎛ h + r 2 + h2 ⎞
⎤
⎟⎟ + r − r 2 + h 2 ⎥
⎢h ln⎜⎜
r
⎠
⎣ ⎝
⎦
h: via length (m)
r: via radius (m)
Dr. J.E. Rayas Sánchez
(M.E. Goldfarb and R.A. Pucel, 1991) 14
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling Vias – Example
(R. Mellitz, 2003) 15
Dr. J.E. Rayas Sánchez
Modeling a Plated Through Hole Via (PTH)
(R. Mellitz, 2003) 16
Dr. J.E. Rayas Sánchez
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Via Modeling though EM Simulation
Some electromagnetic simulators have the capability of
automatically synthesizing a lumped circuit model using
inductors, capacitors, resistors and mutual inductors
The equivalent circuit is usually provided in SPICE format
This method is intended for any electrically small circuit
(small with respect to the wavelength at the highest
frequency of excitation)
By using this approach, we can develop very accurate
models of vias (with arbitrary geometries), without relying
on empirical formulas
Dr. J.E. Rayas Sánchez
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Modeling a Squared Grounded Via Using Sonnet
(top layer)
Dr. J.E. Rayas Sánchez
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Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
(bottom layer, ground)
Dr. J.E. Rayas Sánchez
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Modeling a Squared Via Using Sonnet (cont)
w
D
FR4
D
h
w = 50mil
D = 80mil
H = 100mil
εr = 4.3
loss tan = 0.025
Dr. J.E. Rayas Sánchez
20
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
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Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
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Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
23
Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
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Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
200MHz
Dr. J.E. Rayas Sánchez
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Modeling a Squared Via Using Sonnet (cont)
13.8GHz
Dr. J.E. Rayas Sánchez
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Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
20GHz
Dr. J.E. Rayas Sánchez
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Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
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Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
29
Modeling a Squared Via Using Sonnet (cont)
Dr. J.E. Rayas Sánchez
30
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
Lumped Circuit Model of a Squared Via
0.9
0.8
L
0.7
0.6
R
L (nH)
C
0.5
0.4
0.3
L ≅ 808 µH
0.2
(circuit model
above 5GHz is
useless)
0.1
0
0
2
4
6
8
10
12
14
16
18
20
frequency (GHz)
Dr. J.E. Rayas Sánchez
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Modeling a Squared Via Using Sonnet (cont)
Lumped Circuit Model of a Squared Via
2.5
L
R
1.5
C (pF)
C
2
1
C ≅ 0.11 pF
0.5
(circuit model
above 5GHz is
useless)
0
0
2
4
6
8
10
12
14
16
18
20
frequency (GHz)
Dr. J.E. Rayas Sánchez
32
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]
Signal Integrity and High-Speed Interconnects
January-May 2006
Modeling a Squared Via Using Sonnet (cont)
Lumped Circuit Model of a Squared Via
4
3
L
2
1
R
R (ohms)
C
0
-1
-2
R≅0Ω
-3
(circuit model
above 5GHz is
useless)
-4
-5
-6
0
2
4
6
8
10
12
14
16
18
20
frequency (GHz)
Dr. J.E. Rayas Sánchez
33
Estimating L with Formulas
Taking h = 100mil, d = 50mil
Using Johnson’s formula:
Lbarrel = 5.08h[ln(4h / d ) + 1] = 1.5644 nH
Using Goldfarb’s formula: (r = d/2)
Lbarrel =
µ0
2π
⎤
⎡ ⎛ h + r 2 + h2 ⎞
⎟⎟ + r − r 2 + h 2 ⎥ = 0.6675 nH
⎢h ln⎜⎜
r
⎠
⎦
⎣ ⎝
Dr. J.E. Rayas Sánchez
34
Dr. J. E. Rayas Sánchez
http://iteso.mx/~erayas [email protected]