use ieee.std_logic_1164.all

-- Compuerta XNOR2
-- XNOR2 es una entidad que genera la salida de una compuerta XNOR
library ieee;
use ieee.std_logic_1164.all;
entity XNOR2 is
port (
a, b:
in std_logic; -- a, b son las entradas
q:
out std_logic); -- q es la salida
end XNOR2;
architecture struct of XNOR2 is
begin
q <= a XNOR b;
end struct;
-- Compuerta AND4
-- AND es una entidad que genera la salida de una compuerta AND de 4 entradas
library ieee;
use ieee.std_logic_1164.all;
entity AND4 is
port (
a, b, c, d:
in std_logic; -- a, b, c, d son las entradas
s:
out std_logic); -- q es la salida
end AND4;
architecture struct of AND4 is
begin
s <= (a AND b) AND (c AND d);
end struct;
-- Comparador eqcomp4
-- eqcomp4 es un comparador de igualdad de cuatro bits
library ieee;
use ieee.std_logic_1164.all;
entity eqcomp4 is
port (
a, b:
in std_logic_vector(3 downto 0);
-- a, b son las entradas
equals:
out std_logic);
-- equals es la salida
end eqcomp4;
architecture struct of eqcomp4 is
component AND4 port (
--Declara una compuerta AND de 4 entradas
a,b,c,d:
in std_logic;
s
:
out std_logic);
end component;
component XNOR2 port (
--Declara una compuerta XNOR de 2 entradas
a,b:
in std_logic;
q:
out std_logic);
end component;
signal x: std_logic_vector (0 to 3);
begin
u0: XNOR2 port map (a(0), b(0), x(0));
u1: XNOR2 port map (a(1), b(1), x(1));
u2: XNOR2 port map (a(2), b(2), x(2));
u3: XNOR2 port map (a(3), b(3), x(3));
u4: AND4 port map (x(0), x(1), x(2), x(3), equals);
end struct;